From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by sourceware.org (Postfix) with ESMTPS id CA6F3384F02F for ; Wed, 9 Nov 2022 07:15:08 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org CA6F3384F02F Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1667978108; x=1699514108; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=PixhRrW6S+MyOgu0xUF0AF22u0SGGlnvfX2ykkyD6dQ=; b=h70USN2H6PtAbNEjajNMxfvVN9Mb7zjXTfYR0DYytr1LcIdQ2ff7KTdh 3IylBKuj1lwdl1EgIQ3/KCAPjkH85U29Wx9kF0Kbdg1S7u6n4K6Jzo08D CBthirIS8isXxF6TE3hEa35nThc7y1TAK8e5DI2M0bqNQ+tChAYMiK95G lJUcqDTIUNsC44T9CcqjOiSagmtLVV1htfuw6bAdIvBxwWrsvLE5MVPgp iL62daXFItRjMAp/73L7R/gFxEr+BSEisKnLeqoCdnK89EhXyEsZEX7v+ lhRaIgNTlR14QrA9hKDGqEtFgajd2AFT0U/4++A7mcjnAf2Im+LSH0RY5 Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10525"; a="291297612" X-IronPort-AV: E=Sophos;i="5.96,149,1665471600"; d="scan'208";a="291297612" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Nov 2022 23:15:07 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10525"; a="587668846" X-IronPort-AV: E=Sophos;i="5.96,149,1665471600"; d="scan'208";a="587668846" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga003.jf.intel.com with ESMTP; 08 Nov 2022 23:15:04 -0800 Received: from shliclel320.sh.intel.com (shliclel320.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 7017110056F9; Wed, 9 Nov 2022 15:15:03 +0800 (CST) From: Haochen Jiang To: gcc-patches@gcc.gnu.org Cc: ubizjak@gmail.com, jakub@redhat.com, hongtao.liu@intel.com Subject: [PATCH] i386: Add ISA check for newly introduced prefetch builtins. Date: Wed, 9 Nov 2022 15:13:02 +0800 Message-Id: <20221109071302.78435-1-haochen.jiang@intel.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: References: X-Spam-Status: No, score=-11.2 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hi all, As Hongtao said, the fail on pentiumpro is caused by missing ISA check since we are using emit_insn () through new builtins and it won't check if the TARGET matches. Previously, the builtin in middle-end will check that. On pentiumpro, we won't have anything that supports any prefetch so that it dropped into the pattern and then failed. I have added the restrictions just like what middle-end builtin_prefetch does. Also I added missing checks for PREFETCHI. Ok for trunk? BRs, Haochen gcc/ChangeLog: * config/i386/i386-builtin.def (BDESC): Add OPTION_MASK_ISA2_PREFETCHI for prefetchi builtin. * config/i386/i386-expand.cc (ix86_expand_builtin): Add ISA check before emit_insn. * config/i386/prfchiintrin.h: Add target for intrin. gcc/testsuite/ChangeLog: * gcc.target/i386/prefetchi-5.c: New test. --- gcc/config/i386/i386-builtin.def | 2 +- gcc/config/i386/i386-expand.cc | 11 +++++++++-- gcc/config/i386/prfchiintrin.h | 14 +++++++++++++- gcc/testsuite/gcc.target/i386/prefetchi-5.c | 4 ++++ 4 files changed, 27 insertions(+), 4 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/prefetchi-5.c diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def index ea3aff7f125..5e0461acc00 100644 --- a/gcc/config/i386/i386-builtin.def +++ b/gcc/config/i386/i386-builtin.def @@ -498,7 +498,7 @@ BDESC (0, OPTION_MASK_ISA2_WIDEKL, CODE_FOR_nothing, "__builtin_ia32_aesencwide1 BDESC (0, OPTION_MASK_ISA2_WIDEKL, CODE_FOR_nothing, "__builtin_ia32_aesencwide256kl_u8", IX86_BUILTIN_AESENCWIDE256KLU8, UNKNOWN, (int) UINT8_FTYPE_PV2DI_PCV2DI_PCVOID) /* PREFETCHI */ -BDESC (0, 0, CODE_FOR_prefetchi, "__builtin_ia32_prefetchi", IX86_BUILTIN_PREFETCHI, UNKNOWN, (int) VOID_FTYPE_PCVOID_INT) +BDESC (0, OPTION_MASK_ISA2_PREFETCHI, CODE_FOR_prefetchi, "__builtin_ia32_prefetchi", IX86_BUILTIN_PREFETCHI, UNKNOWN, (int) VOID_FTYPE_PCVOID_INT) BDESC (0, 0, CODE_FOR_nothing, "__builtin_ia32_prefetch", IX86_BUILTIN_PREFETCH, UNKNOWN, (int) VOID_FTYPE_PCVOID_INT_INT_INT) BDESC_END (SPECIAL_ARGS, PURE_ARGS) diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc index 9c92b07d5cd..0e45c195390 100644 --- a/gcc/config/i386/i386-expand.cc +++ b/gcc/config/i386/i386-expand.cc @@ -13131,7 +13131,7 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget, if (INTVAL (op3) == 1) { - if (TARGET_64BIT + if (TARGET_64BIT && TARGET_PREFETCHI && local_func_symbolic_operand (op0, GET_MODE (op0))) emit_insn (gen_prefetchi (op0, op2)); else @@ -13150,7 +13150,14 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget, op0 = convert_memory_address (Pmode, op0); op0 = copy_addr_to_reg (op0); } - emit_insn (gen_prefetch (op0, op1, op2)); + + if (TARGET_3DNOW || TARGET_PREFETCH_SSE + || TARGET_PRFCHW || TARGET_PREFETCHWT1) + emit_insn (gen_prefetch (op0, op1, op2)); + else if (!MEM_P (op0) && side_effects_p (op0)) + /* Don't do anything with direct references to volatile memory, + but generate code to handle other side effects. */ + emit_insn (op0); } return 0; diff --git a/gcc/config/i386/prfchiintrin.h b/gcc/config/i386/prfchiintrin.h index 06deef488ba..996a4be1aba 100644 --- a/gcc/config/i386/prfchiintrin.h +++ b/gcc/config/i386/prfchiintrin.h @@ -30,6 +30,13 @@ #ifdef __x86_64__ + +#ifndef __PREFETCHI__ +#pragma GCC push_options +#pragma GCC target("prefetchi") +#define __DISABLE_PREFETCHI__ +#endif /* __PREFETCHI__ */ + extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__)) _m_prefetchit0 (void* __P) @@ -44,6 +51,11 @@ _m_prefetchit1 (void* __P) __builtin_ia32_prefetchi (__P, 2); } -#endif +#ifdef __DISABLE_PREFETCHI__ +#undef __DISABLE_PREFETCHI__ +#pragma GCC pop_options +#endif /* __DISABLE_PREFETCHI__ */ + +#endif /* __x86_64__ */ #endif /* _PRFCHIINTRIN_H_INCLUDED */ diff --git a/gcc/testsuite/gcc.target/i386/prefetchi-5.c b/gcc/testsuite/gcc.target/i386/prefetchi-5.c new file mode 100644 index 00000000000..8c26540f96a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/prefetchi-5.c @@ -0,0 +1,4 @@ +/* { dg-do compile { target { ia32 } } } */ +/* { dg-options "-O0 -march=pentiumpro" } */ + +#include "prefetchi-4.c" -- 2.18.1