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From: Philipp Tomsich <philipp.tomsich@vrull.eu>
To: gcc-patches@gcc.gnu.org
Cc: Richard Biener <rguenther@suse.de>,
	Jiang-Ning Liu <jiangning.liu@amperecomputing.com>,
	Jeff Law <jlaw@ventanamicro.com>,
	Tamar Christina <tamar.christina@arm.com>,
	Christoph Muellner <christoph.muellner@vrull.eu>,
	Philipp Tomsich <philipp.tomsich@vrull.eu>
Subject: [PATCH] ifcombine: recognize single bit test of sign-bit
Date: Thu, 10 Nov 2022 00:07:47 +0100	[thread overview]
Message-ID: <20221109230747.3240551-1-philipp.tomsich@vrull.eu> (raw)

Our ifcombine pass combines 2 single-bit tests into a single test of
the form "(a & T) == T".

However, detection of the bit-tests does not work for sign-bits (of
any mode) as the RTL presented to the pass uses a cast to a
signed-type and an order-operator.  E.g., the test for 'a & 0x80'
presents as:
    _1 = *a_5(D);
    _2 = (signed char) _1;
    if (_2 < 0)
      goto <bb 3>;
    else
      goto <bb 5>;

This adds detection logic to recognize_single_bit_test() for this case
and reports it as a single-bit test.

gcc/ChangeLog:

	* tree-ssa-ifcombine.cc (recognize_single_bit_test): Add
          detection for tests against the sign-bit of the relevant
          type as a single-bit test.

gcc/testsuite/ChangeLog:

	* gcc.dg/tree-ssa/ssa-ifcombine-14.c: New test.

Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
---

 .../gcc.dg/tree-ssa/ssa-ifcombine-14.c        | 14 +++++++++++++
 gcc/tree-ssa-ifcombine.cc                     | 20 +++++++++++++++++++
 2 files changed, 34 insertions(+)
 create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/ssa-ifcombine-14.c

diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-ifcombine-14.c b/gcc/testsuite/gcc.dg/tree-ssa/ssa-ifcombine-14.c
new file mode 100644
index 00000000000..f9b1115a34a
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-ifcombine-14.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O -fdump-tree-ifcombine-details-blocks" } */
+
+void sink();
+
+void same(unsigned char *a)
+{
+  if (*a & 0x80)
+    if (*a & 0x40)
+      g();
+}
+
+/* { dg-final { scan-tree-dump "optimizing double bit test" } } */
+
diff --git a/gcc/tree-ssa-ifcombine.cc b/gcc/tree-ssa-ifcombine.cc
index 80c41c45489..cd6331f84db 100644
--- a/gcc/tree-ssa-ifcombine.cc
+++ b/gcc/tree-ssa-ifcombine.cc
@@ -225,6 +225,26 @@ recognize_single_bit_test (gcond *cond, tree *name, tree *bit, bool inv)
 {
   gimple *stmt;
 
+  /* Handle the test for a sign-bit:
+       unsigned charD.15 _1;
+       _2 = (signed char) _1;
+       if (_2 < 0) */
+  if (TREE_CODE (gimple_cond_lhs (cond)) == SSA_NAME
+      && !TYPE_UNSIGNED (TREE_TYPE (gimple_cond_lhs (cond)))
+      && gimple_cond_code (cond) == (inv ? GE_EXPR : LT_EXPR)
+      && integer_zerop (gimple_cond_rhs (cond)))
+    {
+      tree type = TREE_TYPE (gimple_cond_lhs (cond));
+
+      stmt = SSA_NAME_DEF_STMT (gimple_cond_lhs (cond));
+      if (!is_gimple_assign (stmt))
+	return false;
+      *name = gimple_assign_rhs1 (stmt);
+      *bit = build_int_cst (integer_type_node, TYPE_PRECISION (type) - 1);
+
+      return true;
+    }
+
   /* Get at the definition of the result of the bit test.  */
   if (gimple_cond_code (cond) != (inv ? EQ_EXPR : NE_EXPR)
       || TREE_CODE (gimple_cond_lhs (cond)) != SSA_NAME
-- 
2.34.1


             reply	other threads:[~2022-11-09 23:08 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-09 23:07 Philipp Tomsich [this message]
2022-11-10  6:57 ` Richard Biener

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