From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by sourceware.org (Postfix) with ESMTPS id C930E3858D1E for ; Thu, 10 Nov 2022 06:03:54 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org C930E3858D1E Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1668060234; x=1699596234; h=from:to:subject:date:message-id; bh=cHPGcxyqmNFcrjQ40fJc5zGlxMiMjF2ZBH6LUkEenLg=; b=fH5nTpH2VvkZa/OdR5D/BvCpI2ZVCXvvcmflmRuPfUQefe0D0EXhSoUS Qpj9FvWrC3rX1GVIfk4PDcbe0QUgeHuQrZTXkF0oV4D5ZNlxbGGdbgJVC vcRf/zx5qnCo3EXtnxkE5EKwudJw9MwQ6uMizkLALGgWJIfpOOMKFWMv7 qSnReZbsRDIELDoa5+DJSurN9qKSUCp7jy976qAfiMLQ9WFlIAUF5pceV lFCWxLBCw/+QmR4FO4SECBnqTkCChJRhiZrG27kfaV/mc6SlZHtbmS9ax hLqLmcx8xhDMBDNXmiqbjOrdQsKP4rDR5ZdpTkaJ3OUwyW5JcPB/3n1o0 Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10526"; a="309937241" X-IronPort-AV: E=Sophos;i="5.96,152,1665471600"; d="scan'208";a="309937241" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Nov 2022 22:03:45 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10526"; a="811913922" X-IronPort-AV: E=Sophos;i="5.96,152,1665471600"; d="scan'208";a="811913922" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga005.jf.intel.com with ESMTP; 09 Nov 2022 22:03:44 -0800 Received: from shliclel320.sh.intel.com (shliclel320.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id B76901005703 for ; Thu, 10 Nov 2022 14:03:43 +0800 (CST) From: Haochen Jiang To: gcc-patches@gcc.gnu.org Subject: [wwwdocs] gcc-13: Mention Intel new ISA and march support. Date: Thu, 10 Nov 2022 14:01:43 +0800 Message-Id: <20221110060143.28132-1-haochen.jiang@intel.com> X-Mailer: git-send-email 2.18.1 X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hi all, This patch aims to mention newly added Intel ISA and march support. Ok for trunk? BRs, Haochen --- htdocs/gcc-13/changes.html | 50 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/htdocs/gcc-13/changes.html b/htdocs/gcc-13/changes.html index bd11cbec..0daf921b 100644 --- a/htdocs/gcc-13/changes.html +++ b/htdocs/gcc-13/changes.html @@ -240,6 +240,56 @@ a work-in-progress.

__bf16 type to x86 psABI. Users need to adjust their AVX512BF16-related source code when upgrading GCC12 to GCC13. +
  • New ISA extension support for Intel AVX-IFMA was added to GCC. + AVX-IFMA intrinsics are available via the -mavxifma + compiler switch. +
    • +
  • New ISA extension support for Intel AVX-VNNI-INT8 was added to GCC. + AVX-VNNI-INT8 intrinsics are available via the -mavxvnniint8 + compiler switch. +
    • +
  • New ISA extension support for Intel AVX-NE-CONVERT was added to GCC. + AVX-NE-CONVERT intrinsics are available via the + -mavxneconvert compiler switch. +
    • +
  • New ISA extension support for Intel CMPccXADD was added to GCC. + CMPccXADD intrinsics are available via the -mcmpccxadd + compiler switch. +
    • +
  • New ISA extension support for Intel AMX-FP16 was added to GCC. + AMX-FP16 intrinsics are available via the -mamx-fp16 + compiler switch. +
    • +
  • New ISA extension support for Intel PREFETCHI was added to GCC. + PREFETCHI intrinsics are available via the -mprefetchi + compiler switch. +
    • +
  • New ISA extension support for Intel RAO-INT was added to GCC. + RAO-INT intrinsics are available via the -mraoint + compiler switch. +
    • +
  • GCC now supports the Intel CPU named Raptor Lake through + -march=raptorlake. + Raptor Lake is based on Alder Lake. +
    • +
  • GCC now supports the Intel CPU named Meteor Lake through + -march=meteorlake. + Meteor Lake is based on Alder Lake. +
    • +
  • GCC now supports the Intel CPU named Sierra Forest through + -march=sierraforest. + The switch enables the AVX-IFMA, AVX-VNNI-INT8, AVX-NE-CONVERT and + CMPccXADD ISA extensions. +
    • +
  • GCC now supports the Intel CPU named Grand Ridge through + -march=grandridge. + The switch enables the AVX-IFMA, AVX-VNNI-INT8, AVX-NE-CONVERT, CMPccXADD + and RAO-INT ISA extensions. +
    • +
  • GCC now supports the Intel CPU named Granite Rapids through + -march=graniterapids. + The switch enables the AMX-FP16 and PREFETCHI ISA extensions. +
    • -- 2.18.1