From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by sourceware.org (Postfix) with ESMTPS id ED91F3858D20 for ; Fri, 11 Nov 2022 01:26:46 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org ED91F3858D20 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1668130007; x=1699666007; h=from:to:cc:subject:date:message-id; bh=UBaZsBiw5cce6sSSDIM69THYjQTpTKbRoBNmTUuKfwY=; b=MDBbrgzi7eefnU7aJFYaeMkApK2/b8fK0kd+EMxn1+7twW6O+MGDS58m L+K0t5YgPtBuuciwGwVN4KGfOcZLd8ZWrCy7Rz8HDfS8FsZXvL/NGwTHf uIsiMujBRYBSDdX7+H6wbedNlV4DTgJGhx0lkS1uaOeNBpGZvYF6uhBQX Iyskgk7vgmh398k2a0Sem4o+PIBQgwPMOULwzy66bqBNUR3iMg5vQaAB7 EN05JzKEo8ax0+jPd9+htSb3Bdaq4EJQulKi3UbiGvynAeCRbLY56G+Cy 0wSOcVDVdXb8FbrEug40ftofwJHf7kePGV2+byNz7n/eh6heKY5W4trA5 Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10527"; a="309117820" X-IronPort-AV: E=Sophos;i="5.96,155,1665471600"; d="scan'208";a="309117820" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Nov 2022 17:26:34 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10527"; a="762498212" X-IronPort-AV: E=Sophos;i="5.96,155,1665471600"; d="scan'208";a="762498212" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga004.jf.intel.com with ESMTP; 10 Nov 2022 17:26:31 -0800 Received: from shliclel320.sh.intel.com (shliclel320.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 39A0D100571B; Fri, 11 Nov 2022 09:26:31 +0800 (CST) From: liuhongt To: gcc-patches@gcc.gnu.org Cc: crazylht@gmail.com, hjl.tools@gmail.com, ubizjak@gmail.com Subject: [PATCH 0/2] Support HWASAN with Intel LAM Date: Fri, 11 Nov 2022 09:26:29 +0800 Message-Id: <20221111012631.76776-1-hongtao.liu@intel.com> X-Mailer: git-send-email 2.18.1 X-Spam-Status: No, score=-6.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,KAM_SHORT,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: 2 years ago, ARM folks support HWASAN[1] in GCC[2], and introduced several target hooks(Many thanks to their work) so other backends can do similar things if they have similar feature. Intel LAM(linear Address Masking)[3 Charpter 14] supports similar feature with the upper bits of pointers can be used as metadata, LAM support two modes: LAM_U48:bits 48-62 can be used as metadata LAM_U57:bits 57-62 can be used as metedata. These 2 patches mainly support those target hooks, but HWASAN is not really enabled until the final decision for the LAM kernel interface which may take quite a long time. We have verified our patches with a "fake" interface locally[4], and decided to push the backend patches to the GCC13 to make other HWASAN developper's work easy. [1] https://clang.llvm.org/docs/HardwareAssistedAddressSanitizerDesign.html [2] https://gcc.gnu.org/pipermail/gcc-patches/2020-November/557857.html [3] https://www.intel.com/content/dam/develop/external/us/en/documents/architecture-instruction-set-extensions-programming-reference.pdf [4] https://gitlab.com/x86-gcc/gcc/-/tree/users/intel/lam/master Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}. Ok for trunk? liuhongt (2): Implement hwasan target_hook. Enable hwasan for x86-64. gcc/config/i386/i386-expand.cc | 12 ++++ gcc/config/i386/i386-options.cc | 3 + gcc/config/i386/i386-opts.h | 6 ++ gcc/config/i386/i386-protos.h | 2 + gcc/config/i386/i386.cc | 123 ++++++++++++++++++++++++++++++++ gcc/config/i386/i386.opt | 16 +++++ libsanitizer/configure.tgt | 1 + 7 files changed, 163 insertions(+) -- 2.18.1