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([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id b9-20020a0565120b8900b004a4251c7f75sm1042967lfv.202.2022.11.12.13.29.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 12 Nov 2022 13:29:46 -0800 (PST) From: Philipp Tomsich To: gcc-patches@gcc.gnu.org Cc: Vineet Gupta , Palmer Dabbelt , Christoph Muellner , Kito Cheng , Jeff Law , Philipp Tomsich Subject: [PATCH 0/7] RISC-V: Backend support for XVentanaCondOps/ZiCondops Date: Sat, 12 Nov 2022 22:29:36 +0100 Message-Id: <20221112212943.3068249-1-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-6.3 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,JMQ_SPF_NEUTRAL,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Both the XVentanaCondOps (a vendor-defined extension from Ventana Microsystems) and the proposed ZiCondOps extensions define a conditional-zero(-or-value) instruction, which is similar to the following C construct: rd = rc ? rs : 0 This functionality can be tied back into if-convertsion and also match some typical programming idioms. This series includes backend support for XVentanaCondops and infrastructure to handle conditional-zero constructions in if-conversion. Tested against SPEC CPU 2017. Philipp Tomsich (7): RISC-V: Recognize xventanacondops extension RISC-V: Generate vt.maskc on noce_try_store_flag_mask if-conversion RISC-V: Support noce_try_store_flag_mask as vt.maskc RISC-V: Recognize sign-extract + and cases for XVentanaCondOps RISC-V: Recognize bexti in negated if-conversion RISC-V: Support immediates in XVentanaCondOps ifcvt: add if-conversion to conditional-zero instructions gcc/common/config/riscv/riscv-common.cc | 2 + gcc/config/riscv/predicates.md | 12 + gcc/config/riscv/riscv-opts.h | 3 + gcc/config/riscv/riscv.cc | 14 ++ gcc/config/riscv/riscv.md | 27 +++ gcc/config/riscv/riscv.opt | 3 + gcc/config/riscv/xventanacondops.md | 150 ++++++++++++ gcc/ifcvt.cc | 214 ++++++++++++++++++ .../gcc.target/riscv/xventanacondops-and-01.c | 16 ++ .../gcc.target/riscv/xventanacondops-and-02.c | 15 ++ .../gcc.target/riscv/xventanacondops-eq-01.c | 11 + .../gcc.target/riscv/xventanacondops-eq-02.c | 14 ++ .../riscv/xventanacondops-ifconv-imm.c | 19 ++ .../gcc.target/riscv/xventanacondops-le-01.c | 17 ++ .../gcc.target/riscv/xventanacondops-lt-01.c | 16 ++ .../gcc.target/riscv/xventanacondops-lt-03.c | 17 ++ .../gcc.target/riscv/xventanacondops-ne-01.c | 11 + .../gcc.target/riscv/xventanacondops-ne-03.c | 15 ++ .../gcc.target/riscv/xventanacondops-ne-04.c | 15 ++ .../gcc.target/riscv/xventanacondops-xor-01.c | 14 ++ 20 files changed, 605 insertions(+) create mode 100644 gcc/config/riscv/xventanacondops.md create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-and-01.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-and-02.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-eq-01.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-eq-02.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-ifconv-imm.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-le-01.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-lt-01.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-lt-03.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-ne-01.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-ne-03.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-ne-04.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-xor-01.c -- 2.34.1