From: Philipp Tomsich <philipp.tomsich@vrull.eu>
To: gcc-patches@gcc.gnu.org
Cc: Vineet Gupta <vineetg@rivosinc.com>,
Kito Cheng <kito.cheng@gmail.com>,
Christoph Muellner <christoph.muellner@vrull.eu>,
Jeff Law <jlaw@ventanamicro.com>,
Palmer Dabbelt <palmer@rivosinc.com>,
Philipp Tomsich <philipp.tomsich@vrull.eu>
Subject: [PATCH] RISC-V: Split "(a & (1UL << bitno)) ? 0 : -1" to bext + addi
Date: Sun, 13 Nov 2022 21:48:40 +0100 [thread overview]
Message-ID: <20221113204840.4062092-1-philipp.tomsich@vrull.eu> (raw)
For a straightforward application of bext for the following function
long bext64(long a, char bitno)
{
return (a & (1UL << bitno)) ? 0 : -1;
}
we generate
srl a0,a0,a1 # 7 [c=4 l=4] lshrdi3
andi a0,a0,1 # 8 [c=4 l=4] anddi3/1
addi a0,a0,-1 # 14 [c=4 l=4] adddi3/1
due to the following failed match at combine time:
(set (reg:DI 82)
(zero_extract:DI (reg:DI 83)
(const_int 1 [0x1])
(reg:DI 84)))
The existing pattern for bext requires the 3rd argument to
zero_extract to be a QImode register wrapped in a zero_extension.
This adds an additional pattern that allows an Xmode argument.
With this change, the testcase compiles to
bext a0,a0,a1 # 8 [c=4 l=4] *bextdi
addi a0,a0,-1 # 14 [c=4 l=4] adddi3/1
gcc/ChangeLog:
* config/riscv/bitmanip.md (*bext<mode>): Add an additional
pattern that allows the 3rd argument to zero_extract to be
an Xmode register operand.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/zbs-bext.c: Add testcases.
* gcc.target/riscv/zbs-bexti.c: Add testcases.
Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
---
gcc/config/riscv/bitmanip.md | 12 +++++++++++
gcc/testsuite/gcc.target/riscv/zbs-bext.c | 23 +++++++++++++++++---
gcc/testsuite/gcc.target/riscv/zbs-bexti.c | 25 ++++++++++++++++------
3 files changed, 50 insertions(+), 10 deletions(-)
diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index f1d8f24c2d3..8222c600ca5 100644
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -644,6 +644,18 @@
"bext\t%0,%1,%2"
[(set_attr "type" "bitmanip")])
+;; When performing `(a & (1UL << bitno)) ? 0 : -1` the combiner
+;; usually has the `bitno` typed as X-mode (i.e. no further
+;; zero-extension is performed around the bitno).
+(define_insn "*bext<mode>"
+ [(set (match_operand:X 0 "register_operand" "=r")
+ (zero_extract:X (match_operand:X 1 "register_operand" "r")
+ (const_int 1)
+ (match_operand:X 2 "register_operand" "r")))]
+ "TARGET_ZBS"
+ "bext\t%0,%1,%2"
+ [(set_attr "type" "bitmanip")])
+
(define_insn "*bexti"
[(set (match_operand:X 0 "register_operand" "=r")
(zero_extract:X (match_operand:X 1 "register_operand" "r")
diff --git a/gcc/testsuite/gcc.target/riscv/zbs-bext.c b/gcc/testsuite/gcc.target/riscv/zbs-bext.c
index 47982396119..8de9c5a167c 100644
--- a/gcc/testsuite/gcc.target/riscv/zbs-bext.c
+++ b/gcc/testsuite/gcc.target/riscv/zbs-bext.c
@@ -1,6 +1,6 @@
/* { dg-do compile } */
/* { dg-options "-march=rv64gc_zbs -mabi=lp64" } */
-/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
/* bext */
long
@@ -16,6 +16,23 @@ foo1 (long i)
return 1L & (i >> 20);
}
+long bext64_1(long a, char bitno)
+{
+ return (a & (1UL << bitno)) ? 1 : 0;
+}
+
+long bext64_2(long a, char bitno)
+{
+ return (a & (1UL << bitno)) ? 0 : -1;
+}
+
+long bext64_3(long a, char bitno)
+{
+ return (a & (1UL << bitno)) ? -1 : 0;
+}
+
/* { dg-final { scan-assembler-times "bexti\t" 1 } } */
-/* { dg-final { scan-assembler-times "bext\t" 1 } } */
-/* { dg-final { scan-assembler-not "andi" } } */
+/* { dg-final { scan-assembler-times "bext\t" 4 } } */
+/* { dg-final { scan-assembler-times "addi\t" 1 } } */
+/* { dg-final { scan-assembler-times "neg\t" 1 } } */
+/* { dg-final { scan-assembler-not "andi" } } */
\ No newline at end of file
diff --git a/gcc/testsuite/gcc.target/riscv/zbs-bexti.c b/gcc/testsuite/gcc.target/riscv/zbs-bexti.c
index 99e3b58309c..30b69c9bc3e 100644
--- a/gcc/testsuite/gcc.target/riscv/zbs-bexti.c
+++ b/gcc/testsuite/gcc.target/riscv/zbs-bexti.c
@@ -1,14 +1,25 @@
/* { dg-do compile } */
-/* { dg-options "-march=rv64gc_zbs -mabi=lp64 -O2" } */
+/* { dg-options "-march=rv64gc_zbs -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
/* bexti */
-#define BIT_NO 4
+#define BIT_NO 21
-long
-foo0 (long a)
+long bexti64_1(long a, char bitno)
{
- return (a & (1 << BIT_NO)) ? 0 : -1;
+ return (a & (1UL << BIT_NO)) ? 1 : 0;
}
-/* { dg-final { scan-assembler "bexti" } } */
-/* { dg-final { scan-assembler "addi" } } */
+long bexti64_2(long a, char bitno)
+{
+ return (a & (1UL << BIT_NO)) ? 0 : -1;
+}
+
+long bexti64_3(long a, char bitno)
+{
+ return (a & (1UL << BIT_NO)) ? -1 : 0;
+}
+
+/* { dg-final { scan-assembler-times "bexti\t" 3 } } */
+/* { dg-final { scan-assembler-times "addi\t" 1 } } */
+/* { dg-final { scan-assembler-times "neg\t" 1 } } */
--
2.34.1
next reply other threads:[~2022-11-13 20:48 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-13 20:48 Philipp Tomsich [this message]
2022-11-15 17:25 ` Jeff Law
2022-11-16 20:01 ` Philipp Tomsich
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