From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-lf1-x130.google.com (mail-lf1-x130.google.com [IPv6:2a00:1450:4864:20::130]) by sourceware.org (Postfix) with ESMTPS id BDE1B3882F35 for ; Sun, 13 Nov 2022 21:20:38 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org BDE1B3882F35 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu Received: by mail-lf1-x130.google.com with SMTP id j16so16297633lfe.12 for ; Sun, 13 Nov 2022 13:20:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RcdR6MpitLfibQ9CF3pkeh3wSoXK9QDYP9Oza3PCEtc=; b=ql90qoXsRL4WJIXl7hzlVpA2nBJfE3LBIyl656mP1cEXOhAxVAHS0axZf48ODz0Wwa dxV2IXzo+gJknRWy6ZWBejEZwFDdnX8gu0puALPBrPhd60Ib/eyOO+Ys2AYXVjzJ2cTw 3Xr9yWdCWYXoVd+POhgLzmDyiW4vbNL3ZKcd8J8s+gRWU9pLYHTSjxdKLLDTiA1mcVHZ 5eXQNPGDeemBF1o7ddGLPq6TeKJ5OyIfG7RZd3BO9IY49KibVeqjFsV93o0ZSszgT5Z3 0CPI0zQSxaRM6r+85JpRvAwpWA9p45EV5JH5OJa1qmxmLLdHd63RLyg8juoSdJh5VLNq DcCQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RcdR6MpitLfibQ9CF3pkeh3wSoXK9QDYP9Oza3PCEtc=; b=GK70Yqa+qb+ny13HH5A7SRbR9jtc6Itc5q025+IpdgifdhQ65O54i+x2uXAuVwBvmP wImqHw9R7y6ggqMDrwL8ulPTaCv1NYkfhjmWwVgpQZxL3lrBQMD8zOu7DhPOxXM2l2lJ d/C1VM4ztN8TrrkjhvBvupRozwrWIXcFRdRppNN8VvcuiNITrOYtH3kcXnBCQbWmnomJ q+22n6ACxcJCqJbg5yNfifnGe4qz7H/h/vAr6OJfruAnLvu6JKnuPWEXltz0zza0JTnR SUAFhuk32mhjAAjdGh3HIp8qZdAG5Wh1NY44za9CtLpfIX9Xq8V6CSaAUq8p28oMh0M3 WIyg== X-Gm-Message-State: ANoB5pkWwbdMpsleIhimZaoOpSBkPAg5xivg9N48BzKRB8hMHYo+Dsq3 wSizG4PNLZ90a1zZg6gllbgaRhx5QtOLf+Az X-Google-Smtp-Source: AA0mqf71IhiAqXvh3xItP6iBBidIo9F3TEJSPyqTo4K2jiV1MoJnBh7WFUQer3rcpefb+GhHTby40w== X-Received: by 2002:ac2:52af:0:b0:4b4:118a:c775 with SMTP id r15-20020ac252af000000b004b4118ac775mr2969597lfm.244.1668374436911; Sun, 13 Nov 2022 13:20:36 -0800 (PST) Received: from ubuntu-focal.. ([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id d5-20020a0565123d0500b004948ddb4e4dsm1529079lfv.301.2022.11.13.13.20.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Nov 2022 13:20:36 -0800 (PST) From: Philipp Tomsich To: gcc-patches@gcc.gnu.org Cc: Jeff Law , Vineet Gupta , Kito Cheng , Christoph Muellner , Palmer Dabbelt , Philipp Tomsich Subject: [PATCH v2 3/8] RISC-V: Support noce_try_store_flag_mask as vt.maskc Date: Sun, 13 Nov 2022 22:20:24 +0100 Message-Id: <20221113212030.4078815-4-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221113212030.4078815-1-philipp.tomsich@vrull.eu> References: <20221113212030.4078815-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-11.3 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,JMQ_SPF_NEUTRAL,KAM_SHORT,LIKELY_SPAM_BODY,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: When if-conversion in noce_try_store_flag_mask starts the sequence off with an order-operator, our patterns for vt.maskc will receive the result of the order-operator as a register argument; consequently, they can't know that the result will be either 1 or 0. To convey this information (and make vt.maskc applicable), we wrap the result of the order-operator in a eq/ne against (const_int 0). This commit adds the split pattern to handle these cases. During if-conversion, if noce_try_store_flag_mask succeeds, we may see if (cur < next) { next = 0; } transformed into 27: r82:SI=ltu(r76:DI,r75:DI) REG_DEAD r76:DI 28: r81:SI=r82:SI^0x1 REG_DEAD r82:SI 29: r80:DI=zero_extend(r81:SI) REG_DEAD r81:SI This currently escapes the combiner, as RISC-V does not have a pattern to apply the 'slt' instruction to 'geu' verbs. By adding a pattern in this commit, we match such cases. gcc/ChangeLog: * config/riscv/xventanacondops.md: Add split to wrap an an order-operator suitably for generating vt.maskc. * config/riscv/predicates.md (anyge_operator): Define. (anygt_operator): Define. (anyle_operator): Define. (anylt_operator): Define. * config/riscv/riscv.md: Helpers for ge(u) & le(u). gcc/testsuite/ChangeLog: * gcc.target/riscv/xventanacondops-le-01.c: New test. * gcc.target/riscv/xventanacondops-lt-03.c: New test. Signed-off-by: Philipp Tomsich --- Changes in v2: - Fixed a pattern that was truncated during a rebase (last line missing). - Ran whitespace-cleanup on xventanacondops-le-01.c - Ran whitespace-cleanup on xventanacondops-lt-03.c gcc/config/riscv/predicates.md | 12 +++++ gcc/config/riscv/riscv.md | 26 +++++++++++ gcc/config/riscv/xventanacondops.md | 46 +++++++++++++++++++ .../gcc.target/riscv/xventanacondops-le-01.c | 16 +++++++ .../gcc.target/riscv/xventanacondops-lt-03.c | 16 +++++++ 5 files changed, 116 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-le-01.c create mode 100644 gcc/testsuite/gcc.target/riscv/xventanacondops-lt-03.c diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md index b368c11c930..490bff688a7 100644 --- a/gcc/config/riscv/predicates.md +++ b/gcc/config/riscv/predicates.md @@ -204,6 +204,18 @@ (define_predicate "equality_operator" (match_code "eq,ne")) +(define_predicate "anyge_operator" + (match_code "ge,geu")) + +(define_predicate "anygt_operator" + (match_code "gt,gtu")) + +(define_predicate "anyle_operator" + (match_code "le,leu")) + +(define_predicate "anylt_operator" + (match_code "lt,ltu")) + (define_predicate "order_operator" (match_code "eq,ne,lt,ltu,le,leu,ge,geu,gt,gtu")) diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 4331842b7b2..d1f3270a3c8 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -2636,6 +2636,19 @@ [(set_attr "type" "slt") (set_attr "mode" "")]) +(define_split + [(set (match_operand:GPR 0 "register_operand") + (match_operator:GPR 1 "anyle_operator" + [(match_operand:X 2 "register_operand") + (match_operand:X 3 "register_operand")]))] + "TARGET_XVENTANACONDOPS" + [(set (match_dup 0) (match_dup 4)) + (set (match_dup 0) (eq:GPR (match_dup 0) (const_int 0)))] + { + operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == LE ? LT : LTU, + mode, operands[3], operands[2]); + }) + (define_insn "*slt_" [(set (match_operand:GPR 0 "register_operand" "= r") (any_lt:GPR (match_operand:X 1 "register_operand" " r") @@ -2657,6 +2670,19 @@ [(set_attr "type" "slt") (set_attr "mode" "")]) +(define_split + [(set (match_operand:GPR 0 "register_operand") + (match_operator:GPR 1 "anyge_operator" + [(match_operand:X 2 "register_operand") + (match_operand:X 3 "register_operand")]))] + "TARGET_XVENTANACONDOPS" + [(set (match_dup 0) (match_dup 4)) + (set (match_dup 0) (eq:GPR (match_dup 0) (const_int 0)))] +{ + operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == GE ? LT : LTU, + mode, operands[2], operands[3]); +}) + ;; ;; .................... ;; diff --git a/gcc/config/riscv/xventanacondops.md b/gcc/config/riscv/xventanacondops.md index 641cef0e44e..f23058b95b2 100644 --- a/gcc/config/riscv/xventanacondops.md +++ b/gcc/config/riscv/xventanacondops.md @@ -28,3 +28,49 @@ (match_operand:DI 2 "register_operand" "r")))] "TARGET_XVENTANACONDOPS" "vt.maskc\t%0,%2,%1") + +;; Make order operators digestible to the vt.maskc logic by +;; wrapping their result in a comparison against (const_int 0). + +;; "a >= b" is "!(a < b)" +(define_split + [(set (match_operand:X 0 "register_operand") + (and:X (neg:X (match_operator:X 1 "anyge_operator" + [(match_operand:X 2 "register_operand") + (match_operand:X 3 "register_operand")])) + (match_operand:X 4 "register_operand"))) + (clobber (match_operand:X 5 "register_operand"))] + "TARGET_XVENTANACONDOPS" + [(set (match_dup 5) (match_dup 6)) + (set (match_dup 0) (and:X (neg:X (eq:X (match_dup 5) (const_int 0))) + (match_dup 4)))] +{ + operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == GE ? LT : LTU, + mode, operands[2], operands[3]); +}) + +;; "a > b" +(define_split + [(set (match_operand:X 0 "register_operand") + (and:X (neg:X (match_operator:X 1 "anygt_operator" + [(match_operand:X 2 "register_operand") + (match_operand:X 3 "register_operand")])) + (match_operand:X 4 "register_operand"))) + (clobber (match_operand:X 5 "register_operand"))] + "TARGET_XVENTANACONDOPS" + [(set (match_dup 5) (match_dup 1)) + (set (match_dup 0) (and:X (neg:X (ne:X (match_dup 5) (const_int 0))) + (match_dup 4)))]) + +;; "a <= b" is "!(a > b)" +(define_split + [(set (match_operand:X 0 "register_operand") + (and:X (neg:X (match_operator:X 1 "anyle_operator" + [(match_operand:X 2 "register_operand") + (match_operand:X 3 "arith_operand")])) + (match_operand:X 4 "register_operand"))) + (clobber (match_operand:X 5 "register_operand"))] + "TARGET_XVENTANACONDOPS" + [(set (match_dup 5) (match_dup 1)) + (set (match_dup 0) (and:X (neg:X (ne:X (match_dup 5) (const_int 0))) + (match_dup 4)))]) diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-le-01.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-le-01.c new file mode 100644 index 00000000000..f6f80958e9d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-le-01.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zba_zbb_zbs_xventanacondops -mabi=lp64 -mbranch-cost=4" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O1" "-Os" "-Oz" } } */ + +long long sink (long long); + +long long lt3 (long long a, long long b) +{ + if (a <= b) + b = 0; + + return sink(b); +} + +/* { dg-final { scan-assembler-times "sgt\t" 1 } } */ +/* { dg-final { scan-assembler-times "vt.maskc\t" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-lt-03.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-lt-03.c new file mode 100644 index 00000000000..f671f357f91 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-lt-03.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zba_zbb_zbs_xventanacondops -mabi=lp64 -mbranch-cost=4" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O1" "-Os" "-Oz" } } */ + +long long sink (long long); + +long long lt3 (long long a, long long b) +{ + if (a < b) + b = 0; + + return sink(b); +} + +/* { dg-final { scan-assembler-times "slt\t" 1 } } */ +/* { dg-final { scan-assembler-times "vt.maskcn\t" 1 } } */ -- 2.34.1