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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id lb17-20020a170907785100b00734bfab4d59sm3432282ejc.170.2022.11.13.13.46.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Nov 2022 13:46:47 -0800 (PST) From: Christoph Muellner To: gcc-patches@gcc.gnu.org, Kito Cheng , Jim Wilson , Palmer Dabbelt , Andrew Waterman , Philipp Tomsich , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?UTF-8?q?Christoph=20M=C3=BCllner?= Subject: [PATCH 5/7] riscv: thead: Add support for XTheadBb ISA extension Date: Sun, 13 Nov 2022 22:46:34 +0100 Message-Id: <20221113214636.2747737-6-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221113214636.2747737-1-christoph.muellner@vrull.eu> References: <20221113214636.2747737-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,JMQ_SPF_NEUTRAL,KAM_MANYTO,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Christoph Müllner The XTheadBb ISA extension provides instructions similar to Zbb: * th.srri/th.srriw * th.ext/th.extu * th.ff1 (count-leading-zeros) * th.rev/th.revw Instructions that are not covered, because they don't fit into a pattern: * th.ff0 (count-leading-ones) * th.tstnbz For the cases where the RISC-V backend already provides instruction patterns with GCC standard pattern names (e.g. rotatert), this patch simply uses expanders so we can match the pattern using unnamed instruction patterns for zb* and xtheadb*. gcc/ChangeLog: * config/riscv/bitmanip.md (clz2): Add expand. (ctz2): Add expand. (popcount2): Add expand. (*si2): Hide pattern name. (*di2): Hide pattern name. (rotr3): Add expand. (*rotrsi3): Hide pattern name. (*rotrdi3): Hide pattern name. (*rotrsi3_sext): Hide pattern name. (bswapdi2): Add expand. (bswapsi2): Add expand. (*bswap2): Hide pattern name. * config/riscv/riscv.cc (riscv_rtx_costs): Add support for sign-extract. * config/riscv/riscv.md (extv): New expand. (extzv): New expand. * config/riscv/thead.md (*th_srrisi3): New pattern. (*th_srridi3): New pattern. (*th_ext): New pattern. (*th_extu): New pattern. (*th_clz): New pattern. (*th_revsi2): New pattern. (*th_revdi2): New pattern. gcc/testsuite/ChangeLog: * gcc.target/riscv/xtheadbb-ext.c: New test. * gcc.target/riscv/xtheadbb-extu.c: New test. * gcc.target/riscv/xtheadbb-rev.c: New test. * gcc.target/riscv/xtheadbb-srri.c: New test. Signed-off-by: Christoph Müllner --- gcc/config/riscv/bitmanip.md | 47 ++++++++++++-- gcc/config/riscv/riscv.cc | 10 +++ gcc/config/riscv/riscv.md | 26 ++++++++ gcc/config/riscv/thead.md | 62 +++++++++++++++++++ gcc/testsuite/gcc.target/riscv/xtheadbb-ext.c | 19 ++++++ .../gcc.target/riscv/xtheadbb-extu.c | 12 ++++ gcc/testsuite/gcc.target/riscv/xtheadbb-rev.c | 40 ++++++++++++ .../gcc.target/riscv/xtheadbb-srri.c | 18 ++++++ 8 files changed, 228 insertions(+), 6 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-ext.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-extu.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-rev.c create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbb-srri.c diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md index b44fb9517e7..3dbb92b6115 100644 --- a/gcc/config/riscv/bitmanip.md +++ b/gcc/config/riscv/bitmanip.md @@ -119,6 +119,21 @@ (define_insn "*slliuw" ;; ZBB extension. +(define_expand "clz2" + [(set (match_operand:GPR 0 "register_operand") + (clz:GPR (match_operand:GPR 1 "register_operand")))] + "TARGET_ZBB || TARGET_XTHEADBB") + +(define_expand "ctz2" + [(set (match_operand:GPR 0 "register_operand") + (ctz:GPR (match_operand:GPR 1 "register_operand")))] + "TARGET_ZBB") + +(define_expand "popcount2" + [(set (match_operand:GPR 0 "register_operand") + (popcount:GPR (match_operand:GPR 1 "register_operand")))] + "TARGET_ZBB") + (define_insn "*_not" [(set (match_operand:X 0 "register_operand" "=r") (bitmanip_bitwise:X (not:X (match_operand:X 1 "register_operand" "r")) @@ -137,7 +152,7 @@ (define_insn "*xor_not" [(set_attr "type" "bitmanip") (set_attr "mode" "")]) -(define_insn "si2" +(define_insn "*si2" [(set (match_operand:SI 0 "register_operand" "=r") (clz_ctz_pcnt:SI (match_operand:SI 1 "register_operand" "r")))] "TARGET_ZBB" @@ -154,7 +169,7 @@ (define_insn "*disi2" [(set_attr "type" "bitmanip") (set_attr "mode" "SI")]) -(define_insn "di2" +(define_insn "*di2" [(set (match_operand:DI 0 "register_operand" "=r") (clz_ctz_pcnt:DI (match_operand:DI 1 "register_operand" "r")))] "TARGET_64BIT && TARGET_ZBB" @@ -194,7 +209,17 @@ (define_insn "*zero_extendhi2_zbb" [(set_attr "type" "bitmanip,load") (set_attr "mode" "HI")]) -(define_insn "rotrsi3" +(define_expand "rotr3" + [(set (match_operand:GPR 0 "register_operand") + (rotatert:GPR (match_operand:GPR 1 "register_operand") + (match_operand:QI 2 "arith_operand")))] + "TARGET_ZBB || TARGET_XTHEADBB" +{ + if (TARGET_XTHEADBB && !immediate_operand (operands[2], VOIDmode)) + FAIL; +}) + +(define_insn "*rotrsi3" [(set (match_operand:SI 0 "register_operand" "=r") (rotatert:SI (match_operand:SI 1 "register_operand" "r") (match_operand:QI 2 "arith_operand" "rI")))] @@ -202,7 +227,7 @@ (define_insn "rotrsi3" "ror%i2%~\t%0,%1,%2" [(set_attr "type" "bitmanip")]) -(define_insn "rotrdi3" +(define_insn "*rotrdi3" [(set (match_operand:DI 0 "register_operand" "=r") (rotatert:DI (match_operand:DI 1 "register_operand" "r") (match_operand:QI 2 "arith_operand" "rI")))] @@ -210,7 +235,7 @@ (define_insn "rotrdi3" "ror%i2\t%0,%1,%2" [(set_attr "type" "bitmanip")]) -(define_insn "rotrsi3_sext" +(define_insn "*rotrsi3_sext" [(set (match_operand:DI 0 "register_operand" "=r") (sign_extend:DI (rotatert:SI (match_operand:SI 1 "register_operand" "r") (match_operand:QI 2 "register_operand" "r"))))] @@ -242,7 +267,17 @@ (define_insn "rotlsi3_sext" "rolw\t%0,%1,%2" [(set_attr "type" "bitmanip")]) -(define_insn "bswap2" +(define_expand "bswapdi2" + [(set (match_operand:DI 0 "register_operand") + (bswap:DI (match_operand:DI 1 "register_operand")))] + "TARGET_64BIT && (TARGET_ZBB || TARGET_XTHEADBB)") + +(define_expand "bswapsi2" + [(set (match_operand:SI 0 "register_operand") + (bswap:SI (match_operand:SI 1 "register_operand")))] + "(!TARGET_64BIT && TARGET_ZBB) || TARGET_XTHEADBB") + +(define_insn "*bswap2" [(set (match_operand:X 0 "register_operand" "=r") (bswap:X (match_operand:X 1 "register_operand" "r")))] "TARGET_ZBB" diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 9a795264e00..c0de99d1ca6 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -2377,6 +2377,16 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN *total = COSTS_N_INSNS (SINGLE_SHIFT_COST); return true; } + /* Fall through. */ + case SIGN_EXTRACT: + if (TARGET_XTHEADBB + && REG_P (XEXP (x, 0)) + && CONST_INT_P (XEXP (x, 1)) + && CONST_INT_P (XEXP (x, 2))) + { + *total = COSTS_N_INSNS (SINGLE_SHIFT_COST); + return true; + } return false; case ASHIFT: diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 850a2d958e4..cfe1fd6baea 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -3003,6 +3003,32 @@ (define_insn "riscv_prefetchi_" "prefetch.i\t%a0" ) +(define_expand "extv" + [(set (match_operand:GPR 0 "register_operand" "=r") + (sign_extract:GPR (match_operand:GPR 1 "register_operand" "r") + (match_operand 2 "const_int_operand") + (match_operand 3 "const_int_operand")))] + "TARGET_XTHEADBB" +{ + if (TARGET_XTHEADBB + && ((INTVAL (operands[2]) + INTVAL (operands[3])) + >= GET_MODE_BITSIZE (GET_MODE (operands[1])).to_constant ())) + FAIL; +}) + +(define_expand "extzv" + [(set (match_operand:GPR 0 "register_operand" "=r") + (zero_extract:GPR (match_operand:GPR 1 "register_operand" "r") + (match_operand 2 "const_int_operand") + (match_operand 3 "const_int_operand")))] + "TARGET_XTHEADBB" +{ + if (TARGET_XTHEADBB + && ((INTVAL (operands[2]) + INTVAL (operands[3])) + >= GET_MODE_BITSIZE (GET_MODE (operands[1])).to_constant ())) + FAIL; +}) + (include "bitmanip.md") (include "sync.md") (include "peephole.md") diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md index e9a6c1eeb71..ad42c03c0ce 100644 --- a/gcc/config/riscv/thead.md +++ b/gcc/config/riscv/thead.md @@ -28,6 +28,68 @@ (define_insn "*th_addsl" [(set_attr "type" "bitmanip") (set_attr "mode" "")]) +(define_insn "*th_srrisi3" + [(set (match_operand:SI 0 "register_operand" "=r") + (rotatert:SI (match_operand:SI 1 "register_operand" "r") + (match_operand:QI 2 "immediate_operand" "I")))] + "TARGET_XTHEADBB" + { return TARGET_64BIT ? "th.srriw\t%0,%1,%2" : "th.srri\t%0,%1,%2"; } + [(set_attr "type" "bitmanip")]) + +(define_insn "*th_srridi3" + [(set (match_operand:DI 0 "register_operand" "=r") + (rotatert:DI (match_operand:DI 1 "register_operand" "r") + (match_operand:QI 2 "immediate_operand" "I")))] + "TARGET_XTHEADBB && TARGET_64BIT" + "th.srri\t%0,%1,%2" + [(set_attr "type" "bitmanip")]) + +(define_insn "*th_ext" + [(set (match_operand:X 0 "register_operand" "=r") + (sign_extract:X (match_operand:X 1 "register_operand" "r") + (match_operand 2 "const_int_operand") + (match_operand 3 "const_int_operand")))] + "TARGET_XTHEADBB" +{ + operands[3] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[3])); + return "th.ext\t%0,%1,%2,%3"; +} + [(set_attr "type" "bitmanip")]) + +(define_insn "*th_extu" + [(set (match_operand:X 0 "register_operand" "=r") + (zero_extract:X (match_operand:X 1 "register_operand" "r") + (match_operand 2 "const_int_operand") + (match_operand 3 "const_int_operand")))] + "TARGET_XTHEADBB" +{ + operands[3] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[3])); + return "th.extu\t%0,%1,%2,%3"; +} + [(set_attr "type" "bitmanip")]) + +(define_insn "*th_clz" + [(set (match_operand:X 0 "register_operand" "=r") + (clz:X (match_operand:X 1 "register_operand" "r")))] + "TARGET_XTHEADBB" + "th.ff1\t%0,%1" + [(set_attr "type" "bitmanip") + (set_attr "mode" "")]) + +(define_insn "*th_revsi2" + [(set (match_operand:SI 0 "register_operand" "=r") + (bswap:SI (match_operand:SI 1 "register_operand" "r")))] + "TARGET_XTHEADBB" + { return TARGET_64BIT ? "th.revw\t%0,%1" : "th.rev\t%0,%1"; } + [(set_attr "type" "bitmanip")]) + +(define_insn "*th_revdi2" + [(set (match_operand:DI 0 "register_operand" "=r") + (bswap:DI (match_operand:DI 1 "register_operand" "r")))] + "TARGET_XTHEADBB && TARGET_64BIT" + "th.rev\t%0,%1" + [(set_attr "type" "bitmanip")]) + (define_insn "*th_tst" [(set (match_operand:X 0 "register_operand" "=r") (zero_extract:X (match_operand:X 1 "register_operand" "r") diff --git a/gcc/testsuite/gcc.target/riscv/xtheadbb-ext.c b/gcc/testsuite/gcc.target/riscv/xtheadbb-ext.c new file mode 100644 index 00000000000..35c3afa5aad --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadbb-ext.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_xtheadbb -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Og" } } */ + +struct bar +{ + long a:18; + long b:24; + long c:22; +}; + +long +foo (struct bar *s) +{ + return s->b; +} + +/* { dg-final { scan-assembler "ext\t" } } */ +/* { dg-final { scan-assembler-not "andi" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xtheadbb-extu.c b/gcc/testsuite/gcc.target/riscv/xtheadbb-extu.c new file mode 100644 index 00000000000..d52af1dec61 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadbb-extu.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_xtheadbb -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Os" "-Og" } } */ + +int +foo (int a, int b) +{ + return ((a & (1 << 25)) ? 5 : 4); +} + +/* { dg-final { scan-assembler "extu\t" } } */ +/* { dg-final { scan-assembler-not "andi" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xtheadbb-rev.c b/gcc/testsuite/gcc.target/riscv/xtheadbb-rev.c new file mode 100644 index 00000000000..fb35317ae9f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadbb-rev.c @@ -0,0 +1,40 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_xtheadbb -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Og" } } */ + +unsigned int +foo32 (unsigned int x) +{ + return (((x << 24) & 0xff000000) + | ((x << 8) & 0xff0000) + | ((x >> 8) & 0xff00) + | ((x >> 24) & 0xff)); +} + +unsigned int +foo32_1 (unsigned int x) +{ + return __builtin_bswap32 (x); +} + +unsigned long +foo64 (unsigned long x) +{ + return (((x << 56) & 0xff00000000000000ull) + | ((x << 40) & 0xff000000000000ull) + | ((x << 24) & 0xff0000000000ull) + | ((x << 8) & 0xff00000000ull) + | ((x >> 8) & 0xff000000) + | ((x >> 24) & 0xff0000) + | ((x >> 40) & 0xff00) + | ((x >> 56) & 0xff)); +} + +unsigned long +foo64_1 (unsigned long x) +{ + return __builtin_bswap64 (x); +} + +/* { dg-final { scan-assembler-times "th.revw\t" 2 } } */ +/* { dg-final { scan-assembler-times "th.rev\t" 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xtheadbb-srri.c b/gcc/testsuite/gcc.target/riscv/xtheadbb-srri.c new file mode 100644 index 00000000000..cd992ae3f0a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadbb-srri.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_xtheadbb -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-g" } } */ + +unsigned long foo1(unsigned long rs1) +{ + long shamt = __riscv_xlen - 11; + return (rs1 << shamt) | + (rs1 >> ((__riscv_xlen - shamt) & (__riscv_xlen - 1))); +} +unsigned long foo2(unsigned long rs1) +{ + unsigned long shamt = __riscv_xlen - 11; + return (rs1 >> shamt) | + (rs1 << ((__riscv_xlen - shamt) & (__riscv_xlen - 1))); +} + +/* { dg-final { scan-assembler-times "th.srri" 2 } } */ -- 2.38.1