[PATCH v3] RISC-V missing __builtin_lceil and __builtin_lfloor

[Kevin Lee <kevinl@rivosinc.com>]

l<rint_pattern> insn condition has been modified based on the thread in
https://gcc.gnu.org/pipermail/gcc-patches/2022-November/605481.html. The
lfloor-lecil-inexact checks call instead of scan-assembler-not
"fcvt.l.s/d" due to https://gcc.gnu.org/bugzilla/show_bug.cgi?id=107723.

Is this patch good for commit?

gcc/ChangeLog:

	Michael Collison <collison@rivosinc.com>
	Kevin Lee <kevinl@rivosinc.com>
	* config/riscv/iterators.md (RINT): Additional iterators.
	(rint_pattern): Additional attributes.
	(rint_rm): Ditto.
	* config/riscv/riscv.md (UNSPEC_LCEIL): New unspec.
	(UNSPEC_LFLOOR): Ditto.
	(l<rint_pattern><ANYF:mode><GPR:mode>2): Additional conditions.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/lfloor-lceil-inexact.c: New test.
	* gcc.target/riscv/lfloor-lceil.c: New test.
---
 gcc/config/riscv/iterators.md                 | 10 ++-
 gcc/config/riscv/riscv.md                     |  8 +-
 .../gcc.target/riscv/lfloor-lceil-inexact.c   | 78 ++++++++++++++++++
 gcc/testsuite/gcc.target/riscv/lfloor-lceil.c | 79 +++++++++++++++++++
 4 files changed, 171 insertions(+), 4 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/lfloor-lceil-inexact.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/lfloor-lceil.c

diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md
index 50380ecfac9..c5adcb08421 100644
--- a/gcc/config/riscv/iterators.md
+++ b/gcc/config/riscv/iterators.md
@@ -233,9 +233,13 @@ (define_code_attr bitmanip_insn [(smin "min")
 ;; -------------------------------------------------------------------
 
 ;; Iterator and attributes for floating-point rounding instructions.
-(define_int_iterator RINT [UNSPEC_LRINT UNSPEC_LROUND])
-(define_int_attr rint_pattern [(UNSPEC_LRINT "rint") (UNSPEC_LROUND "round")])
-(define_int_attr rint_rm [(UNSPEC_LRINT "dyn") (UNSPEC_LROUND "rmm")])
+(define_int_iterator RINT [UNSPEC_LRINT UNSPEC_LROUND UNSPEC_LCEIL UNSPEC_LFLOOR])
+(define_int_attr rint_pattern [(UNSPEC_LRINT "rint") (UNSPEC_LROUND "round")
+                             (UNSPEC_LCEIL "ceil") (UNSPEC_LFLOOR "floor")])
+(define_int_attr rint_rm [(UNSPEC_LRINT "dyn") (UNSPEC_LROUND "rmm")
+                        (UNSPEC_LCEIL "rup") (UNSPEC_LFLOOR "rdn")])
+(define_int_attr rint_allow_inexact [(UNSPEC_LRINT "1") (UNSPEC_LROUND "0")
+                        (UNSPEC_LCEIL "0") (UNSPEC_LFLOOR "0")])
 
 ;; Iterator and attributes for quiet comparisons.
 (define_int_iterator QUIET_COMPARISON [UNSPEC_FLT_QUIET UNSPEC_FLE_QUIET])
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 798f7370a08..57777074f8e 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -60,6 +60,9 @@ (define_c_enum "unspec" [
   UNSPEC_FMIN
   UNSPEC_FMAX
 
+  UNSPEC_LCEIL
+  UNSPEC_LFLOOR
+
   ;; Stack tie
   UNSPEC_TIE
 ])
@@ -1552,7 +1555,10 @@ (define_insn "l<rint_pattern><ANYF:mode><GPR:mode>2"
 	(unspec:GPR
 	    [(match_operand:ANYF 1 "register_operand" " f")]
 	    RINT))]
-  "TARGET_HARD_FLOAT || TARGET_ZFINX"
+  "(TARGET_HARD_FLOAT || TARGET_ZFINX) &&
+    (<rint_allow_inexact>
+      || flag_fp_int_builtin_inexact
+      || !flag_trapping_math)"
   "fcvt.<GPR:ifmt>.<ANYF:fmt> %0,%1,<rint_rm>"
   [(set_attr "type" "fcvt")
    (set_attr "mode" "<ANYF:MODE>")])
diff --git a/gcc/testsuite/gcc.target/riscv/lfloor-lceil-inexact.c b/gcc/testsuite/gcc.target/riscv/lfloor-lceil-inexact.c
new file mode 100644
index 00000000000..3b37df20d0e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/lfloor-lceil-inexact.c
@@ -0,0 +1,78 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d -fno-fp-int-builtin-inexact" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
+
+int
+ceil1(float i)
+{
+  return __builtin_lceil(i);
+}
+
+long
+ceil2(float i)
+{
+  return __builtin_lceil(i);
+}
+
+long long
+ceil3(float i)
+{
+  return __builtin_lceil(i);
+}
+
+int
+ceil4(double i)
+{
+  return __builtin_lceil(i);
+}
+
+long
+ceil5(double i)
+{
+  return __builtin_lceil(i);
+}
+
+long long
+ceil6(double i)
+{
+  return __builtin_lceil(i);
+}
+
+int
+floor1(float i)
+{
+  return __builtin_lfloor(i);
+}
+
+long
+floor2(float i)
+{
+  return __builtin_lfloor(i);
+}
+
+long long
+floor3(float i)
+{
+  return __builtin_lfloor(i);
+}
+
+int
+floor4(double i)
+{
+  return __builtin_lfloor(i);
+}
+
+long
+floor5(double i)
+{
+  return __builtin_lfloor(i);
+}
+
+long long
+floor6(double i)
+{
+  return __builtin_lfloor(i);
+}
+
+/* { dg-final { scan-assembler-times "call" 12 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/lfloor-lceil.c b/gcc/testsuite/gcc.target/riscv/lfloor-lceil.c
new file mode 100644
index 00000000000..4715de746fb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/lfloor-lceil.c
@@ -0,0 +1,79 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
+
+int
+ceil1(float i)
+{
+  return __builtin_lceil(i);
+}
+
+long
+ceil2(float i)
+{
+  return __builtin_lceil(i);
+}
+
+long long
+ceil3(float i)
+{
+  return __builtin_lceil(i);
+}
+
+int
+ceil4(double i)
+{
+  return __builtin_lceil(i);
+}
+
+long
+ceil5(double i)
+{
+  return __builtin_lceil(i);
+}
+
+long long
+ceil6(double i)
+{
+  return __builtin_lceil(i);
+}
+
+int
+floor1(float i)
+{
+  return __builtin_lfloor(i);
+}
+
+long
+floor2(float i)
+{
+  return __builtin_lfloor(i);
+}
+
+long long
+floor3(float i)
+{
+  return __builtin_lfloor(i);
+}
+
+int
+floor4(double i)
+{
+  return __builtin_lfloor(i);
+}
+
+long
+floor5(double i)
+{
+  return __builtin_lfloor(i);
+}
+
+long long
+floor6(double i)
+{
+  return __builtin_lfloor(i);
+}
+
+/* { dg-final { scan-assembler-times "fcvt.l.s" 6 } } */
+/* { dg-final { scan-assembler-times "fcvt.l.d" 6 } } */
+/* { dg-final { scan-assembler-not "call" } } */
-- 
2.25.1