From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from out30-43.freemail.mail.aliyun.com (out30-43.freemail.mail.aliyun.com [115.124.30.43]) by sourceware.org (Postfix) with ESMTPS id D4305384F6D0 for ; Fri, 18 Nov 2022 04:50:24 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org D4305384F6D0 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linux.alibaba.com X-Alimail-AntiSpam:AC=PASS;BC=-1|-1;BR=01201311R171e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=ay29a033018045170;MF=cooper.qu@linux.alibaba.com;NM=1;PH=DS;RN=2;SR=0;TI=SMTPD_---0VV3bWOI_1668747020; Received: from localhost(mailfrom:cooper.qu@linux.alibaba.com fp:SMTPD_---0VV3bWOI_1668747020) by smtp.aliyun-inc.com; Fri, 18 Nov 2022 12:50:20 +0800 Date: Fri, 18 Nov 2022 12:50:19 +0800 From: "cooper.qu@linux.alibaba.com" To: Christoph Muellner Cc: gcc-patches@gcc.gnu.org Subject: Re: [PATCH 2/7] riscv: riscv-cores.def: Add T-Head XuanTie C906 Message-ID: <20221118045019.GC12452@L-PF1ZESZG-1136.hz.ali.com> References: <20221113214636.2747737-1-christoph.muellner@vrull.eu> <20221113214636.2747737-3-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20221113214636.2747737-3-christoph.muellner@vrull.eu> X-Spam-Status: No, score=-20.3 required=5.0 tests=BAYES_00,ENV_AND_HDR_SPF_MATCH,GIT_PATCH_0,KAM_DMARC_STATUS,KAM_NUMSUBJECT,KAM_SHORT,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_NONE,SPF_PASS,TXREP,UNPARSEABLE_RELAY,USER_IN_DEF_SPF_WL autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On Sun, Nov 13, 2022 at 10:46:31PM +0100, Christoph Muellner wrote: > From: Christoph Müllner > > This adds T-Head's XuanTie C906 to the list of known cores as "thead-c906". > The C906 is shipped for quite some time (it is the core of the Allwinner D1). > Note, that the tuning struct for the C906 is already part of GCC (it is > also name "thead-c906"). > > gcc/ChangeLog: > > * config/riscv/riscv-cores.def (RISCV_CORE): Add "thead-c906". > > gcc/testsuite/ChangeLog: > > * gcc.target/riscv/mcpu-thead-c906.c: New test. > > Signed-off-by: Christoph Müllner > --- > gcc/config/riscv/riscv-cores.def | 2 ++ > .../gcc.target/riscv/mcpu-thead-c906.c | 18 ++++++++++++++++++ > 2 files changed, 20 insertions(+) > create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-thead-c906.c > > diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def > index 31ad34682c5..648a010e09b 100644 > --- a/gcc/config/riscv/riscv-cores.def > +++ b/gcc/config/riscv/riscv-cores.def > @@ -73,4 +73,6 @@ RISCV_CORE("sifive-s76", "rv64imafdc", "sifive-7-series") > RISCV_CORE("sifive-u54", "rv64imafdc", "sifive-5-series") > RISCV_CORE("sifive-u74", "rv64imafdc", "sifive-7-series") > > +RISCV_CORE("thead-c906", "rv64imafdc", "thead-c906") > + I think it makes more sense that thead-906 includes extended instructions by default. Thanks, Cooper