From: Feng Wang <wangfeng@eswincomputing.com>
To: gcc-patches@gcc.gnu.org
Cc: kito.cheng@gmail.com, palmer@dabbelt.com,
Feng Wang <wangfeng@eswincomputing.com>
Subject: [PATCH v2 0/1] RISC-V: Optimze the reverse conditions of rotate shift
Date: Tue, 6 Dec 2022 09:11:52 +0000 [thread overview]
Message-ID: <20221206091153.27281-1-wangfeng@eswincomputing.com> (raw)
The first patch is https://gcc.gnu.org/pipermail/gcc-patches/2022-November/607332.html.
Accroding to Jeff's suggestion I added some conditions when reverse the rotate
shift during RTL expansion and RTL optimization.
wangfeng (1):
RISC-V: Optimze the reverse conditions of rotate shift
gcc/config/riscv/bitmanip.md | 4 +-
gcc/expmed.cc | 14 ++--
gcc/rtl.h | 1 +
gcc/simplify-rtx.cc | 49 ++++++++++----
.../gcc.target/riscv/zbb-rol-ror-04.c | 52 +++++++++++++++
.../gcc.target/riscv/zbb-rol-ror-05.c | 24 +++++++
.../gcc.target/riscv/zbb-rol-ror-06.c | 36 +++++++++++
.../gcc.target/riscv/zbb-rol-ror-07.c | 64 +++++++++++++++++++
8 files changed, 219 insertions(+), 25 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-rol-ror-04.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-rol-ror-05.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-rol-ror-06.c
create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-rol-ror-07.c
--
2.17.1
next reply other threads:[~2022-12-06 9:12 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-06 9:11 Feng Wang [this message]
2022-12-06 9:11 ` [PATCH v2 1/1] " Feng Wang
2023-04-17 17:53 ` Jeff Law
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