From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from cstnet.cn (smtp21.cstnet.cn [159.226.251.21]) by sourceware.org (Postfix) with ESMTP id E354738417E9 for ; Tue, 13 Dec 2022 06:49:54 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org E354738417E9 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from localhost.localdomain (unknown [125.65.12.192]) by APP-01 (Coremail) with SMTP id qwCowAD3eOyJIJhjKJ_NBg--.29090S2; Tue, 13 Dec 2022 14:49:47 +0800 (CST) From: shihua@iscas.ac.cn To: gcc-patches@gcc.gnu.org Cc: lazyparser@gmail.com, jiawei@iscas.ac.cn, kito.cheng@gmail.com, Liao Shihua Subject: [RFC]RISC-V: Support RV64-ILP32 Date: Tue, 13 Dec 2022 14:49:27 +0800 Message-Id: <20221213064927.1416-1-shihua@iscas.ac.cn> X-Mailer: git-send-email 2.38.0.windows.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CM-TRANSID:qwCowAD3eOyJIJhjKJ_NBg--.29090S2 X-Coremail-Antispam: 1UD129KBjvJXoWxZrW3uryfZw15Cw13GF15urg_yoWrXFyfpF 4UGw4ay34rAFsIgw4xtrWrGw15Gwnagw1Yv398ZrW7Aan8Jryvy3Z0qa13XrWDWFs0qrnr AFnIkr4ay3yUC3DanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUkq14x267AKxVWUJVW8JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26r1I6r4UM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4j 6F4UM28EF7xvwVC2z280aVAFwI0_Gr1j6F4UJwA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Cr 1j6rxdM2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj 6xIIjxv20xvE14v26r1j6r18McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr 0_Gr1lF7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7M4kE6xkIj40Ew7xC 0wCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r 1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_JF0_Jw1lIxkGc2Ij 64vIr41lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Jr 0_Gr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF 0xvEx4A2jsIEc7CjxVAFwI0_Jr0_GrUvcSsGvfC2KfnxnUUI43ZEXa7VUjRVbDUUUUU== X-Originating-IP: [125.65.12.192] X-CM-SenderInfo: xvklx33d6l2u1dvotugofq/1tbiCgETEWOX7BGJ+wAAsy X-Spam-Status: No, score=-12.8 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,KAM_NUMSUBJECT,SPF_HELO_PASS,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Liao Shihua This patch support rv64 insn in ilp32 ABI. It was inspired by aarch64 both support 64-bit and 32-bit ABI with the same set of instructions. gcc/ChangeLog: * config.gcc: Implememt ilp32* with rv64*. * config/riscv/riscv.cc (riscv_option_override): Remove the constraint between RV64 and ILP32. * config/riscv/riscv.h (TARGET_ILP32): Define TARGET_ILP32 with riscv_abi. (POINTER_SIZE):POINTER_SIZE will change with TARGET_ILP32. (Pmode):Likewise. * config/riscv/riscv.md: Convert split mode with Pmode and change mode form Xmode to Pmode in stack_tie. --- gcc/config.gcc | 3 +++ gcc/config/riscv/riscv.cc | 4 ---- gcc/config/riscv/riscv.h | 8 ++++++-- gcc/config/riscv/riscv.md | 8 ++++++-- 4 files changed, 15 insertions(+), 8 deletions(-) diff --git a/gcc/config.gcc b/gcc/config.gcc index c5064dd3766..069293a6e19 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -4748,6 +4748,9 @@ case "${target}" in ilp32,rv32* | ilp32e,rv32e* \ | ilp32f,rv32*f* | ilp32f,rv32g* \ | ilp32d,rv32*d* | ilp32d,rv32g* \ + | ilp32f,rv64*f* | ilp32f,rv64g* \ + | ilp32d,rv64*d* | ilp32d,rv64g* \ + | ilp32,rv64* \ | lp64,rv64* \ | lp64f,rv64*f* | lp64f,rv64g* \ | lp64d,rv64*d* | lp64d,rv64g*) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index ee756aab694..03f313e2b28 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -5026,10 +5026,6 @@ riscv_option_override (void) if (TARGET_RVE && riscv_abi != ABI_ILP32E) error ("rv32e requires ilp32e ABI"); - /* We do not yet support ILP32 on RV64. */ - if (BITS_PER_WORD != POINTER_SIZE) - error ("ABI requires %<-march=rv%d%>", POINTER_SIZE); - /* Validate -mpreferred-stack-boundary= value. */ riscv_stack_boundary = ABI_STACK_BOUNDARY; if (riscv_preferred_stack_boundary_arg) diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h index 8a4d2cf7f85..63aece89878 100644 --- a/gcc/config/riscv/riscv.h +++ b/gcc/config/riscv/riscv.h @@ -79,6 +79,10 @@ extern const char *riscv_default_mtune (int argc, const char **argv); #define TARGET_64BIT (__riscv_xlen == 64) #endif /* IN_LIBGCC2 */ +#ifndef TARGET_ILP32 +#define TARGET_ILP32 (riscv_abi <= ABI_ILP32D) +#endif /*TARGET_ILP32*/ + #ifdef HAVE_AS_MISA_SPEC #define ASM_MISA_SPEC "%{misa-spec=*}" #else @@ -167,7 +171,7 @@ ASM_MISA_SPEC #define SHORT_TYPE_SIZE 16 #define INT_TYPE_SIZE 32 #define LONG_LONG_TYPE_SIZE 64 -#define POINTER_SIZE (riscv_abi >= ABI_LP64 ? 64 : 32) +#define POINTER_SIZE (TARGET_ILP32 ? 32 : 64) #define LONG_TYPE_SIZE POINTER_SIZE #define FLOAT_TYPE_SIZE 32 @@ -729,7 +733,7 @@ typedef struct { After generation of rtl, the compiler makes no further distinction between pointers and any other objects of this machine mode. */ -#define Pmode word_mode +#define Pmode (TARGET_ILP32 ? SImode : DImode) /* Give call MEMs SImode since it is the "most permissive" mode for both 32-bit and 64-bit targets. */ diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index b3c5bce842a..34034aec8c0 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -2559,6 +2559,10 @@ "reload_completed" [(const_int 0)] { + if (GET_MODE (operands[0]) != Pmode) + operands[0] = convert_to_mode (Pmode, operands[0], 0); + if (GET_MODE (operands[1]) != Pmode) + operands[1] = convert_to_mode (Pmode, operands[1], 0); riscv_set_return_address (operands[0], operands[1]); DONE; }) @@ -2759,8 +2763,8 @@ (define_insn "stack_tie" [(set (mem:BLK (scratch)) - (unspec:BLK [(match_operand:X 0 "register_operand" "r") - (match_operand:X 1 "register_operand" "r")] + (unspec:BLK [(match_operand:P 0 "register_operand" "r") + (match_operand:P 1 "register_operand" "r")] UNSPEC_TIE))] "" "" -- 2.38.0.windows.1