From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtpbgsg1.qq.com (smtpbgsg1.qq.com [54.254.200.92]) by sourceware.org (Postfix) with ESMTPS id C3E063858425 for ; Tue, 20 Dec 2022 14:56:57 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org C3E063858425 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp70t1671548212tzvgo12q Received: from rios-cad5.localdomain ( [58.60.1.11]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 20 Dec 2022 22:56:51 +0800 (CST) X-QQ-SSF: 01400000002000E0L000B00A0000000 X-QQ-FEAT: ILHsT53NKPjPtwUzRWesxbe46NhyTDtYvDW5OIvKPzCoKDYQ/jG+c0gEBDrLW +sHMaNFiSFTNk5rmGbNXhmJTtNzkFS0B0VGp9LPZNjXcvQVJVxrSAmI8azS3F6BlI+t1Ftb lT1KN6KY970H+l0D57wxlSB+YEolIoOZVRX2hxDrDPzE4Y2N94DoJRaLTMm6xjfrzvmZf7g C5n+hF+Jwp05HvSp4yRpehhaRdLBK/YRzAUyqcdarsi29KfsUNBZl5zRe31kBfE2pOXmu+7 ZLTZgOtC7p+s1lUXBO4J+C5/zU6yU3z3riRs/0Gae0NZr8HswgsOJvGCx/fclGdiC150Od7 SWeP0fNKnvTy35ed2QvT4GY9IhMaTFaU+HJ5+Wc7wL2lT6hMeSmmcIVW13AGxXrjmbpRC3S +TqGKPTuIjo= X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: Remove side effects of vsetvl pattern in RTL. Date: Tue, 20 Dec 2022 22:56:49 +0800 Message-Id: <20221220145649.232331-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Ju-Zhe Zhong gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc: Change it to no side effects. * config/riscv/vector.md (@vsetvl_no_side_effects): New pattern. --- .../riscv/riscv-vector-builtins-bases.cc | 2 +- gcc/config/riscv/vector.md | 26 +++++++++++++++++++ 2 files changed, 27 insertions(+), 1 deletion(-) diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index 75879dea25a..c1193dbbfb5 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -75,7 +75,7 @@ public: /* MU. */ e.add_input_operand (Pmode, gen_int_mode (0, Pmode)); - return e.generate_insn (code_for_vsetvl (Pmode)); + return e.generate_insn (code_for_vsetvl_no_side_effects (Pmode)); } }; diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 84adbb9974a..98b8f701c92 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -565,6 +565,32 @@ [(set_attr "type" "vsetvl") (set_attr "mode" "")]) +;; It's emit by vsetvl/vsetvlmax intrinsics with no side effects. +;; Since we have many optmization passes from "expand" to "reload_completed", +;; such pattern can allow us gain benefits of these optimizations. +(define_insn_and_split "@vsetvl_no_side_effects" + [(set (match_operand:P 0 "register_operand" "=r") + (unspec:P [(match_operand:P 1 "csr_operand" "rK") + (match_operand 2 "const_int_operand" "i") + (match_operand 3 "const_int_operand" "i") + (match_operand 4 "const_int_operand" "i") + (match_operand 5 "const_int_operand" "i")] UNSPEC_VSETVL))] + "TARGET_VECTOR" + "#" + "&& epilogue_completed" + [(parallel + [(set (match_dup 0) + (unspec:P [(match_dup 1) (match_dup 2) (match_dup 3) + (match_dup 4) (match_dup 5)] UNSPEC_VSETVL)) + (set (reg:SI VL_REGNUM) + (unspec:SI [(match_dup 1) (match_dup 2) (match_dup 3)] UNSPEC_VSETVL)) + (set (reg:SI VTYPE_REGNUM) + (unspec:SI [(match_dup 2) (match_dup 3) (match_dup 4) + (match_dup 5)] UNSPEC_VSETVL))])] + "" + [(set_attr "type" "vsetvl") + (set_attr "mode" "SI")]) + ;; RVV machine description matching format ;; (define_insn "" ;; [(set (match_operand:MODE 0) -- 2.36.3