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From: Segher Boessenkool <segher@kernel.crashing.org>
To: HAO CHEN GUI <guihaoc@linux.ibm.com>
Cc: gcc-patches <gcc-patches@gcc.gnu.org>, David <dje.gcc@gmail.com>,
	"Kewen.Lin" <linkw@linux.ibm.com>,
	Peter Bergner <bergner@linux.ibm.com>
Subject: Re: [PATCH v6, rs6000] Change mode and insn condition for VSX scalar extract/insert instructions
Date: Tue, 20 Dec 2022 12:03:23 -0600	[thread overview]
Message-ID: <20221220180323.GS25951@gate.crashing.org> (raw)
In-Reply-To: <3d530867-c6a2-15bf-fd65-54313622acda@linux.ibm.com>

Hi!

On Mon, Dec 19, 2022 at 02:27:57PM +0800, HAO CHEN GUI wrote:
>     This patch fixes several problems:
>     1. The exponent of double-precision can be put into a SImode register.
>     So "xsxexpdp" doesn't require 64-bit environment. Also "xsxsigdp",
>     "xsiexpdp" and "xsiexpdpf" can put exponent into a GPR register.
> 
>     2. "TARGET_64BIT" check in insn conditions should be replaced with
>     "TARGET_POWERPC64" check.
> 
>     3. "lp64" check in test cases should be replaced with "has_arch_ppc64"
>     check. "ilp32" check should be replaced with "dg-skip-if has_arch_ppc64".

These things are independent.  Please do independent patches (a series
is fine and even preferred, of course).  Not only is this much harder to
review the way it is, it was harder to write as well, write changelog
for, etc.  Often when you prepare patches it becomes apparent that you
should have structured things a bit differently.  That is a good time to
do exactly so :-)

>     This patch keeps outer interfaces of these builtins unchanged.

Of course.  This patch doesn't edit any builtins, it changes only the
machine description.  "Of the corresponding builtins" :-)


Segher

      reply	other threads:[~2022-12-20 18:04 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-12-19  6:27 HAO CHEN GUI
2022-12-20 18:03 ` Segher Boessenkool [this message]

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