From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtpbgsg1.qq.com (smtpbgsg1.qq.com [54.254.200.92]) by sourceware.org (Postfix) with ESMTPS id F32703858D28 for ; Tue, 31 Jan 2023 12:16:55 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org F32703858D28 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp66t1675167409tgul1mgy Received: from rios-cad5.localdomain ( [58.60.1.11]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 31 Jan 2023 20:16:48 +0800 (CST) X-QQ-SSF: 01400000000000E0L000000A0000000 X-QQ-FEAT: 1VT9TMQFSYuaG/cI8704p8mSwJJtblPav/Z3mNYJO2bhgxlSf9KpvPsLrYWzj ho4/dj5xyWJe86EeF/c8djKFp5ljSXOzL7I2gH2FaOSAfkJG0Ac6dcFz56n/M2lkzSqj9rn cTsO3wQGZQM9MEQ/3/IaziTLyHypViudjjQiRCzvfzkrEOoui/KvnBGd7jZM+FjSMCTR/HQ N2D+6On4LzTBOMwz9SBevz+gPmvC4mDyQEN8E270eiyVO1z3uubegf6N5vI0/m+KNNzqeRu UHcyuQnUBQagooh+fUsTFozygXFhuxKtRsKcBtYbWbEKGja6fR8j3YRZLLh/yLsVN6Y8n2g kApiF01g2yxTvp/kACytUEw0M2GXCYd1S1nu37QA/Yy3WjxfU6HtcpTd7SrU8lrVlTfVu6X f4uhMs3tLSs= X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: Add srl.vv C API tests Date: Tue, 31 Jan 2023 20:16:47 +0800 Message-Id: <20230131121647.303063-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,KAM_SHORT,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Ju-Zhe Zhong gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/vsrl_vv-1.c: New test. * gcc.target/riscv/rvv/base/vsrl_vv-2.c: New test. * gcc.target/riscv/rvv/base/vsrl_vv-3.c: New test. * gcc.target/riscv/rvv/base/vsrl_vv_m-1.c: New test. * gcc.target/riscv/rvv/base/vsrl_vv_m-2.c: New test. * gcc.target/riscv/rvv/base/vsrl_vv_m-3.c: New test. * gcc.target/riscv/rvv/base/vsrl_vv_mu-1.c: New test. * gcc.target/riscv/rvv/base/vsrl_vv_mu-2.c: New test. * gcc.target/riscv/rvv/base/vsrl_vv_mu-3.c: New test. * gcc.target/riscv/rvv/base/vsrl_vv_tu-1.c: New test. * gcc.target/riscv/rvv/base/vsrl_vv_tu-2.c: New test. * gcc.target/riscv/rvv/base/vsrl_vv_tu-3.c: New test. * gcc.target/riscv/rvv/base/vsrl_vv_tum-1.c: New test. * gcc.target/riscv/rvv/base/vsrl_vv_tum-2.c: New test. * gcc.target/riscv/rvv/base/vsrl_vv_tum-3.c: New test. * gcc.target/riscv/rvv/base/vsrl_vv_tumu-1.c: New test. * gcc.target/riscv/rvv/base/vsrl_vv_tumu-2.c: New test. * gcc.target/riscv/rvv/base/vsrl_vv_tumu-3.c: New test. --- .../gcc.target/riscv/rvv/base/vsrl_vv-1.c | 160 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vsrl_vv-2.c | 160 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vsrl_vv-3.c | 160 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vsrl_vv_m-1.c | 160 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vsrl_vv_m-2.c | 160 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vsrl_vv_m-3.c | 160 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vsrl_vv_mu-1.c | 160 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vsrl_vv_mu-2.c | 160 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vsrl_vv_mu-3.c | 160 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vsrl_vv_tu-1.c | 160 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vsrl_vv_tu-2.c | 160 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vsrl_vv_tu-3.c | 160 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vsrl_vv_tum-1.c | 160 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vsrl_vv_tum-2.c | 160 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vsrl_vv_tum-3.c | 160 ++++++++++++++++++ .../riscv/rvv/base/vsrl_vv_tumu-1.c | 160 ++++++++++++++++++ .../riscv/rvv/base/vsrl_vv_tumu-2.c | 160 ++++++++++++++++++ .../riscv/rvv/base/vsrl_vv_tumu-3.c | 160 ++++++++++++++++++ 18 files changed, 2880 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_tumu-3.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv-1.c new file mode 100644 index 00000000000..a4c556adda0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv-1.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vsrl_vv_u8mf8(vuint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8mf8(op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vsrl_vv_u8mf4(vuint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8mf4(op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vsrl_vv_u8mf2(vuint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8mf2(op1,shift,vl); +} + + +vuint8m1_t test___riscv_vsrl_vv_u8m1(vuint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8m1(op1,shift,vl); +} + + +vuint8m2_t test___riscv_vsrl_vv_u8m2(vuint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8m2(op1,shift,vl); +} + + +vuint8m4_t test___riscv_vsrl_vv_u8m4(vuint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8m4(op1,shift,vl); +} + + +vuint8m8_t test___riscv_vsrl_vv_u8m8(vuint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8m8(op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vsrl_vv_u16mf4(vuint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16mf4(op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vsrl_vv_u16mf2(vuint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16mf2(op1,shift,vl); +} + + +vuint16m1_t test___riscv_vsrl_vv_u16m1(vuint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16m1(op1,shift,vl); +} + + +vuint16m2_t test___riscv_vsrl_vv_u16m2(vuint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16m2(op1,shift,vl); +} + + +vuint16m4_t test___riscv_vsrl_vv_u16m4(vuint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16m4(op1,shift,vl); +} + + +vuint16m8_t test___riscv_vsrl_vv_u16m8(vuint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16m8(op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vsrl_vv_u32mf2(vuint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32mf2(op1,shift,vl); +} + + +vuint32m1_t test___riscv_vsrl_vv_u32m1(vuint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32m1(op1,shift,vl); +} + + +vuint32m2_t test___riscv_vsrl_vv_u32m2(vuint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32m2(op1,shift,vl); +} + + +vuint32m4_t test___riscv_vsrl_vv_u32m4(vuint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32m4(op1,shift,vl); +} + + +vuint32m8_t test___riscv_vsrl_vv_u32m8(vuint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32m8(op1,shift,vl); +} + + +vuint64m1_t test___riscv_vsrl_vv_u64m1(vuint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u64m1(op1,shift,vl); +} + + +vuint64m2_t test___riscv_vsrl_vv_u64m2(vuint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u64m2(op1,shift,vl); +} + + +vuint64m4_t test___riscv_vsrl_vv_u64m4(vuint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u64m4(op1,shift,vl); +} + + +vuint64m8_t test___riscv_vsrl_vv_u64m8(vuint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u64m8(op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv-2.c new file mode 100644 index 00000000000..f21a4159a03 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv-2.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vsrl_vv_u8mf8(vuint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8mf8(op1,shift,31); +} + + +vuint8mf4_t test___riscv_vsrl_vv_u8mf4(vuint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8mf4(op1,shift,31); +} + + +vuint8mf2_t test___riscv_vsrl_vv_u8mf2(vuint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8mf2(op1,shift,31); +} + + +vuint8m1_t test___riscv_vsrl_vv_u8m1(vuint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8m1(op1,shift,31); +} + + +vuint8m2_t test___riscv_vsrl_vv_u8m2(vuint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8m2(op1,shift,31); +} + + +vuint8m4_t test___riscv_vsrl_vv_u8m4(vuint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8m4(op1,shift,31); +} + + +vuint8m8_t test___riscv_vsrl_vv_u8m8(vuint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8m8(op1,shift,31); +} + + +vuint16mf4_t test___riscv_vsrl_vv_u16mf4(vuint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16mf4(op1,shift,31); +} + + +vuint16mf2_t test___riscv_vsrl_vv_u16mf2(vuint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16mf2(op1,shift,31); +} + + +vuint16m1_t test___riscv_vsrl_vv_u16m1(vuint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16m1(op1,shift,31); +} + + +vuint16m2_t test___riscv_vsrl_vv_u16m2(vuint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16m2(op1,shift,31); +} + + +vuint16m4_t test___riscv_vsrl_vv_u16m4(vuint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16m4(op1,shift,31); +} + + +vuint16m8_t test___riscv_vsrl_vv_u16m8(vuint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16m8(op1,shift,31); +} + + +vuint32mf2_t test___riscv_vsrl_vv_u32mf2(vuint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32mf2(op1,shift,31); +} + + +vuint32m1_t test___riscv_vsrl_vv_u32m1(vuint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32m1(op1,shift,31); +} + + +vuint32m2_t test___riscv_vsrl_vv_u32m2(vuint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32m2(op1,shift,31); +} + + +vuint32m4_t test___riscv_vsrl_vv_u32m4(vuint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32m4(op1,shift,31); +} + + +vuint32m8_t test___riscv_vsrl_vv_u32m8(vuint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32m8(op1,shift,31); +} + + +vuint64m1_t test___riscv_vsrl_vv_u64m1(vuint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u64m1(op1,shift,31); +} + + +vuint64m2_t test___riscv_vsrl_vv_u64m2(vuint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u64m2(op1,shift,31); +} + + +vuint64m4_t test___riscv_vsrl_vv_u64m4(vuint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u64m4(op1,shift,31); +} + + +vuint64m8_t test___riscv_vsrl_vv_u64m8(vuint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u64m8(op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv-3.c new file mode 100644 index 00000000000..ffab5f50c02 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv-3.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vsrl_vv_u8mf8(vuint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8mf8(op1,shift,32); +} + + +vuint8mf4_t test___riscv_vsrl_vv_u8mf4(vuint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8mf4(op1,shift,32); +} + + +vuint8mf2_t test___riscv_vsrl_vv_u8mf2(vuint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8mf2(op1,shift,32); +} + + +vuint8m1_t test___riscv_vsrl_vv_u8m1(vuint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8m1(op1,shift,32); +} + + +vuint8m2_t test___riscv_vsrl_vv_u8m2(vuint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8m2(op1,shift,32); +} + + +vuint8m4_t test___riscv_vsrl_vv_u8m4(vuint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8m4(op1,shift,32); +} + + +vuint8m8_t test___riscv_vsrl_vv_u8m8(vuint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8m8(op1,shift,32); +} + + +vuint16mf4_t test___riscv_vsrl_vv_u16mf4(vuint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16mf4(op1,shift,32); +} + + +vuint16mf2_t test___riscv_vsrl_vv_u16mf2(vuint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16mf2(op1,shift,32); +} + + +vuint16m1_t test___riscv_vsrl_vv_u16m1(vuint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16m1(op1,shift,32); +} + + +vuint16m2_t test___riscv_vsrl_vv_u16m2(vuint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16m2(op1,shift,32); +} + + +vuint16m4_t test___riscv_vsrl_vv_u16m4(vuint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16m4(op1,shift,32); +} + + +vuint16m8_t test___riscv_vsrl_vv_u16m8(vuint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16m8(op1,shift,32); +} + + +vuint32mf2_t test___riscv_vsrl_vv_u32mf2(vuint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32mf2(op1,shift,32); +} + + +vuint32m1_t test___riscv_vsrl_vv_u32m1(vuint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32m1(op1,shift,32); +} + + +vuint32m2_t test___riscv_vsrl_vv_u32m2(vuint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32m2(op1,shift,32); +} + + +vuint32m4_t test___riscv_vsrl_vv_u32m4(vuint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32m4(op1,shift,32); +} + + +vuint32m8_t test___riscv_vsrl_vv_u32m8(vuint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32m8(op1,shift,32); +} + + +vuint64m1_t test___riscv_vsrl_vv_u64m1(vuint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u64m1(op1,shift,32); +} + + +vuint64m2_t test___riscv_vsrl_vv_u64m2(vuint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u64m2(op1,shift,32); +} + + +vuint64m4_t test___riscv_vsrl_vv_u64m4(vuint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u64m4(op1,shift,32); +} + + +vuint64m8_t test___riscv_vsrl_vv_u64m8(vuint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u64m8(op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_m-1.c new file mode 100644 index 00000000000..2674fa400e7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_m-1.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vsrl_vv_u8mf8_m(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8mf8_m(mask,op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vsrl_vv_u8mf4_m(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8mf4_m(mask,op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vsrl_vv_u8mf2_m(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8mf2_m(mask,op1,shift,vl); +} + + +vuint8m1_t test___riscv_vsrl_vv_u8m1_m(vbool8_t mask,vuint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8m1_m(mask,op1,shift,vl); +} + + +vuint8m2_t test___riscv_vsrl_vv_u8m2_m(vbool4_t mask,vuint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8m2_m(mask,op1,shift,vl); +} + + +vuint8m4_t test___riscv_vsrl_vv_u8m4_m(vbool2_t mask,vuint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8m4_m(mask,op1,shift,vl); +} + + +vuint8m8_t test___riscv_vsrl_vv_u8m8_m(vbool1_t mask,vuint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8m8_m(mask,op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vsrl_vv_u16mf4_m(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16mf4_m(mask,op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vsrl_vv_u16mf2_m(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16mf2_m(mask,op1,shift,vl); +} + + +vuint16m1_t test___riscv_vsrl_vv_u16m1_m(vbool16_t mask,vuint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16m1_m(mask,op1,shift,vl); +} + + +vuint16m2_t test___riscv_vsrl_vv_u16m2_m(vbool8_t mask,vuint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16m2_m(mask,op1,shift,vl); +} + + +vuint16m4_t test___riscv_vsrl_vv_u16m4_m(vbool4_t mask,vuint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16m4_m(mask,op1,shift,vl); +} + + +vuint16m8_t test___riscv_vsrl_vv_u16m8_m(vbool2_t mask,vuint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16m8_m(mask,op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vsrl_vv_u32mf2_m(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32mf2_m(mask,op1,shift,vl); +} + + +vuint32m1_t test___riscv_vsrl_vv_u32m1_m(vbool32_t mask,vuint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32m1_m(mask,op1,shift,vl); +} + + +vuint32m2_t test___riscv_vsrl_vv_u32m2_m(vbool16_t mask,vuint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32m2_m(mask,op1,shift,vl); +} + + +vuint32m4_t test___riscv_vsrl_vv_u32m4_m(vbool8_t mask,vuint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32m4_m(mask,op1,shift,vl); +} + + +vuint32m8_t test___riscv_vsrl_vv_u32m8_m(vbool4_t mask,vuint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32m8_m(mask,op1,shift,vl); +} + + +vuint64m1_t test___riscv_vsrl_vv_u64m1_m(vbool64_t mask,vuint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u64m1_m(mask,op1,shift,vl); +} + + +vuint64m2_t test___riscv_vsrl_vv_u64m2_m(vbool32_t mask,vuint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u64m2_m(mask,op1,shift,vl); +} + + +vuint64m4_t test___riscv_vsrl_vv_u64m4_m(vbool16_t mask,vuint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u64m4_m(mask,op1,shift,vl); +} + + +vuint64m8_t test___riscv_vsrl_vv_u64m8_m(vbool8_t mask,vuint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u64m8_m(mask,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_m-2.c new file mode 100644 index 00000000000..bd499021f79 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_m-2.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vsrl_vv_u8mf8_m(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8mf8_m(mask,op1,shift,31); +} + + +vuint8mf4_t test___riscv_vsrl_vv_u8mf4_m(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8mf4_m(mask,op1,shift,31); +} + + +vuint8mf2_t test___riscv_vsrl_vv_u8mf2_m(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8mf2_m(mask,op1,shift,31); +} + + +vuint8m1_t test___riscv_vsrl_vv_u8m1_m(vbool8_t mask,vuint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8m1_m(mask,op1,shift,31); +} + + +vuint8m2_t test___riscv_vsrl_vv_u8m2_m(vbool4_t mask,vuint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8m2_m(mask,op1,shift,31); +} + + +vuint8m4_t test___riscv_vsrl_vv_u8m4_m(vbool2_t mask,vuint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8m4_m(mask,op1,shift,31); +} + + +vuint8m8_t test___riscv_vsrl_vv_u8m8_m(vbool1_t mask,vuint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8m8_m(mask,op1,shift,31); +} + + +vuint16mf4_t test___riscv_vsrl_vv_u16mf4_m(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16mf4_m(mask,op1,shift,31); +} + + +vuint16mf2_t test___riscv_vsrl_vv_u16mf2_m(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16mf2_m(mask,op1,shift,31); +} + + +vuint16m1_t test___riscv_vsrl_vv_u16m1_m(vbool16_t mask,vuint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16m1_m(mask,op1,shift,31); +} + + +vuint16m2_t test___riscv_vsrl_vv_u16m2_m(vbool8_t mask,vuint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16m2_m(mask,op1,shift,31); +} + + +vuint16m4_t test___riscv_vsrl_vv_u16m4_m(vbool4_t mask,vuint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16m4_m(mask,op1,shift,31); +} + + +vuint16m8_t test___riscv_vsrl_vv_u16m8_m(vbool2_t mask,vuint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16m8_m(mask,op1,shift,31); +} + + +vuint32mf2_t test___riscv_vsrl_vv_u32mf2_m(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32mf2_m(mask,op1,shift,31); +} + + +vuint32m1_t test___riscv_vsrl_vv_u32m1_m(vbool32_t mask,vuint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32m1_m(mask,op1,shift,31); +} + + +vuint32m2_t test___riscv_vsrl_vv_u32m2_m(vbool16_t mask,vuint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32m2_m(mask,op1,shift,31); +} + + +vuint32m4_t test___riscv_vsrl_vv_u32m4_m(vbool8_t mask,vuint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32m4_m(mask,op1,shift,31); +} + + +vuint32m8_t test___riscv_vsrl_vv_u32m8_m(vbool4_t mask,vuint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32m8_m(mask,op1,shift,31); +} + + +vuint64m1_t test___riscv_vsrl_vv_u64m1_m(vbool64_t mask,vuint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u64m1_m(mask,op1,shift,31); +} + + +vuint64m2_t test___riscv_vsrl_vv_u64m2_m(vbool32_t mask,vuint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u64m2_m(mask,op1,shift,31); +} + + +vuint64m4_t test___riscv_vsrl_vv_u64m4_m(vbool16_t mask,vuint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u64m4_m(mask,op1,shift,31); +} + + +vuint64m8_t test___riscv_vsrl_vv_u64m8_m(vbool8_t mask,vuint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u64m8_m(mask,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_m-3.c new file mode 100644 index 00000000000..3d18432327c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_m-3.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vsrl_vv_u8mf8_m(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8mf8_m(mask,op1,shift,32); +} + + +vuint8mf4_t test___riscv_vsrl_vv_u8mf4_m(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8mf4_m(mask,op1,shift,32); +} + + +vuint8mf2_t test___riscv_vsrl_vv_u8mf2_m(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8mf2_m(mask,op1,shift,32); +} + + +vuint8m1_t test___riscv_vsrl_vv_u8m1_m(vbool8_t mask,vuint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8m1_m(mask,op1,shift,32); +} + + +vuint8m2_t test___riscv_vsrl_vv_u8m2_m(vbool4_t mask,vuint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8m2_m(mask,op1,shift,32); +} + + +vuint8m4_t test___riscv_vsrl_vv_u8m4_m(vbool2_t mask,vuint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8m4_m(mask,op1,shift,32); +} + + +vuint8m8_t test___riscv_vsrl_vv_u8m8_m(vbool1_t mask,vuint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8m8_m(mask,op1,shift,32); +} + + +vuint16mf4_t test___riscv_vsrl_vv_u16mf4_m(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16mf4_m(mask,op1,shift,32); +} + + +vuint16mf2_t test___riscv_vsrl_vv_u16mf2_m(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16mf2_m(mask,op1,shift,32); +} + + +vuint16m1_t test___riscv_vsrl_vv_u16m1_m(vbool16_t mask,vuint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16m1_m(mask,op1,shift,32); +} + + +vuint16m2_t test___riscv_vsrl_vv_u16m2_m(vbool8_t mask,vuint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16m2_m(mask,op1,shift,32); +} + + +vuint16m4_t test___riscv_vsrl_vv_u16m4_m(vbool4_t mask,vuint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16m4_m(mask,op1,shift,32); +} + + +vuint16m8_t test___riscv_vsrl_vv_u16m8_m(vbool2_t mask,vuint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16m8_m(mask,op1,shift,32); +} + + +vuint32mf2_t test___riscv_vsrl_vv_u32mf2_m(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32mf2_m(mask,op1,shift,32); +} + + +vuint32m1_t test___riscv_vsrl_vv_u32m1_m(vbool32_t mask,vuint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32m1_m(mask,op1,shift,32); +} + + +vuint32m2_t test___riscv_vsrl_vv_u32m2_m(vbool16_t mask,vuint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32m2_m(mask,op1,shift,32); +} + + +vuint32m4_t test___riscv_vsrl_vv_u32m4_m(vbool8_t mask,vuint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32m4_m(mask,op1,shift,32); +} + + +vuint32m8_t test___riscv_vsrl_vv_u32m8_m(vbool4_t mask,vuint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32m8_m(mask,op1,shift,32); +} + + +vuint64m1_t test___riscv_vsrl_vv_u64m1_m(vbool64_t mask,vuint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u64m1_m(mask,op1,shift,32); +} + + +vuint64m2_t test___riscv_vsrl_vv_u64m2_m(vbool32_t mask,vuint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u64m2_m(mask,op1,shift,32); +} + + +vuint64m4_t test___riscv_vsrl_vv_u64m4_m(vbool16_t mask,vuint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u64m4_m(mask,op1,shift,32); +} + + +vuint64m8_t test___riscv_vsrl_vv_u64m8_m(vbool8_t mask,vuint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u64m8_m(mask,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_mu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_mu-1.c new file mode 100644 index 00000000000..e55e6d0a807 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_mu-1.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vsrl_vv_u8mf8_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8mf8_mu(mask,merge,op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vsrl_vv_u8mf4_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8mf4_mu(mask,merge,op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vsrl_vv_u8mf2_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8mf2_mu(mask,merge,op1,shift,vl); +} + + +vuint8m1_t test___riscv_vsrl_vv_u8m1_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8m1_mu(mask,merge,op1,shift,vl); +} + + +vuint8m2_t test___riscv_vsrl_vv_u8m2_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8m2_mu(mask,merge,op1,shift,vl); +} + + +vuint8m4_t test___riscv_vsrl_vv_u8m4_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8m4_mu(mask,merge,op1,shift,vl); +} + + +vuint8m8_t test___riscv_vsrl_vv_u8m8_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8m8_mu(mask,merge,op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vsrl_vv_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16mf4_mu(mask,merge,op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vsrl_vv_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16mf2_mu(mask,merge,op1,shift,vl); +} + + +vuint16m1_t test___riscv_vsrl_vv_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16m1_mu(mask,merge,op1,shift,vl); +} + + +vuint16m2_t test___riscv_vsrl_vv_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16m2_mu(mask,merge,op1,shift,vl); +} + + +vuint16m4_t test___riscv_vsrl_vv_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16m4_mu(mask,merge,op1,shift,vl); +} + + +vuint16m8_t test___riscv_vsrl_vv_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16m8_mu(mask,merge,op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vsrl_vv_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32mf2_mu(mask,merge,op1,shift,vl); +} + + +vuint32m1_t test___riscv_vsrl_vv_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32m1_mu(mask,merge,op1,shift,vl); +} + + +vuint32m2_t test___riscv_vsrl_vv_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32m2_mu(mask,merge,op1,shift,vl); +} + + +vuint32m4_t test___riscv_vsrl_vv_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32m4_mu(mask,merge,op1,shift,vl); +} + + +vuint32m8_t test___riscv_vsrl_vv_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32m8_mu(mask,merge,op1,shift,vl); +} + + +vuint64m1_t test___riscv_vsrl_vv_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u64m1_mu(mask,merge,op1,shift,vl); +} + + +vuint64m2_t test___riscv_vsrl_vv_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u64m2_mu(mask,merge,op1,shift,vl); +} + + +vuint64m4_t test___riscv_vsrl_vv_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u64m4_mu(mask,merge,op1,shift,vl); +} + + +vuint64m8_t test___riscv_vsrl_vv_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u64m8_mu(mask,merge,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_mu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_mu-2.c new file mode 100644 index 00000000000..4f58100ecc8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_mu-2.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vsrl_vv_u8mf8_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8mf8_mu(mask,merge,op1,shift,31); +} + + +vuint8mf4_t test___riscv_vsrl_vv_u8mf4_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8mf4_mu(mask,merge,op1,shift,31); +} + + +vuint8mf2_t test___riscv_vsrl_vv_u8mf2_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8mf2_mu(mask,merge,op1,shift,31); +} + + +vuint8m1_t test___riscv_vsrl_vv_u8m1_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8m1_mu(mask,merge,op1,shift,31); +} + + +vuint8m2_t test___riscv_vsrl_vv_u8m2_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8m2_mu(mask,merge,op1,shift,31); +} + + +vuint8m4_t test___riscv_vsrl_vv_u8m4_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8m4_mu(mask,merge,op1,shift,31); +} + + +vuint8m8_t test___riscv_vsrl_vv_u8m8_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8m8_mu(mask,merge,op1,shift,31); +} + + +vuint16mf4_t test___riscv_vsrl_vv_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16mf4_mu(mask,merge,op1,shift,31); +} + + +vuint16mf2_t test___riscv_vsrl_vv_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16mf2_mu(mask,merge,op1,shift,31); +} + + +vuint16m1_t test___riscv_vsrl_vv_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16m1_mu(mask,merge,op1,shift,31); +} + + +vuint16m2_t test___riscv_vsrl_vv_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16m2_mu(mask,merge,op1,shift,31); +} + + +vuint16m4_t test___riscv_vsrl_vv_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16m4_mu(mask,merge,op1,shift,31); +} + + +vuint16m8_t test___riscv_vsrl_vv_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16m8_mu(mask,merge,op1,shift,31); +} + + +vuint32mf2_t test___riscv_vsrl_vv_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32mf2_mu(mask,merge,op1,shift,31); +} + + +vuint32m1_t test___riscv_vsrl_vv_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32m1_mu(mask,merge,op1,shift,31); +} + + +vuint32m2_t test___riscv_vsrl_vv_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32m2_mu(mask,merge,op1,shift,31); +} + + +vuint32m4_t test___riscv_vsrl_vv_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32m4_mu(mask,merge,op1,shift,31); +} + + +vuint32m8_t test___riscv_vsrl_vv_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32m8_mu(mask,merge,op1,shift,31); +} + + +vuint64m1_t test___riscv_vsrl_vv_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u64m1_mu(mask,merge,op1,shift,31); +} + + +vuint64m2_t test___riscv_vsrl_vv_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u64m2_mu(mask,merge,op1,shift,31); +} + + +vuint64m4_t test___riscv_vsrl_vv_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u64m4_mu(mask,merge,op1,shift,31); +} + + +vuint64m8_t test___riscv_vsrl_vv_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u64m8_mu(mask,merge,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_mu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_mu-3.c new file mode 100644 index 00000000000..78defb2f75d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_mu-3.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vsrl_vv_u8mf8_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8mf8_mu(mask,merge,op1,shift,32); +} + + +vuint8mf4_t test___riscv_vsrl_vv_u8mf4_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8mf4_mu(mask,merge,op1,shift,32); +} + + +vuint8mf2_t test___riscv_vsrl_vv_u8mf2_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8mf2_mu(mask,merge,op1,shift,32); +} + + +vuint8m1_t test___riscv_vsrl_vv_u8m1_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8m1_mu(mask,merge,op1,shift,32); +} + + +vuint8m2_t test___riscv_vsrl_vv_u8m2_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8m2_mu(mask,merge,op1,shift,32); +} + + +vuint8m4_t test___riscv_vsrl_vv_u8m4_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8m4_mu(mask,merge,op1,shift,32); +} + + +vuint8m8_t test___riscv_vsrl_vv_u8m8_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8m8_mu(mask,merge,op1,shift,32); +} + + +vuint16mf4_t test___riscv_vsrl_vv_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16mf4_mu(mask,merge,op1,shift,32); +} + + +vuint16mf2_t test___riscv_vsrl_vv_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16mf2_mu(mask,merge,op1,shift,32); +} + + +vuint16m1_t test___riscv_vsrl_vv_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16m1_mu(mask,merge,op1,shift,32); +} + + +vuint16m2_t test___riscv_vsrl_vv_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16m2_mu(mask,merge,op1,shift,32); +} + + +vuint16m4_t test___riscv_vsrl_vv_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16m4_mu(mask,merge,op1,shift,32); +} + + +vuint16m8_t test___riscv_vsrl_vv_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16m8_mu(mask,merge,op1,shift,32); +} + + +vuint32mf2_t test___riscv_vsrl_vv_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32mf2_mu(mask,merge,op1,shift,32); +} + + +vuint32m1_t test___riscv_vsrl_vv_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32m1_mu(mask,merge,op1,shift,32); +} + + +vuint32m2_t test___riscv_vsrl_vv_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32m2_mu(mask,merge,op1,shift,32); +} + + +vuint32m4_t test___riscv_vsrl_vv_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32m4_mu(mask,merge,op1,shift,32); +} + + +vuint32m8_t test___riscv_vsrl_vv_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32m8_mu(mask,merge,op1,shift,32); +} + + +vuint64m1_t test___riscv_vsrl_vv_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u64m1_mu(mask,merge,op1,shift,32); +} + + +vuint64m2_t test___riscv_vsrl_vv_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u64m2_mu(mask,merge,op1,shift,32); +} + + +vuint64m4_t test___riscv_vsrl_vv_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u64m4_mu(mask,merge,op1,shift,32); +} + + +vuint64m8_t test___riscv_vsrl_vv_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u64m8_mu(mask,merge,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_tu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_tu-1.c new file mode 100644 index 00000000000..ebe481b18c6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_tu-1.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vsrl_vv_u8mf8_tu(vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8mf8_tu(merge,op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vsrl_vv_u8mf4_tu(vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8mf4_tu(merge,op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vsrl_vv_u8mf2_tu(vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8mf2_tu(merge,op1,shift,vl); +} + + +vuint8m1_t test___riscv_vsrl_vv_u8m1_tu(vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8m1_tu(merge,op1,shift,vl); +} + + +vuint8m2_t test___riscv_vsrl_vv_u8m2_tu(vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8m2_tu(merge,op1,shift,vl); +} + + +vuint8m4_t test___riscv_vsrl_vv_u8m4_tu(vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8m4_tu(merge,op1,shift,vl); +} + + +vuint8m8_t test___riscv_vsrl_vv_u8m8_tu(vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8m8_tu(merge,op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vsrl_vv_u16mf4_tu(vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16mf4_tu(merge,op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vsrl_vv_u16mf2_tu(vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16mf2_tu(merge,op1,shift,vl); +} + + +vuint16m1_t test___riscv_vsrl_vv_u16m1_tu(vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16m1_tu(merge,op1,shift,vl); +} + + +vuint16m2_t test___riscv_vsrl_vv_u16m2_tu(vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16m2_tu(merge,op1,shift,vl); +} + + +vuint16m4_t test___riscv_vsrl_vv_u16m4_tu(vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16m4_tu(merge,op1,shift,vl); +} + + +vuint16m8_t test___riscv_vsrl_vv_u16m8_tu(vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16m8_tu(merge,op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vsrl_vv_u32mf2_tu(vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32mf2_tu(merge,op1,shift,vl); +} + + +vuint32m1_t test___riscv_vsrl_vv_u32m1_tu(vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32m1_tu(merge,op1,shift,vl); +} + + +vuint32m2_t test___riscv_vsrl_vv_u32m2_tu(vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32m2_tu(merge,op1,shift,vl); +} + + +vuint32m4_t test___riscv_vsrl_vv_u32m4_tu(vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32m4_tu(merge,op1,shift,vl); +} + + +vuint32m8_t test___riscv_vsrl_vv_u32m8_tu(vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32m8_tu(merge,op1,shift,vl); +} + + +vuint64m1_t test___riscv_vsrl_vv_u64m1_tu(vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u64m1_tu(merge,op1,shift,vl); +} + + +vuint64m2_t test___riscv_vsrl_vv_u64m2_tu(vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u64m2_tu(merge,op1,shift,vl); +} + + +vuint64m4_t test___riscv_vsrl_vv_u64m4_tu(vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u64m4_tu(merge,op1,shift,vl); +} + + +vuint64m8_t test___riscv_vsrl_vv_u64m8_tu(vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u64m8_tu(merge,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_tu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_tu-2.c new file mode 100644 index 00000000000..51840e85b6e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_tu-2.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vsrl_vv_u8mf8_tu(vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8mf8_tu(merge,op1,shift,31); +} + + +vuint8mf4_t test___riscv_vsrl_vv_u8mf4_tu(vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8mf4_tu(merge,op1,shift,31); +} + + +vuint8mf2_t test___riscv_vsrl_vv_u8mf2_tu(vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8mf2_tu(merge,op1,shift,31); +} + + +vuint8m1_t test___riscv_vsrl_vv_u8m1_tu(vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8m1_tu(merge,op1,shift,31); +} + + +vuint8m2_t test___riscv_vsrl_vv_u8m2_tu(vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8m2_tu(merge,op1,shift,31); +} + + +vuint8m4_t test___riscv_vsrl_vv_u8m4_tu(vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8m4_tu(merge,op1,shift,31); +} + + +vuint8m8_t test___riscv_vsrl_vv_u8m8_tu(vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8m8_tu(merge,op1,shift,31); +} + + +vuint16mf4_t test___riscv_vsrl_vv_u16mf4_tu(vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16mf4_tu(merge,op1,shift,31); +} + + +vuint16mf2_t test___riscv_vsrl_vv_u16mf2_tu(vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16mf2_tu(merge,op1,shift,31); +} + + +vuint16m1_t test___riscv_vsrl_vv_u16m1_tu(vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16m1_tu(merge,op1,shift,31); +} + + +vuint16m2_t test___riscv_vsrl_vv_u16m2_tu(vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16m2_tu(merge,op1,shift,31); +} + + +vuint16m4_t test___riscv_vsrl_vv_u16m4_tu(vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16m4_tu(merge,op1,shift,31); +} + + +vuint16m8_t test___riscv_vsrl_vv_u16m8_tu(vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16m8_tu(merge,op1,shift,31); +} + + +vuint32mf2_t test___riscv_vsrl_vv_u32mf2_tu(vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32mf2_tu(merge,op1,shift,31); +} + + +vuint32m1_t test___riscv_vsrl_vv_u32m1_tu(vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32m1_tu(merge,op1,shift,31); +} + + +vuint32m2_t test___riscv_vsrl_vv_u32m2_tu(vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32m2_tu(merge,op1,shift,31); +} + + +vuint32m4_t test___riscv_vsrl_vv_u32m4_tu(vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32m4_tu(merge,op1,shift,31); +} + + +vuint32m8_t test___riscv_vsrl_vv_u32m8_tu(vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32m8_tu(merge,op1,shift,31); +} + + +vuint64m1_t test___riscv_vsrl_vv_u64m1_tu(vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u64m1_tu(merge,op1,shift,31); +} + + +vuint64m2_t test___riscv_vsrl_vv_u64m2_tu(vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u64m2_tu(merge,op1,shift,31); +} + + +vuint64m4_t test___riscv_vsrl_vv_u64m4_tu(vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u64m4_tu(merge,op1,shift,31); +} + + +vuint64m8_t test___riscv_vsrl_vv_u64m8_tu(vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u64m8_tu(merge,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_tu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_tu-3.c new file mode 100644 index 00000000000..7e6975c5361 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_tu-3.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vsrl_vv_u8mf8_tu(vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8mf8_tu(merge,op1,shift,32); +} + + +vuint8mf4_t test___riscv_vsrl_vv_u8mf4_tu(vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8mf4_tu(merge,op1,shift,32); +} + + +vuint8mf2_t test___riscv_vsrl_vv_u8mf2_tu(vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8mf2_tu(merge,op1,shift,32); +} + + +vuint8m1_t test___riscv_vsrl_vv_u8m1_tu(vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8m1_tu(merge,op1,shift,32); +} + + +vuint8m2_t test___riscv_vsrl_vv_u8m2_tu(vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8m2_tu(merge,op1,shift,32); +} + + +vuint8m4_t test___riscv_vsrl_vv_u8m4_tu(vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8m4_tu(merge,op1,shift,32); +} + + +vuint8m8_t test___riscv_vsrl_vv_u8m8_tu(vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8m8_tu(merge,op1,shift,32); +} + + +vuint16mf4_t test___riscv_vsrl_vv_u16mf4_tu(vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16mf4_tu(merge,op1,shift,32); +} + + +vuint16mf2_t test___riscv_vsrl_vv_u16mf2_tu(vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16mf2_tu(merge,op1,shift,32); +} + + +vuint16m1_t test___riscv_vsrl_vv_u16m1_tu(vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16m1_tu(merge,op1,shift,32); +} + + +vuint16m2_t test___riscv_vsrl_vv_u16m2_tu(vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16m2_tu(merge,op1,shift,32); +} + + +vuint16m4_t test___riscv_vsrl_vv_u16m4_tu(vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16m4_tu(merge,op1,shift,32); +} + + +vuint16m8_t test___riscv_vsrl_vv_u16m8_tu(vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16m8_tu(merge,op1,shift,32); +} + + +vuint32mf2_t test___riscv_vsrl_vv_u32mf2_tu(vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32mf2_tu(merge,op1,shift,32); +} + + +vuint32m1_t test___riscv_vsrl_vv_u32m1_tu(vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32m1_tu(merge,op1,shift,32); +} + + +vuint32m2_t test___riscv_vsrl_vv_u32m2_tu(vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32m2_tu(merge,op1,shift,32); +} + + +vuint32m4_t test___riscv_vsrl_vv_u32m4_tu(vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32m4_tu(merge,op1,shift,32); +} + + +vuint32m8_t test___riscv_vsrl_vv_u32m8_tu(vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32m8_tu(merge,op1,shift,32); +} + + +vuint64m1_t test___riscv_vsrl_vv_u64m1_tu(vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u64m1_tu(merge,op1,shift,32); +} + + +vuint64m2_t test___riscv_vsrl_vv_u64m2_tu(vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u64m2_tu(merge,op1,shift,32); +} + + +vuint64m4_t test___riscv_vsrl_vv_u64m4_tu(vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u64m4_tu(merge,op1,shift,32); +} + + +vuint64m8_t test___riscv_vsrl_vv_u64m8_tu(vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u64m8_tu(merge,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_tum-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_tum-1.c new file mode 100644 index 00000000000..ab7bbbfb075 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_tum-1.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vsrl_vv_u8mf8_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8mf8_tum(mask,merge,op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vsrl_vv_u8mf4_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8mf4_tum(mask,merge,op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vsrl_vv_u8mf2_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8mf2_tum(mask,merge,op1,shift,vl); +} + + +vuint8m1_t test___riscv_vsrl_vv_u8m1_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8m1_tum(mask,merge,op1,shift,vl); +} + + +vuint8m2_t test___riscv_vsrl_vv_u8m2_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8m2_tum(mask,merge,op1,shift,vl); +} + + +vuint8m4_t test___riscv_vsrl_vv_u8m4_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8m4_tum(mask,merge,op1,shift,vl); +} + + +vuint8m8_t test___riscv_vsrl_vv_u8m8_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8m8_tum(mask,merge,op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vsrl_vv_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16mf4_tum(mask,merge,op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vsrl_vv_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16mf2_tum(mask,merge,op1,shift,vl); +} + + +vuint16m1_t test___riscv_vsrl_vv_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16m1_tum(mask,merge,op1,shift,vl); +} + + +vuint16m2_t test___riscv_vsrl_vv_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16m2_tum(mask,merge,op1,shift,vl); +} + + +vuint16m4_t test___riscv_vsrl_vv_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16m4_tum(mask,merge,op1,shift,vl); +} + + +vuint16m8_t test___riscv_vsrl_vv_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16m8_tum(mask,merge,op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vsrl_vv_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32mf2_tum(mask,merge,op1,shift,vl); +} + + +vuint32m1_t test___riscv_vsrl_vv_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32m1_tum(mask,merge,op1,shift,vl); +} + + +vuint32m2_t test___riscv_vsrl_vv_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32m2_tum(mask,merge,op1,shift,vl); +} + + +vuint32m4_t test___riscv_vsrl_vv_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32m4_tum(mask,merge,op1,shift,vl); +} + + +vuint32m8_t test___riscv_vsrl_vv_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32m8_tum(mask,merge,op1,shift,vl); +} + + +vuint64m1_t test___riscv_vsrl_vv_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u64m1_tum(mask,merge,op1,shift,vl); +} + + +vuint64m2_t test___riscv_vsrl_vv_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u64m2_tum(mask,merge,op1,shift,vl); +} + + +vuint64m4_t test___riscv_vsrl_vv_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u64m4_tum(mask,merge,op1,shift,vl); +} + + +vuint64m8_t test___riscv_vsrl_vv_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u64m8_tum(mask,merge,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_tum-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_tum-2.c new file mode 100644 index 00000000000..3a9c4060c51 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_tum-2.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vsrl_vv_u8mf8_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8mf8_tum(mask,merge,op1,shift,31); +} + + +vuint8mf4_t test___riscv_vsrl_vv_u8mf4_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8mf4_tum(mask,merge,op1,shift,31); +} + + +vuint8mf2_t test___riscv_vsrl_vv_u8mf2_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8mf2_tum(mask,merge,op1,shift,31); +} + + +vuint8m1_t test___riscv_vsrl_vv_u8m1_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8m1_tum(mask,merge,op1,shift,31); +} + + +vuint8m2_t test___riscv_vsrl_vv_u8m2_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8m2_tum(mask,merge,op1,shift,31); +} + + +vuint8m4_t test___riscv_vsrl_vv_u8m4_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8m4_tum(mask,merge,op1,shift,31); +} + + +vuint8m8_t test___riscv_vsrl_vv_u8m8_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8m8_tum(mask,merge,op1,shift,31); +} + + +vuint16mf4_t test___riscv_vsrl_vv_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16mf4_tum(mask,merge,op1,shift,31); +} + + +vuint16mf2_t test___riscv_vsrl_vv_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16mf2_tum(mask,merge,op1,shift,31); +} + + +vuint16m1_t test___riscv_vsrl_vv_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16m1_tum(mask,merge,op1,shift,31); +} + + +vuint16m2_t test___riscv_vsrl_vv_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16m2_tum(mask,merge,op1,shift,31); +} + + +vuint16m4_t test___riscv_vsrl_vv_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16m4_tum(mask,merge,op1,shift,31); +} + + +vuint16m8_t test___riscv_vsrl_vv_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16m8_tum(mask,merge,op1,shift,31); +} + + +vuint32mf2_t test___riscv_vsrl_vv_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32mf2_tum(mask,merge,op1,shift,31); +} + + +vuint32m1_t test___riscv_vsrl_vv_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32m1_tum(mask,merge,op1,shift,31); +} + + +vuint32m2_t test___riscv_vsrl_vv_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32m2_tum(mask,merge,op1,shift,31); +} + + +vuint32m4_t test___riscv_vsrl_vv_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32m4_tum(mask,merge,op1,shift,31); +} + + +vuint32m8_t test___riscv_vsrl_vv_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32m8_tum(mask,merge,op1,shift,31); +} + + +vuint64m1_t test___riscv_vsrl_vv_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u64m1_tum(mask,merge,op1,shift,31); +} + + +vuint64m2_t test___riscv_vsrl_vv_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u64m2_tum(mask,merge,op1,shift,31); +} + + +vuint64m4_t test___riscv_vsrl_vv_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u64m4_tum(mask,merge,op1,shift,31); +} + + +vuint64m8_t test___riscv_vsrl_vv_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u64m8_tum(mask,merge,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_tum-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_tum-3.c new file mode 100644 index 00000000000..ed46bd08d9c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_tum-3.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vsrl_vv_u8mf8_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8mf8_tum(mask,merge,op1,shift,32); +} + + +vuint8mf4_t test___riscv_vsrl_vv_u8mf4_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8mf4_tum(mask,merge,op1,shift,32); +} + + +vuint8mf2_t test___riscv_vsrl_vv_u8mf2_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8mf2_tum(mask,merge,op1,shift,32); +} + + +vuint8m1_t test___riscv_vsrl_vv_u8m1_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8m1_tum(mask,merge,op1,shift,32); +} + + +vuint8m2_t test___riscv_vsrl_vv_u8m2_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8m2_tum(mask,merge,op1,shift,32); +} + + +vuint8m4_t test___riscv_vsrl_vv_u8m4_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8m4_tum(mask,merge,op1,shift,32); +} + + +vuint8m8_t test___riscv_vsrl_vv_u8m8_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8m8_tum(mask,merge,op1,shift,32); +} + + +vuint16mf4_t test___riscv_vsrl_vv_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16mf4_tum(mask,merge,op1,shift,32); +} + + +vuint16mf2_t test___riscv_vsrl_vv_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16mf2_tum(mask,merge,op1,shift,32); +} + + +vuint16m1_t test___riscv_vsrl_vv_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16m1_tum(mask,merge,op1,shift,32); +} + + +vuint16m2_t test___riscv_vsrl_vv_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16m2_tum(mask,merge,op1,shift,32); +} + + +vuint16m4_t test___riscv_vsrl_vv_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16m4_tum(mask,merge,op1,shift,32); +} + + +vuint16m8_t test___riscv_vsrl_vv_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16m8_tum(mask,merge,op1,shift,32); +} + + +vuint32mf2_t test___riscv_vsrl_vv_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32mf2_tum(mask,merge,op1,shift,32); +} + + +vuint32m1_t test___riscv_vsrl_vv_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32m1_tum(mask,merge,op1,shift,32); +} + + +vuint32m2_t test___riscv_vsrl_vv_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32m2_tum(mask,merge,op1,shift,32); +} + + +vuint32m4_t test___riscv_vsrl_vv_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32m4_tum(mask,merge,op1,shift,32); +} + + +vuint32m8_t test___riscv_vsrl_vv_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32m8_tum(mask,merge,op1,shift,32); +} + + +vuint64m1_t test___riscv_vsrl_vv_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u64m1_tum(mask,merge,op1,shift,32); +} + + +vuint64m2_t test___riscv_vsrl_vv_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u64m2_tum(mask,merge,op1,shift,32); +} + + +vuint64m4_t test___riscv_vsrl_vv_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u64m4_tum(mask,merge,op1,shift,32); +} + + +vuint64m8_t test___riscv_vsrl_vv_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u64m8_tum(mask,merge,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_tumu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_tumu-1.c new file mode 100644 index 00000000000..875435d4b2c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_tumu-1.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vsrl_vv_u8mf8_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8mf8_tumu(mask,merge,op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vsrl_vv_u8mf4_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8mf4_tumu(mask,merge,op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vsrl_vv_u8mf2_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8mf2_tumu(mask,merge,op1,shift,vl); +} + + +vuint8m1_t test___riscv_vsrl_vv_u8m1_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8m1_tumu(mask,merge,op1,shift,vl); +} + + +vuint8m2_t test___riscv_vsrl_vv_u8m2_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8m2_tumu(mask,merge,op1,shift,vl); +} + + +vuint8m4_t test___riscv_vsrl_vv_u8m4_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8m4_tumu(mask,merge,op1,shift,vl); +} + + +vuint8m8_t test___riscv_vsrl_vv_u8m8_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8m8_tumu(mask,merge,op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vsrl_vv_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16mf4_tumu(mask,merge,op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vsrl_vv_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16mf2_tumu(mask,merge,op1,shift,vl); +} + + +vuint16m1_t test___riscv_vsrl_vv_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16m1_tumu(mask,merge,op1,shift,vl); +} + + +vuint16m2_t test___riscv_vsrl_vv_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16m2_tumu(mask,merge,op1,shift,vl); +} + + +vuint16m4_t test___riscv_vsrl_vv_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16m4_tumu(mask,merge,op1,shift,vl); +} + + +vuint16m8_t test___riscv_vsrl_vv_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16m8_tumu(mask,merge,op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vsrl_vv_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32mf2_tumu(mask,merge,op1,shift,vl); +} + + +vuint32m1_t test___riscv_vsrl_vv_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32m1_tumu(mask,merge,op1,shift,vl); +} + + +vuint32m2_t test___riscv_vsrl_vv_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32m2_tumu(mask,merge,op1,shift,vl); +} + + +vuint32m4_t test___riscv_vsrl_vv_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32m4_tumu(mask,merge,op1,shift,vl); +} + + +vuint32m8_t test___riscv_vsrl_vv_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32m8_tumu(mask,merge,op1,shift,vl); +} + + +vuint64m1_t test___riscv_vsrl_vv_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u64m1_tumu(mask,merge,op1,shift,vl); +} + + +vuint64m2_t test___riscv_vsrl_vv_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u64m2_tumu(mask,merge,op1,shift,vl); +} + + +vuint64m4_t test___riscv_vsrl_vv_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u64m4_tumu(mask,merge,op1,shift,vl); +} + + +vuint64m8_t test___riscv_vsrl_vv_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u64m8_tumu(mask,merge,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_tumu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_tumu-2.c new file mode 100644 index 00000000000..30d1b5f4738 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_tumu-2.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vsrl_vv_u8mf8_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8mf8_tumu(mask,merge,op1,shift,31); +} + + +vuint8mf4_t test___riscv_vsrl_vv_u8mf4_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8mf4_tumu(mask,merge,op1,shift,31); +} + + +vuint8mf2_t test___riscv_vsrl_vv_u8mf2_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8mf2_tumu(mask,merge,op1,shift,31); +} + + +vuint8m1_t test___riscv_vsrl_vv_u8m1_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8m1_tumu(mask,merge,op1,shift,31); +} + + +vuint8m2_t test___riscv_vsrl_vv_u8m2_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8m2_tumu(mask,merge,op1,shift,31); +} + + +vuint8m4_t test___riscv_vsrl_vv_u8m4_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8m4_tumu(mask,merge,op1,shift,31); +} + + +vuint8m8_t test___riscv_vsrl_vv_u8m8_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8m8_tumu(mask,merge,op1,shift,31); +} + + +vuint16mf4_t test___riscv_vsrl_vv_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16mf4_tumu(mask,merge,op1,shift,31); +} + + +vuint16mf2_t test___riscv_vsrl_vv_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16mf2_tumu(mask,merge,op1,shift,31); +} + + +vuint16m1_t test___riscv_vsrl_vv_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16m1_tumu(mask,merge,op1,shift,31); +} + + +vuint16m2_t test___riscv_vsrl_vv_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16m2_tumu(mask,merge,op1,shift,31); +} + + +vuint16m4_t test___riscv_vsrl_vv_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16m4_tumu(mask,merge,op1,shift,31); +} + + +vuint16m8_t test___riscv_vsrl_vv_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16m8_tumu(mask,merge,op1,shift,31); +} + + +vuint32mf2_t test___riscv_vsrl_vv_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32mf2_tumu(mask,merge,op1,shift,31); +} + + +vuint32m1_t test___riscv_vsrl_vv_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32m1_tumu(mask,merge,op1,shift,31); +} + + +vuint32m2_t test___riscv_vsrl_vv_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32m2_tumu(mask,merge,op1,shift,31); +} + + +vuint32m4_t test___riscv_vsrl_vv_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32m4_tumu(mask,merge,op1,shift,31); +} + + +vuint32m8_t test___riscv_vsrl_vv_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32m8_tumu(mask,merge,op1,shift,31); +} + + +vuint64m1_t test___riscv_vsrl_vv_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u64m1_tumu(mask,merge,op1,shift,31); +} + + +vuint64m2_t test___riscv_vsrl_vv_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u64m2_tumu(mask,merge,op1,shift,31); +} + + +vuint64m4_t test___riscv_vsrl_vv_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u64m4_tumu(mask,merge,op1,shift,31); +} + + +vuint64m8_t test___riscv_vsrl_vv_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u64m8_tumu(mask,merge,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_tumu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_tumu-3.c new file mode 100644 index 00000000000..cfd1fcca6fe --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vv_tumu-3.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vsrl_vv_u8mf8_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8mf8_tumu(mask,merge,op1,shift,32); +} + + +vuint8mf4_t test___riscv_vsrl_vv_u8mf4_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8mf4_tumu(mask,merge,op1,shift,32); +} + + +vuint8mf2_t test___riscv_vsrl_vv_u8mf2_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8mf2_tumu(mask,merge,op1,shift,32); +} + + +vuint8m1_t test___riscv_vsrl_vv_u8m1_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8m1_tumu(mask,merge,op1,shift,32); +} + + +vuint8m2_t test___riscv_vsrl_vv_u8m2_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8m2_tumu(mask,merge,op1,shift,32); +} + + +vuint8m4_t test___riscv_vsrl_vv_u8m4_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8m4_tumu(mask,merge,op1,shift,32); +} + + +vuint8m8_t test___riscv_vsrl_vv_u8m8_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u8m8_tumu(mask,merge,op1,shift,32); +} + + +vuint16mf4_t test___riscv_vsrl_vv_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16mf4_tumu(mask,merge,op1,shift,32); +} + + +vuint16mf2_t test___riscv_vsrl_vv_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16mf2_tumu(mask,merge,op1,shift,32); +} + + +vuint16m1_t test___riscv_vsrl_vv_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16m1_tumu(mask,merge,op1,shift,32); +} + + +vuint16m2_t test___riscv_vsrl_vv_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16m2_tumu(mask,merge,op1,shift,32); +} + + +vuint16m4_t test___riscv_vsrl_vv_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16m4_tumu(mask,merge,op1,shift,32); +} + + +vuint16m8_t test___riscv_vsrl_vv_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u16m8_tumu(mask,merge,op1,shift,32); +} + + +vuint32mf2_t test___riscv_vsrl_vv_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32mf2_tumu(mask,merge,op1,shift,32); +} + + +vuint32m1_t test___riscv_vsrl_vv_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32m1_tumu(mask,merge,op1,shift,32); +} + + +vuint32m2_t test___riscv_vsrl_vv_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32m2_tumu(mask,merge,op1,shift,32); +} + + +vuint32m4_t test___riscv_vsrl_vv_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32m4_tumu(mask,merge,op1,shift,32); +} + + +vuint32m8_t test___riscv_vsrl_vv_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u32m8_tumu(mask,merge,op1,shift,32); +} + + +vuint64m1_t test___riscv_vsrl_vv_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u64m1_tumu(mask,merge,op1,shift,32); +} + + +vuint64m2_t test___riscv_vsrl_vv_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u64m2_tumu(mask,merge,op1,shift,32); +} + + +vuint64m4_t test___riscv_vsrl_vv_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u64m4_tumu(mask,merge,op1,shift,32); +} + + +vuint64m8_t test___riscv_vsrl_vv_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vsrl_vv_u64m8_tumu(mask,merge,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ -- 2.36.3