From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtpbgau2.qq.com (smtpbgau2.qq.com [54.206.34.216]) by sourceware.org (Postfix) with ESMTPS id 872983858D28 for ; Tue, 31 Jan 2023 12:39:42 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 872983858D28 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp86t1675168776tse1yo1j Received: from rios-cad5.localdomain ( [58.60.1.11]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 31 Jan 2023 20:39:34 +0800 (CST) X-QQ-SSF: 01400000000000E0L000000A0000000 X-QQ-FEAT: 0laiA9+vjABjnhlqBS1WhQY9SCUgxUKkQKDj7yGz++U2UkrE69lRVe/l4tWG0 q7IH3hqClLKaVFlTqZnl2RhOZBcqaFJ5jQFDH/naJS6oJsmD5iPSuHOJZqtOlvJURQJUmh4 IEBMksbFblYYxyBqpWWSPRC/tjrommQs3+swNiNwCspLvwuTb4P5HAUYaZjrzbynzPLl+Nt qVLZIPmqZfDhuq3ElFA/2iKtNu6WIT06muDWvCwuS1LeVmjfIG1rDo7w0D8rOzLNb2xszbL +tt1dCi4LkZ2ZheBuJvXE+jusAb2Q68ED6RbFrYcdJA5UWivm6Eb/OWZSReWSjoz0n/s4TL le1DIGLOrZyUAeP9R2BSDdvGIRyNQ8uGYEm0QtkKktVrV+SV6rGb3gCUEpWMfO3IHN3J493 t48ndkgdibc= X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: Add binop constraint tests Date: Tue, 31 Jan 2023 20:39:33 +0800 Message-Id: <20230131123933.312078-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-2.7 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,KAM_SHORT,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS,TXREP,UNWANTED_LANGUAGE_BODY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Ju-Zhe Zhong gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/binop_vv_constraint-1.c: New test. --- .../riscv/rvv/base/binop_vv_constraint-1.c | 132 ++++++++++++++++++ 1 file changed, 132 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vv_constraint-1.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vv_constraint-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vv_constraint-1.c new file mode 100644 index 00000000000..3ab1ccee035 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/binop_vv_constraint-1.c @@ -0,0 +1,132 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_vector.h" + +/* +** f1: +** vsetivli\tzero,4,e32,m1,tu,ma +** vle32\.v\tv[0-9]+,0\([a-x0-9]+\) +** vle32\.v\tv[0-9]+,0\([a-x0-9]+\) +** vadd\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** vadd\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** vse32\.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f1 (void * in, void *out) +{ + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tu (v, in, 4); + vint32m1_t v3 = __riscv_vadd_vv_i32m1 (v2, v2, 4); + vint32m1_t v4 = __riscv_vadd_vv_i32m1_tu (v3, v2, v2, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f2: +** vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma +** vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** vsetivli\tzero,4,e32,m1,ta,ma +** vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** vadd\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** vadd\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t +** vse32.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f2 (void * in, void *out) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_m (mask, in, 4); + vint32m1_t v3 = __riscv_vadd_vv_i32m1 (v2, v2, 4); + vint32m1_t v4 = __riscv_vadd_vv_i32m1_m (mask, v3, v3, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f3: +** vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma +** vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** vsetivli\tzero,4,e32,m1,tu,mu +** vle32\.v\tv[0-9]+,0\([a-x0-9]+\) +** vle32.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** vadd\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** vadd\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t +** vse32.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f3 (void * in, void *out) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint32m1_t v = __riscv_vle32_v_i32m1 (in, 4); + vint32m1_t v2 = __riscv_vle32_v_i32m1_tumu (mask, v, in, 4); + vint32m1_t v3 = __riscv_vadd_vv_i32m1 (v2, v2, 4); + vint32m1_t v4 = __riscv_vadd_vv_i32m1_tumu (mask, v3, v2, v2, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f4: +** vsetivli\tzero,4,e8,mf8,tu,ma +** vle8\.v\tv[0-9]+,0\([a-x0-9]+\) +** vle8\.v\tv[0-9]+,0\([a-x0-9]+\) +** vadd\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** vadd\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** vse8\.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f4 (void * in, void *out) +{ + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in, 4); + vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tu (v, in, 4); + vint8mf8_t v3 = __riscv_vadd_vv_i8mf8 (v2, v2, 4); + vint8mf8_t v4 = __riscv_vadd_vv_i8mf8_tu (v3, v2, v2, 4); + __riscv_vse8_v_i8mf8 (out, v4, 4); +} + +/* +** f5: +** vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma +** vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** vsetivli\tzero,4,e8,mf8,ta,ma +** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** vadd\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** vadd\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t +** vse8.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f5 (void * in, void *out) +{ + vbool64_t mask = *(vbool64_t*)in; + asm volatile ("":::"memory"); + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in, 4); + vint8mf8_t v2 = __riscv_vle8_v_i8mf8_m (mask, in, 4); + vint8mf8_t v3 = __riscv_vadd_vv_i8mf8 (v2, v2, 4); + vint8mf8_t v4 = __riscv_vadd_vv_i8mf8_m (mask, v3, v3, 4); + __riscv_vse8_v_i8mf8 (out, v4, 4); +} + +/* +** f6: +** vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma +** vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** vsetivli\tzero,4,e8,mf8,tu,mu +** vle8\.v\tv[0-9]+,0\([a-x0-9]+\) +** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** vadd\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+ +** vadd\.vv\tv[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t +** vse8.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f6 (void * in, void *out) +{ + vbool64_t mask = *(vbool64_t*)in; + asm volatile ("":::"memory"); + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in, 4); + vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tumu (mask, v, in, 4); + vint8mf8_t v3 = __riscv_vadd_vv_i8mf8 (v2, v2, 4); + vint8mf8_t v4 = __riscv_vadd_vv_i8mf8_tumu (mask, v3, v2, v2, 4); + __riscv_vse8_v_i8mf8 (out, v4, 4); +} -- 2.36.3