From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtpbgeu2.qq.com (smtpbgeu2.qq.com [18.194.254.142]) by sourceware.org (Postfix) with ESMTPS id B5FD33858D28 for ; Tue, 31 Jan 2023 12:41:14 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org B5FD33858D28 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp67t1675168868txdh92zl Received: from rios-cad5.localdomain ( [58.60.1.11]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 31 Jan 2023 20:41:07 +0800 (CST) X-QQ-SSF: 01400000000000E0L000000A0000000 X-QQ-FEAT: +ynUkgUhZJmnLeb1nv7s36zlgR6lfbbSJCMqwHXweMMgsyHXncKJeGVudwGbH Vy6kLcj17AKi2H3BH5FkYM9FC4aVPvbWb/uQou7yGD9bHVHk+x1pjY/f66EgdqCqKdpEwmL zqKm0Oaw2a4LILvs+Lq6ch/km+AUFvZ+BtGSzvOYx7EAyIlQLZScjcoKsadvEiAZJycJrBr DHeypftdUptDhum1PhjVdC4lF4W06pzgbILgaREsL51unqei4+ucALIdsV8MNTAdiZDzqaI aoYkWA2S4gDWOgzA4oqXrGgi8t973kXpFWVkTvKzACdb8/9pEhARq34pQpcqnLxa7j4lF58 EGpBPzBIB+NWWKo6O+ggf/BPJes33K+K4+POWxfdwMFLf9TnXdz47S/2yahVyLl+kBhhlHa X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: Add vadd.vv C++ API tests Date: Tue, 31 Jan 2023 20:41:06 +0800 Message-Id: <20230131124106.312795-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_PASS,TXREP,T_SPF_HELO_TEMPERROR autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Ju-Zhe Zhong gcc/testsuite/ChangeLog: * g++.target/riscv/rvv/base/vadd_vv-1.C: New test. * g++.target/riscv/rvv/base/vadd_vv-2.C: New test. * g++.target/riscv/rvv/base/vadd_vv-3.C: New test. * g++.target/riscv/rvv/base/vadd_vv_mu-1.C: New test. * g++.target/riscv/rvv/base/vadd_vv_mu-2.C: New test. * g++.target/riscv/rvv/base/vadd_vv_mu-3.C: New test. * g++.target/riscv/rvv/base/vadd_vv_tu-1.C: New test. * g++.target/riscv/rvv/base/vadd_vv_tu-2.C: New test. * g++.target/riscv/rvv/base/vadd_vv_tu-3.C: New test. * g++.target/riscv/rvv/base/vadd_vv_tum-1.C: New test. * g++.target/riscv/rvv/base/vadd_vv_tum-2.C: New test. * g++.target/riscv/rvv/base/vadd_vv_tum-3.C: New test. * g++.target/riscv/rvv/base/vadd_vv_tumu-1.C: New test. * g++.target/riscv/rvv/base/vadd_vv_tumu-2.C: New test. * g++.target/riscv/rvv/base/vadd_vv_tumu-3.C: New test. --- .../g++.target/riscv/rvv/base/vadd_vv-1.C | 578 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vadd_vv-2.C | 578 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vadd_vv-3.C | 578 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vadd_vv_mu-1.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vadd_vv_mu-2.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vadd_vv_mu-3.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vadd_vv_tu-1.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vadd_vv_tu-2.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vadd_vv_tu-3.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vadd_vv_tum-1.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vadd_vv_tum-2.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vadd_vv_tum-3.C | 292 +++++++++ .../riscv/rvv/base/vadd_vv_tumu-1.C | 292 +++++++++ .../riscv/rvv/base/vadd_vv_tumu-2.C | 292 +++++++++ .../riscv/rvv/base/vadd_vv_tumu-3.C | 292 +++++++++ 15 files changed, 5238 insertions(+) create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv_tumu-3.C diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv-1.C new file mode 100644 index 00000000000..01cd34b941e --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv-1.C @@ -0,0 +1,578 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd(vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint8mf4_t test___riscv_vadd(vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint8mf2_t test___riscv_vadd(vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint8m1_t test___riscv_vadd(vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint8m2_t test___riscv_vadd(vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint8m4_t test___riscv_vadd(vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint8m8_t test___riscv_vadd(vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint16mf4_t test___riscv_vadd(vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint16mf2_t test___riscv_vadd(vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint16m1_t test___riscv_vadd(vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint16m2_t test___riscv_vadd(vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint16m4_t test___riscv_vadd(vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint16m8_t test___riscv_vadd(vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint32mf2_t test___riscv_vadd(vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint32m1_t test___riscv_vadd(vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint32m2_t test___riscv_vadd(vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint32m4_t test___riscv_vadd(vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint32m8_t test___riscv_vadd(vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint64m1_t test___riscv_vadd(vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint64m2_t test___riscv_vadd(vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint64m4_t test___riscv_vadd(vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint64m8_t test___riscv_vadd(vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vadd(vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vadd(vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vadd(vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint8m1_t test___riscv_vadd(vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint8m2_t test___riscv_vadd(vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint8m4_t test___riscv_vadd(vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint8m8_t test___riscv_vadd(vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vadd(vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vadd(vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint16m1_t test___riscv_vadd(vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint16m2_t test___riscv_vadd(vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint16m4_t test___riscv_vadd(vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint16m8_t test___riscv_vadd(vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vadd(vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint32m1_t test___riscv_vadd(vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint32m2_t test___riscv_vadd(vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint32m4_t test___riscv_vadd(vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint32m8_t test___riscv_vadd(vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint64m1_t test___riscv_vadd(vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint64m2_t test___riscv_vadd(vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint64m4_t test___riscv_vadd(vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vuint64m8_t test___riscv_vadd(vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,vl); +} + + +vint8mf8_t test___riscv_vadd(vbool64_t mask,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vadd(vbool32_t mask,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vadd(vbool16_t mask,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint8m1_t test___riscv_vadd(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint8m2_t test___riscv_vadd(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint8m4_t test___riscv_vadd(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint8m8_t test___riscv_vadd(vbool1_t mask,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vadd(vbool64_t mask,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vadd(vbool32_t mask,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint16m1_t test___riscv_vadd(vbool16_t mask,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint16m2_t test___riscv_vadd(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint16m4_t test___riscv_vadd(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint16m8_t test___riscv_vadd(vbool2_t mask,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vadd(vbool64_t mask,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint32m1_t test___riscv_vadd(vbool32_t mask,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint32m2_t test___riscv_vadd(vbool16_t mask,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint32m4_t test___riscv_vadd(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint32m8_t test___riscv_vadd(vbool4_t mask,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint64m1_t test___riscv_vadd(vbool64_t mask,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint64m2_t test___riscv_vadd(vbool32_t mask,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint64m4_t test___riscv_vadd(vbool16_t mask,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vint64m8_t test___riscv_vadd(vbool8_t mask,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vadd(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vadd(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vadd(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vadd(vbool8_t mask,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vadd(vbool4_t mask,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vadd(vbool2_t mask,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vadd(vbool1_t mask,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vadd(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vadd(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vadd(vbool16_t mask,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vadd(vbool8_t mask,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vadd(vbool4_t mask,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vadd(vbool2_t mask,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vadd(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vadd(vbool32_t mask,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vadd(vbool16_t mask,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vadd(vbool8_t mask,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vadd(vbool4_t mask,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vadd(vbool64_t mask,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vadd(vbool32_t mask,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vadd(vbool16_t mask,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vadd(vbool8_t mask,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv-2.C new file mode 100644 index 00000000000..8c1a89896e7 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv-2.C @@ -0,0 +1,578 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd(vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint8mf4_t test___riscv_vadd(vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint8mf2_t test___riscv_vadd(vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint8m1_t test___riscv_vadd(vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint8m2_t test___riscv_vadd(vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint8m4_t test___riscv_vadd(vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint8m8_t test___riscv_vadd(vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint16mf4_t test___riscv_vadd(vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint16mf2_t test___riscv_vadd(vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint16m1_t test___riscv_vadd(vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint16m2_t test___riscv_vadd(vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint16m4_t test___riscv_vadd(vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint16m8_t test___riscv_vadd(vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint32mf2_t test___riscv_vadd(vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint32m1_t test___riscv_vadd(vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint32m2_t test___riscv_vadd(vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint32m4_t test___riscv_vadd(vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint32m8_t test___riscv_vadd(vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint64m1_t test___riscv_vadd(vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint64m2_t test___riscv_vadd(vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint64m4_t test___riscv_vadd(vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint64m8_t test___riscv_vadd(vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint8mf8_t test___riscv_vadd(vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint8mf4_t test___riscv_vadd(vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint8mf2_t test___riscv_vadd(vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint8m1_t test___riscv_vadd(vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint8m2_t test___riscv_vadd(vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint8m4_t test___riscv_vadd(vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint8m8_t test___riscv_vadd(vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint16mf4_t test___riscv_vadd(vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint16mf2_t test___riscv_vadd(vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint16m1_t test___riscv_vadd(vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint16m2_t test___riscv_vadd(vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint16m4_t test___riscv_vadd(vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint16m8_t test___riscv_vadd(vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint32mf2_t test___riscv_vadd(vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint32m1_t test___riscv_vadd(vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint32m2_t test___riscv_vadd(vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint32m4_t test___riscv_vadd(vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint32m8_t test___riscv_vadd(vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint64m1_t test___riscv_vadd(vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint64m2_t test___riscv_vadd(vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint64m4_t test___riscv_vadd(vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vuint64m8_t test___riscv_vadd(vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,31); +} + + +vint8mf8_t test___riscv_vadd(vbool64_t mask,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint8mf4_t test___riscv_vadd(vbool32_t mask,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint8mf2_t test___riscv_vadd(vbool16_t mask,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint8m1_t test___riscv_vadd(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint8m2_t test___riscv_vadd(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint8m4_t test___riscv_vadd(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint8m8_t test___riscv_vadd(vbool1_t mask,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint16mf4_t test___riscv_vadd(vbool64_t mask,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint16mf2_t test___riscv_vadd(vbool32_t mask,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint16m1_t test___riscv_vadd(vbool16_t mask,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint16m2_t test___riscv_vadd(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint16m4_t test___riscv_vadd(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint16m8_t test___riscv_vadd(vbool2_t mask,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint32mf2_t test___riscv_vadd(vbool64_t mask,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint32m1_t test___riscv_vadd(vbool32_t mask,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint32m2_t test___riscv_vadd(vbool16_t mask,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint32m4_t test___riscv_vadd(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint32m8_t test___riscv_vadd(vbool4_t mask,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint64m1_t test___riscv_vadd(vbool64_t mask,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint64m2_t test___riscv_vadd(vbool32_t mask,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint64m4_t test___riscv_vadd(vbool16_t mask,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vint64m8_t test___riscv_vadd(vbool8_t mask,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vadd(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vadd(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vadd(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint8m1_t test___riscv_vadd(vbool8_t mask,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint8m2_t test___riscv_vadd(vbool4_t mask,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint8m4_t test___riscv_vadd(vbool2_t mask,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint8m8_t test___riscv_vadd(vbool1_t mask,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vadd(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vadd(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint16m1_t test___riscv_vadd(vbool16_t mask,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint16m2_t test___riscv_vadd(vbool8_t mask,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint16m4_t test___riscv_vadd(vbool4_t mask,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint16m8_t test___riscv_vadd(vbool2_t mask,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vadd(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint32m1_t test___riscv_vadd(vbool32_t mask,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint32m2_t test___riscv_vadd(vbool16_t mask,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint32m4_t test___riscv_vadd(vbool8_t mask,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint32m8_t test___riscv_vadd(vbool4_t mask,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint64m1_t test___riscv_vadd(vbool64_t mask,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint64m2_t test___riscv_vadd(vbool32_t mask,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint64m4_t test___riscv_vadd(vbool16_t mask,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + +vuint64m8_t test___riscv_vadd(vbool8_t mask,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv-3.C new file mode 100644 index 00000000000..845830f873a --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv-3.C @@ -0,0 +1,578 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd(vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint8mf4_t test___riscv_vadd(vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint8mf2_t test___riscv_vadd(vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint8m1_t test___riscv_vadd(vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint8m2_t test___riscv_vadd(vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint8m4_t test___riscv_vadd(vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint8m8_t test___riscv_vadd(vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint16mf4_t test___riscv_vadd(vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint16mf2_t test___riscv_vadd(vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint16m1_t test___riscv_vadd(vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint16m2_t test___riscv_vadd(vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint16m4_t test___riscv_vadd(vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint16m8_t test___riscv_vadd(vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint32mf2_t test___riscv_vadd(vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint32m1_t test___riscv_vadd(vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint32m2_t test___riscv_vadd(vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint32m4_t test___riscv_vadd(vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint32m8_t test___riscv_vadd(vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint64m1_t test___riscv_vadd(vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint64m2_t test___riscv_vadd(vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint64m4_t test___riscv_vadd(vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint64m8_t test___riscv_vadd(vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint8mf8_t test___riscv_vadd(vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint8mf4_t test___riscv_vadd(vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint8mf2_t test___riscv_vadd(vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint8m1_t test___riscv_vadd(vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint8m2_t test___riscv_vadd(vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint8m4_t test___riscv_vadd(vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint8m8_t test___riscv_vadd(vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint16mf4_t test___riscv_vadd(vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint16mf2_t test___riscv_vadd(vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint16m1_t test___riscv_vadd(vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint16m2_t test___riscv_vadd(vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint16m4_t test___riscv_vadd(vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint16m8_t test___riscv_vadd(vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint32mf2_t test___riscv_vadd(vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint32m1_t test___riscv_vadd(vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint32m2_t test___riscv_vadd(vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint32m4_t test___riscv_vadd(vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint32m8_t test___riscv_vadd(vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint64m1_t test___riscv_vadd(vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint64m2_t test___riscv_vadd(vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint64m4_t test___riscv_vadd(vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vuint64m8_t test___riscv_vadd(vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vadd(op1,op2,32); +} + + +vint8mf8_t test___riscv_vadd(vbool64_t mask,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint8mf4_t test___riscv_vadd(vbool32_t mask,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint8mf2_t test___riscv_vadd(vbool16_t mask,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint8m1_t test___riscv_vadd(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint8m2_t test___riscv_vadd(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint8m4_t test___riscv_vadd(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint8m8_t test___riscv_vadd(vbool1_t mask,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint16mf4_t test___riscv_vadd(vbool64_t mask,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint16mf2_t test___riscv_vadd(vbool32_t mask,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint16m1_t test___riscv_vadd(vbool16_t mask,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint16m2_t test___riscv_vadd(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint16m4_t test___riscv_vadd(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint16m8_t test___riscv_vadd(vbool2_t mask,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint32mf2_t test___riscv_vadd(vbool64_t mask,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint32m1_t test___riscv_vadd(vbool32_t mask,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint32m2_t test___riscv_vadd(vbool16_t mask,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint32m4_t test___riscv_vadd(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint32m8_t test___riscv_vadd(vbool4_t mask,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint64m1_t test___riscv_vadd(vbool64_t mask,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint64m2_t test___riscv_vadd(vbool32_t mask,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint64m4_t test___riscv_vadd(vbool16_t mask,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vint64m8_t test___riscv_vadd(vbool8_t mask,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vadd(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vadd(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vadd(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint8m1_t test___riscv_vadd(vbool8_t mask,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint8m2_t test___riscv_vadd(vbool4_t mask,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint8m4_t test___riscv_vadd(vbool2_t mask,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint8m8_t test___riscv_vadd(vbool1_t mask,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vadd(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vadd(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint16m1_t test___riscv_vadd(vbool16_t mask,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint16m2_t test___riscv_vadd(vbool8_t mask,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint16m4_t test___riscv_vadd(vbool4_t mask,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint16m8_t test___riscv_vadd(vbool2_t mask,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vadd(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint32m1_t test___riscv_vadd(vbool32_t mask,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint32m2_t test___riscv_vadd(vbool16_t mask,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint32m4_t test___riscv_vadd(vbool8_t mask,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint32m8_t test___riscv_vadd(vbool4_t mask,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint64m1_t test___riscv_vadd(vbool64_t mask,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint64m2_t test___riscv_vadd(vbool32_t mask,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint64m4_t test___riscv_vadd(vbool16_t mask,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + +vuint64m8_t test___riscv_vadd(vbool8_t mask,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vadd(mask,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv_mu-1.C new file mode 100644 index 00000000000..e45e4a58f50 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv_mu-1.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vadd_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vadd_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vadd_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vadd_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vadd_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vadd_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vadd_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vadd_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vadd_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vadd_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vadd_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vadd_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vadd_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vadd_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vadd_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vadd_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vadd_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vadd_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vadd_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vadd_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vadd_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vadd_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vadd_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vadd_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vadd_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vadd_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vadd_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vadd_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vadd_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vadd_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vadd_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vadd_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vadd_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vadd_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vadd_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vadd_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vadd_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vadd_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vadd_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vadd_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vadd_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vadd_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vadd_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv_mu-2.C new file mode 100644 index 00000000000..3f4c07f276a --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv_mu-2.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vadd_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vadd_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vadd_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vadd_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vadd_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vadd_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vadd_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vadd_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vadd_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vadd_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vadd_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vadd_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vadd_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vadd_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vadd_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vadd_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vadd_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vadd_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vadd_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vadd_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vadd_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vadd_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vadd_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vadd_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vadd_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vadd_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vadd_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vadd_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vadd_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vadd_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vadd_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vadd_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vadd_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vadd_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vadd_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vadd_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vadd_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vadd_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vadd_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vadd_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vadd_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vadd_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vadd_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv_mu-3.C new file mode 100644 index 00000000000..76fffe8884c --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv_mu-3.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vadd_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vadd_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vadd_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vadd_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vadd_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vadd_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vadd_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vadd_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vadd_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vadd_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vadd_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vadd_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vadd_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vadd_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vadd_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vadd_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vadd_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vadd_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vadd_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vadd_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vadd_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vadd_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vadd_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vadd_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vadd_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vadd_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vadd_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vadd_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vadd_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vadd_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vadd_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vadd_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vadd_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vadd_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vadd_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vadd_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vadd_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vadd_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vadd_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vadd_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vadd_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vadd_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vadd_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vadd_mu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv_tu-1.C new file mode 100644 index 00000000000..44f588b7949 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv_tu-1.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd_tu(vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vadd_tu(vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vadd_tu(vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vadd_tu(vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vadd_tu(vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vadd_tu(vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vadd_tu(vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vadd_tu(vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vadd_tu(vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vadd_tu(vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vadd_tu(vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vadd_tu(vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vadd_tu(vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vadd_tu(vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vadd_tu(vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vadd_tu(vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vadd_tu(vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vadd_tu(vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vadd_tu(vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vadd_tu(vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vadd_tu(vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vadd_tu(vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vadd_tu(vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vadd_tu(vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vadd_tu(vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vadd_tu(vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vadd_tu(vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vadd_tu(vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vadd_tu(vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vadd_tu(vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vadd_tu(vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vadd_tu(vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vadd_tu(vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vadd_tu(vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vadd_tu(vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vadd_tu(vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vadd_tu(vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vadd_tu(vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vadd_tu(vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vadd_tu(vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vadd_tu(vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vadd_tu(vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vadd_tu(vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vadd_tu(vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv_tu-2.C new file mode 100644 index 00000000000..f17abdd19e1 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv_tu-2.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd_tu(vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vadd_tu(vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vadd_tu(vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vadd_tu(vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vadd_tu(vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vadd_tu(vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vadd_tu(vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vadd_tu(vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vadd_tu(vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vadd_tu(vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vadd_tu(vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vadd_tu(vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vadd_tu(vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vadd_tu(vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vadd_tu(vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vadd_tu(vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vadd_tu(vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vadd_tu(vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vadd_tu(vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vadd_tu(vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vadd_tu(vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vadd_tu(vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vadd_tu(vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vadd_tu(vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vadd_tu(vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vadd_tu(vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vadd_tu(vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vadd_tu(vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vadd_tu(vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vadd_tu(vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vadd_tu(vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vadd_tu(vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vadd_tu(vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vadd_tu(vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vadd_tu(vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vadd_tu(vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vadd_tu(vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vadd_tu(vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vadd_tu(vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vadd_tu(vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vadd_tu(vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vadd_tu(vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vadd_tu(vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vadd_tu(vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv_tu-3.C new file mode 100644 index 00000000000..5829459efd8 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv_tu-3.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd_tu(vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vadd_tu(vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vadd_tu(vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vadd_tu(vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vadd_tu(vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vadd_tu(vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vadd_tu(vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vadd_tu(vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vadd_tu(vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vadd_tu(vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vadd_tu(vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vadd_tu(vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vadd_tu(vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vadd_tu(vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vadd_tu(vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vadd_tu(vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vadd_tu(vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vadd_tu(vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vadd_tu(vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vadd_tu(vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vadd_tu(vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vadd_tu(vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vadd_tu(vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vadd_tu(vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vadd_tu(vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vadd_tu(vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vadd_tu(vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vadd_tu(vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vadd_tu(vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vadd_tu(vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vadd_tu(vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vadd_tu(vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vadd_tu(vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vadd_tu(vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vadd_tu(vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vadd_tu(vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vadd_tu(vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vadd_tu(vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vadd_tu(vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vadd_tu(vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vadd_tu(vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vadd_tu(vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vadd_tu(vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vadd_tu(vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vadd_tu(merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv_tum-1.C new file mode 100644 index 00000000000..c2677284eba --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv_tum-1.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vadd_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vadd_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vadd_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vadd_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vadd_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vadd_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vadd_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vadd_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vadd_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vadd_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vadd_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vadd_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vadd_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vadd_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vadd_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vadd_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vadd_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vadd_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vadd_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vadd_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vadd_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vadd_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vadd_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vadd_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vadd_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vadd_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vadd_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vadd_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vadd_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vadd_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vadd_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vadd_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vadd_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vadd_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vadd_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vadd_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vadd_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vadd_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vadd_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vadd_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vadd_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vadd_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vadd_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv_tum-2.C new file mode 100644 index 00000000000..8a0c4450eb6 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv_tum-2.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vadd_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vadd_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vadd_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vadd_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vadd_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vadd_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vadd_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vadd_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vadd_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vadd_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vadd_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vadd_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vadd_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vadd_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vadd_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vadd_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vadd_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vadd_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vadd_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vadd_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vadd_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vadd_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vadd_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vadd_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vadd_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vadd_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vadd_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vadd_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vadd_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vadd_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vadd_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vadd_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vadd_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vadd_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vadd_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vadd_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vadd_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vadd_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vadd_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vadd_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vadd_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vadd_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vadd_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv_tum-3.C new file mode 100644 index 00000000000..b20997f28c8 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv_tum-3.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vadd_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vadd_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vadd_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vadd_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vadd_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vadd_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vadd_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vadd_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vadd_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vadd_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vadd_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vadd_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vadd_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vadd_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vadd_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vadd_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vadd_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vadd_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vadd_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vadd_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vadd_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vadd_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vadd_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vadd_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vadd_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vadd_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vadd_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vadd_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vadd_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vadd_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vadd_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vadd_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vadd_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vadd_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vadd_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vadd_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vadd_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vadd_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vadd_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vadd_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vadd_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vadd_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vadd_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vadd_tum(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv_tumu-1.C new file mode 100644 index 00000000000..87b5ea3dc90 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv_tumu-1.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint8mf4_t test___riscv_vadd_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint8mf2_t test___riscv_vadd_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint8m1_t test___riscv_vadd_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint8m2_t test___riscv_vadd_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint8m4_t test___riscv_vadd_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint8m8_t test___riscv_vadd_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint16mf4_t test___riscv_vadd_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vadd_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vadd_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vadd_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vadd_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vadd_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vadd_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vadd_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vadd_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vadd_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vadd_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vadd_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vadd_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vadd_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vadd_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vadd_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vadd_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vadd_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vadd_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vadd_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vadd_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vadd_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vadd_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vadd_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vadd_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vadd_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vadd_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vadd_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vadd_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vadd_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vadd_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vadd_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vadd_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vadd_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vadd_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vadd_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vadd_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv_tumu-2.C new file mode 100644 index 00000000000..49f25b25662 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv_tumu-2.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint8mf4_t test___riscv_vadd_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint8mf2_t test___riscv_vadd_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint8m1_t test___riscv_vadd_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint8m2_t test___riscv_vadd_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint8m4_t test___riscv_vadd_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint8m8_t test___riscv_vadd_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint16mf4_t test___riscv_vadd_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vadd_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vadd_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vadd_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vadd_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vadd_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vadd_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vadd_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vadd_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vadd_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vadd_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vadd_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vadd_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vadd_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vadd_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint8mf8_t test___riscv_vadd_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vadd_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vadd_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vadd_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vadd_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vadd_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vadd_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vadd_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vadd_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vadd_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vadd_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vadd_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vadd_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vadd_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vadd_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vadd_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vadd_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vadd_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vadd_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vadd_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vadd_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vadd_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv_tumu-3.C new file mode 100644 index 00000000000..10f312314d6 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadd_vv_tumu-3.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadd_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint8mf4_t test___riscv_vadd_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint8mf2_t test___riscv_vadd_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint8m1_t test___riscv_vadd_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint8m2_t test___riscv_vadd_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint8m4_t test___riscv_vadd_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint8m8_t test___riscv_vadd_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint16mf4_t test___riscv_vadd_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vadd_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vadd_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vadd_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vadd_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vadd_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vadd_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vadd_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vadd_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vadd_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vadd_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vadd_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vadd_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vadd_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vadd_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint8mf8_t test___riscv_vadd_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vadd_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vadd_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vadd_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vadd_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vadd_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vadd_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vadd_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vadd_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vadd_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vadd_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vadd_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vadd_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vadd_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vadd_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vadd_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vadd_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vadd_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vadd_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vadd_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vadd_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vadd_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vadd_tumu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ -- 2.36.3