From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtpbg150.qq.com (smtpbg150.qq.com [18.132.163.193]) by sourceware.org (Postfix) with ESMTPS id 425C73858D28 for ; Tue, 31 Jan 2023 12:58:39 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 425C73858D28 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp64t1675169902twpcgr8q Received: from rios-cad5.localdomain ( [58.60.1.11]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 31 Jan 2023 20:58:21 +0800 (CST) X-QQ-SSF: 01400000000000E0L000000A0000000 X-QQ-FEAT: q+yjhizk/eKKFjinOqIo5wzvONcyg3T6wyBhAkFyMXQCYygBV4+SfCrsIr0s5 BM94cOnu+BzK/HmlPalxITPSaWTEwfnZuyelXyd+EbTB2gNu/z0vPZJVJ4mBGH0gmUCJ6jU fc1txnMml/LCntTk/Y52iSXm1/nwzR905rlI391sKzjXemiKhpMGupAchBsx9xAxtE5wY3P FaVllu+e5bvjP7ElHPFMOv/hzDxP21BRKbcZo24RtInbxYyeQvfBUfye01Gcv/pscUhPgNw SEzhDDwqxSwGrM2+azmtgXKpASkFmspmcDEhEWr39rOu7tPTmGM7v/5Lujw6IK3rdfVh+h/ Nj571cjqYCvXhgFc5Ov7iOLYaiFvmNNC5rXrnr1mgkSG3iw7756qHsIXIfIe97JKCeFblpd X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, palmer@dabbelt.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: Add vsrl.vv C++ API tests Date: Tue, 31 Jan 2023 20:58:20 +0800 Message-Id: <20230131125820.319080-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Ju-Zhe Zhong gcc/testsuite/ChangeLog: * g++.target/riscv/rvv/base/vsrl_vv-1.C: New test. * g++.target/riscv/rvv/base/vsrl_vv-2.C: New test. * g++.target/riscv/rvv/base/vsrl_vv-3.C: New test. * g++.target/riscv/rvv/base/vsrl_vv_mu-1.C: New test. * g++.target/riscv/rvv/base/vsrl_vv_mu-2.C: New test. * g++.target/riscv/rvv/base/vsrl_vv_mu-3.C: New test. * g++.target/riscv/rvv/base/vsrl_vv_tu-1.C: New test. * g++.target/riscv/rvv/base/vsrl_vv_tu-2.C: New test. * g++.target/riscv/rvv/base/vsrl_vv_tu-3.C: New test. * g++.target/riscv/rvv/base/vsrl_vv_tum-1.C: New test. * g++.target/riscv/rvv/base/vsrl_vv_tum-2.C: New test. * g++.target/riscv/rvv/base/vsrl_vv_tum-3.C: New test. * g++.target/riscv/rvv/base/vsrl_vv_tumu-1.C: New test. * g++.target/riscv/rvv/base/vsrl_vv_tumu-2.C: New test. * g++.target/riscv/rvv/base/vsrl_vv_tumu-3.C: New test. --- .../g++.target/riscv/rvv/base/vsrl_vv-1.C | 314 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vsrl_vv-2.C | 314 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vsrl_vv-3.C | 314 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vsrl_vv_mu-1.C | 160 +++++++++ .../g++.target/riscv/rvv/base/vsrl_vv_mu-2.C | 160 +++++++++ .../g++.target/riscv/rvv/base/vsrl_vv_mu-3.C | 160 +++++++++ .../g++.target/riscv/rvv/base/vsrl_vv_tu-1.C | 160 +++++++++ .../g++.target/riscv/rvv/base/vsrl_vv_tu-2.C | 160 +++++++++ .../g++.target/riscv/rvv/base/vsrl_vv_tu-3.C | 160 +++++++++ .../g++.target/riscv/rvv/base/vsrl_vv_tum-1.C | 160 +++++++++ .../g++.target/riscv/rvv/base/vsrl_vv_tum-2.C | 160 +++++++++ .../g++.target/riscv/rvv/base/vsrl_vv_tum-3.C | 160 +++++++++ .../riscv/rvv/base/vsrl_vv_tumu-1.C | 160 +++++++++ .../riscv/rvv/base/vsrl_vv_tumu-2.C | 160 +++++++++ .../riscv/rvv/base/vsrl_vv_tumu-3.C | 160 +++++++++ 15 files changed, 2862 insertions(+) create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_tumu-3.C diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv-1.C new file mode 100644 index 00000000000..21b6f49eb75 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv-1.C @@ -0,0 +1,314 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vsrl(vuint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vsrl(vuint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vsrl(vuint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,vl); +} + + +vuint8m1_t test___riscv_vsrl(vuint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,vl); +} + + +vuint8m2_t test___riscv_vsrl(vuint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,vl); +} + + +vuint8m4_t test___riscv_vsrl(vuint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,vl); +} + + +vuint8m8_t test___riscv_vsrl(vuint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vsrl(vuint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vsrl(vuint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,vl); +} + + +vuint16m1_t test___riscv_vsrl(vuint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,vl); +} + + +vuint16m2_t test___riscv_vsrl(vuint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,vl); +} + + +vuint16m4_t test___riscv_vsrl(vuint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,vl); +} + + +vuint16m8_t test___riscv_vsrl(vuint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vsrl(vuint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,vl); +} + + +vuint32m1_t test___riscv_vsrl(vuint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,vl); +} + + +vuint32m2_t test___riscv_vsrl(vuint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,vl); +} + + +vuint32m4_t test___riscv_vsrl(vuint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,vl); +} + + +vuint32m8_t test___riscv_vsrl(vuint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,vl); +} + + +vuint64m1_t test___riscv_vsrl(vuint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,vl); +} + + +vuint64m2_t test___riscv_vsrl(vuint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,vl); +} + + +vuint64m4_t test___riscv_vsrl(vuint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,vl); +} + + +vuint64m8_t test___riscv_vsrl(vuint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,vl); +} + + +vuint8mf8_t test___riscv_vsrl(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vsrl(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vsrl(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,vl); +} + + +vuint8m1_t test___riscv_vsrl(vbool8_t mask,vuint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,vl); +} + + +vuint8m2_t test___riscv_vsrl(vbool4_t mask,vuint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,vl); +} + + +vuint8m4_t test___riscv_vsrl(vbool2_t mask,vuint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,vl); +} + + +vuint8m8_t test___riscv_vsrl(vbool1_t mask,vuint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vsrl(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vsrl(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,vl); +} + + +vuint16m1_t test___riscv_vsrl(vbool16_t mask,vuint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,vl); +} + + +vuint16m2_t test___riscv_vsrl(vbool8_t mask,vuint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,vl); +} + + +vuint16m4_t test___riscv_vsrl(vbool4_t mask,vuint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,vl); +} + + +vuint16m8_t test___riscv_vsrl(vbool2_t mask,vuint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vsrl(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,vl); +} + + +vuint32m1_t test___riscv_vsrl(vbool32_t mask,vuint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,vl); +} + + +vuint32m2_t test___riscv_vsrl(vbool16_t mask,vuint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,vl); +} + + +vuint32m4_t test___riscv_vsrl(vbool8_t mask,vuint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,vl); +} + + +vuint32m8_t test___riscv_vsrl(vbool4_t mask,vuint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,vl); +} + + +vuint64m1_t test___riscv_vsrl(vbool64_t mask,vuint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,vl); +} + + +vuint64m2_t test___riscv_vsrl(vbool32_t mask,vuint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,vl); +} + + +vuint64m4_t test___riscv_vsrl(vbool16_t mask,vuint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,vl); +} + + +vuint64m8_t test___riscv_vsrl(vbool8_t mask,vuint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv-2.C new file mode 100644 index 00000000000..ce57b6c9e1d --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv-2.C @@ -0,0 +1,314 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vsrl(vuint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,31); +} + + +vuint8mf4_t test___riscv_vsrl(vuint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,31); +} + + +vuint8mf2_t test___riscv_vsrl(vuint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,31); +} + + +vuint8m1_t test___riscv_vsrl(vuint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,31); +} + + +vuint8m2_t test___riscv_vsrl(vuint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,31); +} + + +vuint8m4_t test___riscv_vsrl(vuint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,31); +} + + +vuint8m8_t test___riscv_vsrl(vuint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,31); +} + + +vuint16mf4_t test___riscv_vsrl(vuint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,31); +} + + +vuint16mf2_t test___riscv_vsrl(vuint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,31); +} + + +vuint16m1_t test___riscv_vsrl(vuint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,31); +} + + +vuint16m2_t test___riscv_vsrl(vuint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,31); +} + + +vuint16m4_t test___riscv_vsrl(vuint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,31); +} + + +vuint16m8_t test___riscv_vsrl(vuint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,31); +} + + +vuint32mf2_t test___riscv_vsrl(vuint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,31); +} + + +vuint32m1_t test___riscv_vsrl(vuint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,31); +} + + +vuint32m2_t test___riscv_vsrl(vuint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,31); +} + + +vuint32m4_t test___riscv_vsrl(vuint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,31); +} + + +vuint32m8_t test___riscv_vsrl(vuint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,31); +} + + +vuint64m1_t test___riscv_vsrl(vuint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,31); +} + + +vuint64m2_t test___riscv_vsrl(vuint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,31); +} + + +vuint64m4_t test___riscv_vsrl(vuint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,31); +} + + +vuint64m8_t test___riscv_vsrl(vuint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,31); +} + + +vuint8mf8_t test___riscv_vsrl(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,31); +} + + +vuint8mf4_t test___riscv_vsrl(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,31); +} + + +vuint8mf2_t test___riscv_vsrl(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,31); +} + + +vuint8m1_t test___riscv_vsrl(vbool8_t mask,vuint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,31); +} + + +vuint8m2_t test___riscv_vsrl(vbool4_t mask,vuint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,31); +} + + +vuint8m4_t test___riscv_vsrl(vbool2_t mask,vuint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,31); +} + + +vuint8m8_t test___riscv_vsrl(vbool1_t mask,vuint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,31); +} + + +vuint16mf4_t test___riscv_vsrl(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,31); +} + + +vuint16mf2_t test___riscv_vsrl(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,31); +} + + +vuint16m1_t test___riscv_vsrl(vbool16_t mask,vuint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,31); +} + + +vuint16m2_t test___riscv_vsrl(vbool8_t mask,vuint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,31); +} + + +vuint16m4_t test___riscv_vsrl(vbool4_t mask,vuint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,31); +} + + +vuint16m8_t test___riscv_vsrl(vbool2_t mask,vuint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,31); +} + + +vuint32mf2_t test___riscv_vsrl(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,31); +} + + +vuint32m1_t test___riscv_vsrl(vbool32_t mask,vuint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,31); +} + + +vuint32m2_t test___riscv_vsrl(vbool16_t mask,vuint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,31); +} + + +vuint32m4_t test___riscv_vsrl(vbool8_t mask,vuint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,31); +} + + +vuint32m8_t test___riscv_vsrl(vbool4_t mask,vuint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,31); +} + + +vuint64m1_t test___riscv_vsrl(vbool64_t mask,vuint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,31); +} + + +vuint64m2_t test___riscv_vsrl(vbool32_t mask,vuint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,31); +} + + +vuint64m4_t test___riscv_vsrl(vbool16_t mask,vuint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,31); +} + + +vuint64m8_t test___riscv_vsrl(vbool8_t mask,vuint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv-3.C new file mode 100644 index 00000000000..c44b6f75e69 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv-3.C @@ -0,0 +1,314 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vsrl(vuint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,32); +} + + +vuint8mf4_t test___riscv_vsrl(vuint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,32); +} + + +vuint8mf2_t test___riscv_vsrl(vuint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,32); +} + + +vuint8m1_t test___riscv_vsrl(vuint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,32); +} + + +vuint8m2_t test___riscv_vsrl(vuint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,32); +} + + +vuint8m4_t test___riscv_vsrl(vuint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,32); +} + + +vuint8m8_t test___riscv_vsrl(vuint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,32); +} + + +vuint16mf4_t test___riscv_vsrl(vuint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,32); +} + + +vuint16mf2_t test___riscv_vsrl(vuint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,32); +} + + +vuint16m1_t test___riscv_vsrl(vuint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,32); +} + + +vuint16m2_t test___riscv_vsrl(vuint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,32); +} + + +vuint16m4_t test___riscv_vsrl(vuint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,32); +} + + +vuint16m8_t test___riscv_vsrl(vuint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,32); +} + + +vuint32mf2_t test___riscv_vsrl(vuint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,32); +} + + +vuint32m1_t test___riscv_vsrl(vuint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,32); +} + + +vuint32m2_t test___riscv_vsrl(vuint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,32); +} + + +vuint32m4_t test___riscv_vsrl(vuint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,32); +} + + +vuint32m8_t test___riscv_vsrl(vuint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,32); +} + + +vuint64m1_t test___riscv_vsrl(vuint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,32); +} + + +vuint64m2_t test___riscv_vsrl(vuint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,32); +} + + +vuint64m4_t test___riscv_vsrl(vuint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,32); +} + + +vuint64m8_t test___riscv_vsrl(vuint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vsrl(op1,shift,32); +} + + +vuint8mf8_t test___riscv_vsrl(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,32); +} + + +vuint8mf4_t test___riscv_vsrl(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,32); +} + + +vuint8mf2_t test___riscv_vsrl(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,32); +} + + +vuint8m1_t test___riscv_vsrl(vbool8_t mask,vuint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,32); +} + + +vuint8m2_t test___riscv_vsrl(vbool4_t mask,vuint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,32); +} + + +vuint8m4_t test___riscv_vsrl(vbool2_t mask,vuint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,32); +} + + +vuint8m8_t test___riscv_vsrl(vbool1_t mask,vuint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,32); +} + + +vuint16mf4_t test___riscv_vsrl(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,32); +} + + +vuint16mf2_t test___riscv_vsrl(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,32); +} + + +vuint16m1_t test___riscv_vsrl(vbool16_t mask,vuint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,32); +} + + +vuint16m2_t test___riscv_vsrl(vbool8_t mask,vuint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,32); +} + + +vuint16m4_t test___riscv_vsrl(vbool4_t mask,vuint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,32); +} + + +vuint16m8_t test___riscv_vsrl(vbool2_t mask,vuint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,32); +} + + +vuint32mf2_t test___riscv_vsrl(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,32); +} + + +vuint32m1_t test___riscv_vsrl(vbool32_t mask,vuint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,32); +} + + +vuint32m2_t test___riscv_vsrl(vbool16_t mask,vuint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,32); +} + + +vuint32m4_t test___riscv_vsrl(vbool8_t mask,vuint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,32); +} + + +vuint32m8_t test___riscv_vsrl(vbool4_t mask,vuint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,32); +} + + +vuint64m1_t test___riscv_vsrl(vbool64_t mask,vuint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,32); +} + + +vuint64m2_t test___riscv_vsrl(vbool32_t mask,vuint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,32); +} + + +vuint64m4_t test___riscv_vsrl(vbool16_t mask,vuint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,32); +} + + +vuint64m8_t test___riscv_vsrl(vbool8_t mask,vuint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vsrl(mask,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_mu-1.C new file mode 100644 index 00000000000..4ae0bfda046 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_mu-1.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vsrl_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vsrl_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vsrl_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,vl); +} + + +vuint8m1_t test___riscv_vsrl_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,vl); +} + + +vuint8m2_t test___riscv_vsrl_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,vl); +} + + +vuint8m4_t test___riscv_vsrl_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,vl); +} + + +vuint8m8_t test___riscv_vsrl_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vsrl_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vsrl_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,vl); +} + + +vuint16m1_t test___riscv_vsrl_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,vl); +} + + +vuint16m2_t test___riscv_vsrl_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,vl); +} + + +vuint16m4_t test___riscv_vsrl_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,vl); +} + + +vuint16m8_t test___riscv_vsrl_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vsrl_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,vl); +} + + +vuint32m1_t test___riscv_vsrl_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,vl); +} + + +vuint32m2_t test___riscv_vsrl_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,vl); +} + + +vuint32m4_t test___riscv_vsrl_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,vl); +} + + +vuint32m8_t test___riscv_vsrl_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,vl); +} + + +vuint64m1_t test___riscv_vsrl_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,vl); +} + + +vuint64m2_t test___riscv_vsrl_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,vl); +} + + +vuint64m4_t test___riscv_vsrl_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,vl); +} + + +vuint64m8_t test___riscv_vsrl_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_mu-2.C new file mode 100644 index 00000000000..6780575dee4 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_mu-2.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vsrl_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,31); +} + + +vuint8mf4_t test___riscv_vsrl_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,31); +} + + +vuint8mf2_t test___riscv_vsrl_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,31); +} + + +vuint8m1_t test___riscv_vsrl_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,31); +} + + +vuint8m2_t test___riscv_vsrl_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,31); +} + + +vuint8m4_t test___riscv_vsrl_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,31); +} + + +vuint8m8_t test___riscv_vsrl_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,31); +} + + +vuint16mf4_t test___riscv_vsrl_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,31); +} + + +vuint16mf2_t test___riscv_vsrl_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,31); +} + + +vuint16m1_t test___riscv_vsrl_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,31); +} + + +vuint16m2_t test___riscv_vsrl_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,31); +} + + +vuint16m4_t test___riscv_vsrl_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,31); +} + + +vuint16m8_t test___riscv_vsrl_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,31); +} + + +vuint32mf2_t test___riscv_vsrl_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,31); +} + + +vuint32m1_t test___riscv_vsrl_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,31); +} + + +vuint32m2_t test___riscv_vsrl_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,31); +} + + +vuint32m4_t test___riscv_vsrl_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,31); +} + + +vuint32m8_t test___riscv_vsrl_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,31); +} + + +vuint64m1_t test___riscv_vsrl_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,31); +} + + +vuint64m2_t test___riscv_vsrl_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,31); +} + + +vuint64m4_t test___riscv_vsrl_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,31); +} + + +vuint64m8_t test___riscv_vsrl_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_mu-3.C new file mode 100644 index 00000000000..8ba4c22d0a3 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_mu-3.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vsrl_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,32); +} + + +vuint8mf4_t test___riscv_vsrl_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,32); +} + + +vuint8mf2_t test___riscv_vsrl_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,32); +} + + +vuint8m1_t test___riscv_vsrl_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,32); +} + + +vuint8m2_t test___riscv_vsrl_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,32); +} + + +vuint8m4_t test___riscv_vsrl_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,32); +} + + +vuint8m8_t test___riscv_vsrl_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,32); +} + + +vuint16mf4_t test___riscv_vsrl_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,32); +} + + +vuint16mf2_t test___riscv_vsrl_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,32); +} + + +vuint16m1_t test___riscv_vsrl_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,32); +} + + +vuint16m2_t test___riscv_vsrl_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,32); +} + + +vuint16m4_t test___riscv_vsrl_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,32); +} + + +vuint16m8_t test___riscv_vsrl_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,32); +} + + +vuint32mf2_t test___riscv_vsrl_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,32); +} + + +vuint32m1_t test___riscv_vsrl_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,32); +} + + +vuint32m2_t test___riscv_vsrl_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,32); +} + + +vuint32m4_t test___riscv_vsrl_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,32); +} + + +vuint32m8_t test___riscv_vsrl_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,32); +} + + +vuint64m1_t test___riscv_vsrl_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,32); +} + + +vuint64m2_t test___riscv_vsrl_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,32); +} + + +vuint64m4_t test___riscv_vsrl_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,32); +} + + +vuint64m8_t test___riscv_vsrl_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vsrl_mu(mask,merge,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_tu-1.C new file mode 100644 index 00000000000..553965f9bf5 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_tu-1.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vsrl_tu(vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vsrl_tu(vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vsrl_tu(vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,vl); +} + + +vuint8m1_t test___riscv_vsrl_tu(vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,vl); +} + + +vuint8m2_t test___riscv_vsrl_tu(vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,vl); +} + + +vuint8m4_t test___riscv_vsrl_tu(vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,vl); +} + + +vuint8m8_t test___riscv_vsrl_tu(vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vsrl_tu(vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vsrl_tu(vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,vl); +} + + +vuint16m1_t test___riscv_vsrl_tu(vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,vl); +} + + +vuint16m2_t test___riscv_vsrl_tu(vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,vl); +} + + +vuint16m4_t test___riscv_vsrl_tu(vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,vl); +} + + +vuint16m8_t test___riscv_vsrl_tu(vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vsrl_tu(vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,vl); +} + + +vuint32m1_t test___riscv_vsrl_tu(vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,vl); +} + + +vuint32m2_t test___riscv_vsrl_tu(vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,vl); +} + + +vuint32m4_t test___riscv_vsrl_tu(vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,vl); +} + + +vuint32m8_t test___riscv_vsrl_tu(vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,vl); +} + + +vuint64m1_t test___riscv_vsrl_tu(vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,vl); +} + + +vuint64m2_t test___riscv_vsrl_tu(vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,vl); +} + + +vuint64m4_t test___riscv_vsrl_tu(vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,vl); +} + + +vuint64m8_t test___riscv_vsrl_tu(vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_tu-2.C new file mode 100644 index 00000000000..97a4acfd21d --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_tu-2.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vsrl_tu(vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,31); +} + + +vuint8mf4_t test___riscv_vsrl_tu(vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,31); +} + + +vuint8mf2_t test___riscv_vsrl_tu(vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,31); +} + + +vuint8m1_t test___riscv_vsrl_tu(vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,31); +} + + +vuint8m2_t test___riscv_vsrl_tu(vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,31); +} + + +vuint8m4_t test___riscv_vsrl_tu(vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,31); +} + + +vuint8m8_t test___riscv_vsrl_tu(vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,31); +} + + +vuint16mf4_t test___riscv_vsrl_tu(vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,31); +} + + +vuint16mf2_t test___riscv_vsrl_tu(vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,31); +} + + +vuint16m1_t test___riscv_vsrl_tu(vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,31); +} + + +vuint16m2_t test___riscv_vsrl_tu(vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,31); +} + + +vuint16m4_t test___riscv_vsrl_tu(vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,31); +} + + +vuint16m8_t test___riscv_vsrl_tu(vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,31); +} + + +vuint32mf2_t test___riscv_vsrl_tu(vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,31); +} + + +vuint32m1_t test___riscv_vsrl_tu(vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,31); +} + + +vuint32m2_t test___riscv_vsrl_tu(vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,31); +} + + +vuint32m4_t test___riscv_vsrl_tu(vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,31); +} + + +vuint32m8_t test___riscv_vsrl_tu(vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,31); +} + + +vuint64m1_t test___riscv_vsrl_tu(vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,31); +} + + +vuint64m2_t test___riscv_vsrl_tu(vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,31); +} + + +vuint64m4_t test___riscv_vsrl_tu(vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,31); +} + + +vuint64m8_t test___riscv_vsrl_tu(vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_tu-3.C new file mode 100644 index 00000000000..31c2f6f1530 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_tu-3.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vsrl_tu(vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,32); +} + + +vuint8mf4_t test___riscv_vsrl_tu(vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,32); +} + + +vuint8mf2_t test___riscv_vsrl_tu(vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,32); +} + + +vuint8m1_t test___riscv_vsrl_tu(vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,32); +} + + +vuint8m2_t test___riscv_vsrl_tu(vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,32); +} + + +vuint8m4_t test___riscv_vsrl_tu(vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,32); +} + + +vuint8m8_t test___riscv_vsrl_tu(vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,32); +} + + +vuint16mf4_t test___riscv_vsrl_tu(vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,32); +} + + +vuint16mf2_t test___riscv_vsrl_tu(vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,32); +} + + +vuint16m1_t test___riscv_vsrl_tu(vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,32); +} + + +vuint16m2_t test___riscv_vsrl_tu(vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,32); +} + + +vuint16m4_t test___riscv_vsrl_tu(vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,32); +} + + +vuint16m8_t test___riscv_vsrl_tu(vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,32); +} + + +vuint32mf2_t test___riscv_vsrl_tu(vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,32); +} + + +vuint32m1_t test___riscv_vsrl_tu(vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,32); +} + + +vuint32m2_t test___riscv_vsrl_tu(vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,32); +} + + +vuint32m4_t test___riscv_vsrl_tu(vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,32); +} + + +vuint32m8_t test___riscv_vsrl_tu(vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,32); +} + + +vuint64m1_t test___riscv_vsrl_tu(vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,32); +} + + +vuint64m2_t test___riscv_vsrl_tu(vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,32); +} + + +vuint64m4_t test___riscv_vsrl_tu(vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,32); +} + + +vuint64m8_t test___riscv_vsrl_tu(vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vsrl_tu(merge,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_tum-1.C new file mode 100644 index 00000000000..71732133e59 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_tum-1.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vsrl_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vsrl_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vsrl_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,vl); +} + + +vuint8m1_t test___riscv_vsrl_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,vl); +} + + +vuint8m2_t test___riscv_vsrl_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,vl); +} + + +vuint8m4_t test___riscv_vsrl_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,vl); +} + + +vuint8m8_t test___riscv_vsrl_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vsrl_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vsrl_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,vl); +} + + +vuint16m1_t test___riscv_vsrl_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,vl); +} + + +vuint16m2_t test___riscv_vsrl_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,vl); +} + + +vuint16m4_t test___riscv_vsrl_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,vl); +} + + +vuint16m8_t test___riscv_vsrl_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vsrl_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,vl); +} + + +vuint32m1_t test___riscv_vsrl_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,vl); +} + + +vuint32m2_t test___riscv_vsrl_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,vl); +} + + +vuint32m4_t test___riscv_vsrl_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,vl); +} + + +vuint32m8_t test___riscv_vsrl_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,vl); +} + + +vuint64m1_t test___riscv_vsrl_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,vl); +} + + +vuint64m2_t test___riscv_vsrl_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,vl); +} + + +vuint64m4_t test___riscv_vsrl_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,vl); +} + + +vuint64m8_t test___riscv_vsrl_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_tum-2.C new file mode 100644 index 00000000000..bb9e446ee3b --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_tum-2.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vsrl_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,31); +} + + +vuint8mf4_t test___riscv_vsrl_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,31); +} + + +vuint8mf2_t test___riscv_vsrl_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,31); +} + + +vuint8m1_t test___riscv_vsrl_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,31); +} + + +vuint8m2_t test___riscv_vsrl_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,31); +} + + +vuint8m4_t test___riscv_vsrl_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,31); +} + + +vuint8m8_t test___riscv_vsrl_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,31); +} + + +vuint16mf4_t test___riscv_vsrl_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,31); +} + + +vuint16mf2_t test___riscv_vsrl_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,31); +} + + +vuint16m1_t test___riscv_vsrl_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,31); +} + + +vuint16m2_t test___riscv_vsrl_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,31); +} + + +vuint16m4_t test___riscv_vsrl_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,31); +} + + +vuint16m8_t test___riscv_vsrl_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,31); +} + + +vuint32mf2_t test___riscv_vsrl_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,31); +} + + +vuint32m1_t test___riscv_vsrl_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,31); +} + + +vuint32m2_t test___riscv_vsrl_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,31); +} + + +vuint32m4_t test___riscv_vsrl_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,31); +} + + +vuint32m8_t test___riscv_vsrl_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,31); +} + + +vuint64m1_t test___riscv_vsrl_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,31); +} + + +vuint64m2_t test___riscv_vsrl_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,31); +} + + +vuint64m4_t test___riscv_vsrl_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,31); +} + + +vuint64m8_t test___riscv_vsrl_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_tum-3.C new file mode 100644 index 00000000000..3fdb30cc992 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_tum-3.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vsrl_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,32); +} + + +vuint8mf4_t test___riscv_vsrl_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,32); +} + + +vuint8mf2_t test___riscv_vsrl_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,32); +} + + +vuint8m1_t test___riscv_vsrl_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,32); +} + + +vuint8m2_t test___riscv_vsrl_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,32); +} + + +vuint8m4_t test___riscv_vsrl_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,32); +} + + +vuint8m8_t test___riscv_vsrl_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,32); +} + + +vuint16mf4_t test___riscv_vsrl_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,32); +} + + +vuint16mf2_t test___riscv_vsrl_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,32); +} + + +vuint16m1_t test___riscv_vsrl_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,32); +} + + +vuint16m2_t test___riscv_vsrl_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,32); +} + + +vuint16m4_t test___riscv_vsrl_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,32); +} + + +vuint16m8_t test___riscv_vsrl_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,32); +} + + +vuint32mf2_t test___riscv_vsrl_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,32); +} + + +vuint32m1_t test___riscv_vsrl_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,32); +} + + +vuint32m2_t test___riscv_vsrl_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,32); +} + + +vuint32m4_t test___riscv_vsrl_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,32); +} + + +vuint32m8_t test___riscv_vsrl_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,32); +} + + +vuint64m1_t test___riscv_vsrl_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,32); +} + + +vuint64m2_t test___riscv_vsrl_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,32); +} + + +vuint64m4_t test___riscv_vsrl_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,32); +} + + +vuint64m8_t test___riscv_vsrl_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vsrl_tum(mask,merge,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_tumu-1.C new file mode 100644 index 00000000000..0a807bae510 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_tumu-1.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vsrl_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vsrl_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vsrl_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint8m1_t test___riscv_vsrl_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint8m2_t test___riscv_vsrl_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint8m4_t test___riscv_vsrl_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint8m8_t test___riscv_vsrl_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vsrl_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vsrl_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint16m1_t test___riscv_vsrl_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint16m2_t test___riscv_vsrl_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint16m4_t test___riscv_vsrl_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint16m8_t test___riscv_vsrl_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vsrl_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint32m1_t test___riscv_vsrl_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint32m2_t test___riscv_vsrl_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint32m4_t test___riscv_vsrl_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint32m8_t test___riscv_vsrl_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint64m1_t test___riscv_vsrl_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint64m2_t test___riscv_vsrl_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint64m4_t test___riscv_vsrl_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,vl); +} + + +vuint64m8_t test___riscv_vsrl_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_tumu-2.C new file mode 100644 index 00000000000..cfb42441c9b --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_tumu-2.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vsrl_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,31); +} + + +vuint8mf4_t test___riscv_vsrl_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,31); +} + + +vuint8mf2_t test___riscv_vsrl_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,31); +} + + +vuint8m1_t test___riscv_vsrl_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,31); +} + + +vuint8m2_t test___riscv_vsrl_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,31); +} + + +vuint8m4_t test___riscv_vsrl_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,31); +} + + +vuint8m8_t test___riscv_vsrl_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,31); +} + + +vuint16mf4_t test___riscv_vsrl_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,31); +} + + +vuint16mf2_t test___riscv_vsrl_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,31); +} + + +vuint16m1_t test___riscv_vsrl_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,31); +} + + +vuint16m2_t test___riscv_vsrl_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,31); +} + + +vuint16m4_t test___riscv_vsrl_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,31); +} + + +vuint16m8_t test___riscv_vsrl_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,31); +} + + +vuint32mf2_t test___riscv_vsrl_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,31); +} + + +vuint32m1_t test___riscv_vsrl_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,31); +} + + +vuint32m2_t test___riscv_vsrl_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,31); +} + + +vuint32m4_t test___riscv_vsrl_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,31); +} + + +vuint32m8_t test___riscv_vsrl_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,31); +} + + +vuint64m1_t test___riscv_vsrl_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,31); +} + + +vuint64m2_t test___riscv_vsrl_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,31); +} + + +vuint64m4_t test___riscv_vsrl_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,31); +} + + +vuint64m8_t test___riscv_vsrl_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_tumu-3.C new file mode 100644 index 00000000000..a5333829151 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsrl_vv_tumu-3.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vsrl_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,32); +} + + +vuint8mf4_t test___riscv_vsrl_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,32); +} + + +vuint8mf2_t test___riscv_vsrl_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,32); +} + + +vuint8m1_t test___riscv_vsrl_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,32); +} + + +vuint8m2_t test___riscv_vsrl_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,32); +} + + +vuint8m4_t test___riscv_vsrl_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,32); +} + + +vuint8m8_t test___riscv_vsrl_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,32); +} + + +vuint16mf4_t test___riscv_vsrl_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,32); +} + + +vuint16mf2_t test___riscv_vsrl_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,32); +} + + +vuint16m1_t test___riscv_vsrl_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,32); +} + + +vuint16m2_t test___riscv_vsrl_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,32); +} + + +vuint16m4_t test___riscv_vsrl_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,32); +} + + +vuint16m8_t test___riscv_vsrl_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,32); +} + + +vuint32mf2_t test___riscv_vsrl_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,32); +} + + +vuint32m1_t test___riscv_vsrl_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,32); +} + + +vuint32m2_t test___riscv_vsrl_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,32); +} + + +vuint32m4_t test___riscv_vsrl_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,32); +} + + +vuint32m8_t test___riscv_vsrl_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,32); +} + + +vuint64m1_t test___riscv_vsrl_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,32); +} + + +vuint64m2_t test___riscv_vsrl_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,32); +} + + +vuint64m4_t test___riscv_vsrl_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,32); +} + + +vuint64m8_t test___riscv_vsrl_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t shift,size_t vl) +{ + return __riscv_vsrl_tumu(mask,merge,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vsrl\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ -- 2.36.3