From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtpbgeu2.qq.com (smtpbgeu2.qq.com [18.194.254.142]) by sourceware.org (Postfix) with ESMTPS id 31D763858D33 for ; Tue, 31 Jan 2023 22:10:05 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 31D763858D33 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp83t1675203001tki3w47h Received: from rios-cad5.localdomain ( [58.60.1.11]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 01 Feb 2023 06:10:00 +0800 (CST) X-QQ-SSF: 01400000000000E0L000000A0000000 X-QQ-FEAT: lkL5M32tl2AthxwGnnFcGJJaV422BjHb6O5c/35BLdpmwFIvVmhgWu3wk7lYV HeCM7asW3gHWH9h+4PB7nm6EFkOW0i0dTYd2hlvfUpvIockJRtmZD8w+EHCoKjPiXnsrotA cKGSkKz8OnvRnyPZoSoCaa7g0OpbDUnXvmatmeKmys02G7uQDuR3Xr8NtPp+l0/pRujaVB2 iVeXrZiqSofMkzGvrAPY7NSgz8hXJDXMZStyG/k7P9SRwP16+TU9wg2w3qxHEJRu1b2oXIT Jz9Uh0dluRu9UwRcSuqrDWV16wWoNwUveZjqRTf5AAZr5VSh6E2XDb3Ube/LykSJ9ru4Pf3 ix8OYekhbEwXF2/YS0onhTrVOgE+D8M0i2DivG1ZS5h9I8ZoEU= X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: Add vsrl.vx C API tests Date: Wed, 1 Feb 2023 06:09:58 +0800 Message-Id: <20230131220958.20394-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-12.8 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,KAM_SHORT,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_PASS,TXREP,T_SPF_HELO_TEMPERROR autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Ju-Zhe Zhong gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/vsrl_vx-1.c: New test. * gcc.target/riscv/rvv/base/vsrl_vx-2.c: New test. * gcc.target/riscv/rvv/base/vsrl_vx-3.c: New test. * gcc.target/riscv/rvv/base/vsrl_vx_m-1.c: New test. * gcc.target/riscv/rvv/base/vsrl_vx_m-2.c: New test. * gcc.target/riscv/rvv/base/vsrl_vx_m-3.c: New test. * gcc.target/riscv/rvv/base/vsrl_vx_mu-1.c: New test. * gcc.target/riscv/rvv/base/vsrl_vx_mu-2.c: New test. * gcc.target/riscv/rvv/base/vsrl_vx_mu-3.c: New test. * gcc.target/riscv/rvv/base/vsrl_vx_tu-1.c: New test. * gcc.target/riscv/rvv/base/vsrl_vx_tu-2.c: New test. * gcc.target/riscv/rvv/base/vsrl_vx_tu-3.c: New test. * gcc.target/riscv/rvv/base/vsrl_vx_tum-1.c: New test. * gcc.target/riscv/rvv/base/vsrl_vx_tum-2.c: New test. * gcc.target/riscv/rvv/base/vsrl_vx_tum-3.c: New test. * gcc.target/riscv/rvv/base/vsrl_vx_tumu-1.c: New test. * gcc.target/riscv/rvv/base/vsrl_vx_tumu-2.c: New test. * gcc.target/riscv/rvv/base/vsrl_vx_tumu-3.c: New test. --- .../gcc.target/riscv/rvv/base/vsrl_vx-1.c | 160 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vsrl_vx-2.c | 160 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vsrl_vx-3.c | 160 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vsrl_vx_m-1.c | 160 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vsrl_vx_m-2.c | 160 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vsrl_vx_m-3.c | 160 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vsrl_vx_mu-1.c | 160 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vsrl_vx_mu-2.c | 160 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vsrl_vx_mu-3.c | 160 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vsrl_vx_tu-1.c | 160 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vsrl_vx_tu-2.c | 160 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vsrl_vx_tu-3.c | 160 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vsrl_vx_tum-1.c | 160 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vsrl_vx_tum-2.c | 160 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vsrl_vx_tum-3.c | 160 ++++++++++++++++++ .../riscv/rvv/base/vsrl_vx_tumu-1.c | 160 ++++++++++++++++++ .../riscv/rvv/base/vsrl_vx_tumu-2.c | 160 ++++++++++++++++++ .../riscv/rvv/base/vsrl_vx_tumu-3.c | 160 ++++++++++++++++++ 18 files changed, 2880 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_tumu-3.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx-1.c new file mode 100644 index 00000000000..284289a59f4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx-1.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vsrl_vx_u8mf8(vuint8mf8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8mf8(op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vsrl_vx_u8mf4(vuint8mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8mf4(op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vsrl_vx_u8mf2(vuint8mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8mf2(op1,shift,vl); +} + + +vuint8m1_t test___riscv_vsrl_vx_u8m1(vuint8m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8m1(op1,shift,vl); +} + + +vuint8m2_t test___riscv_vsrl_vx_u8m2(vuint8m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8m2(op1,shift,vl); +} + + +vuint8m4_t test___riscv_vsrl_vx_u8m4(vuint8m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8m4(op1,shift,vl); +} + + +vuint8m8_t test___riscv_vsrl_vx_u8m8(vuint8m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8m8(op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vsrl_vx_u16mf4(vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16mf4(op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vsrl_vx_u16mf2(vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16mf2(op1,shift,vl); +} + + +vuint16m1_t test___riscv_vsrl_vx_u16m1(vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16m1(op1,shift,vl); +} + + +vuint16m2_t test___riscv_vsrl_vx_u16m2(vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16m2(op1,shift,vl); +} + + +vuint16m4_t test___riscv_vsrl_vx_u16m4(vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16m4(op1,shift,vl); +} + + +vuint16m8_t test___riscv_vsrl_vx_u16m8(vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16m8(op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vsrl_vx_u32mf2(vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32mf2(op1,shift,vl); +} + + +vuint32m1_t test___riscv_vsrl_vx_u32m1(vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32m1(op1,shift,vl); +} + + +vuint32m2_t test___riscv_vsrl_vx_u32m2(vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32m2(op1,shift,vl); +} + + +vuint32m4_t test___riscv_vsrl_vx_u32m4(vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32m4(op1,shift,vl); +} + + +vuint32m8_t test___riscv_vsrl_vx_u32m8(vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32m8(op1,shift,vl); +} + + +vuint64m1_t test___riscv_vsrl_vx_u64m1(vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u64m1(op1,shift,vl); +} + + +vuint64m2_t test___riscv_vsrl_vx_u64m2(vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u64m2(op1,shift,vl); +} + + +vuint64m4_t test___riscv_vsrl_vx_u64m4(vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u64m4(op1,shift,vl); +} + + +vuint64m8_t test___riscv_vsrl_vx_u64m8(vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u64m8(op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx-2.c new file mode 100644 index 00000000000..3123fe953ec --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx-2.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vsrl_vx_u8mf8(vuint8mf8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8mf8(op1,shift,31); +} + + +vuint8mf4_t test___riscv_vsrl_vx_u8mf4(vuint8mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8mf4(op1,shift,31); +} + + +vuint8mf2_t test___riscv_vsrl_vx_u8mf2(vuint8mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8mf2(op1,shift,31); +} + + +vuint8m1_t test___riscv_vsrl_vx_u8m1(vuint8m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8m1(op1,shift,31); +} + + +vuint8m2_t test___riscv_vsrl_vx_u8m2(vuint8m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8m2(op1,shift,31); +} + + +vuint8m4_t test___riscv_vsrl_vx_u8m4(vuint8m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8m4(op1,shift,31); +} + + +vuint8m8_t test___riscv_vsrl_vx_u8m8(vuint8m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8m8(op1,shift,31); +} + + +vuint16mf4_t test___riscv_vsrl_vx_u16mf4(vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16mf4(op1,shift,31); +} + + +vuint16mf2_t test___riscv_vsrl_vx_u16mf2(vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16mf2(op1,shift,31); +} + + +vuint16m1_t test___riscv_vsrl_vx_u16m1(vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16m1(op1,shift,31); +} + + +vuint16m2_t test___riscv_vsrl_vx_u16m2(vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16m2(op1,shift,31); +} + + +vuint16m4_t test___riscv_vsrl_vx_u16m4(vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16m4(op1,shift,31); +} + + +vuint16m8_t test___riscv_vsrl_vx_u16m8(vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16m8(op1,shift,31); +} + + +vuint32mf2_t test___riscv_vsrl_vx_u32mf2(vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32mf2(op1,shift,31); +} + + +vuint32m1_t test___riscv_vsrl_vx_u32m1(vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32m1(op1,shift,31); +} + + +vuint32m2_t test___riscv_vsrl_vx_u32m2(vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32m2(op1,shift,31); +} + + +vuint32m4_t test___riscv_vsrl_vx_u32m4(vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32m4(op1,shift,31); +} + + +vuint32m8_t test___riscv_vsrl_vx_u32m8(vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32m8(op1,shift,31); +} + + +vuint64m1_t test___riscv_vsrl_vx_u64m1(vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u64m1(op1,shift,31); +} + + +vuint64m2_t test___riscv_vsrl_vx_u64m2(vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u64m2(op1,shift,31); +} + + +vuint64m4_t test___riscv_vsrl_vx_u64m4(vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u64m4(op1,shift,31); +} + + +vuint64m8_t test___riscv_vsrl_vx_u64m8(vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u64m8(op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx-3.c new file mode 100644 index 00000000000..bfba6c4d501 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx-3.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vsrl_vx_u8mf8(vuint8mf8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8mf8(op1,shift,32); +} + + +vuint8mf4_t test___riscv_vsrl_vx_u8mf4(vuint8mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8mf4(op1,shift,32); +} + + +vuint8mf2_t test___riscv_vsrl_vx_u8mf2(vuint8mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8mf2(op1,shift,32); +} + + +vuint8m1_t test___riscv_vsrl_vx_u8m1(vuint8m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8m1(op1,shift,32); +} + + +vuint8m2_t test___riscv_vsrl_vx_u8m2(vuint8m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8m2(op1,shift,32); +} + + +vuint8m4_t test___riscv_vsrl_vx_u8m4(vuint8m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8m4(op1,shift,32); +} + + +vuint8m8_t test___riscv_vsrl_vx_u8m8(vuint8m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8m8(op1,shift,32); +} + + +vuint16mf4_t test___riscv_vsrl_vx_u16mf4(vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16mf4(op1,shift,32); +} + + +vuint16mf2_t test___riscv_vsrl_vx_u16mf2(vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16mf2(op1,shift,32); +} + + +vuint16m1_t test___riscv_vsrl_vx_u16m1(vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16m1(op1,shift,32); +} + + +vuint16m2_t test___riscv_vsrl_vx_u16m2(vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16m2(op1,shift,32); +} + + +vuint16m4_t test___riscv_vsrl_vx_u16m4(vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16m4(op1,shift,32); +} + + +vuint16m8_t test___riscv_vsrl_vx_u16m8(vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16m8(op1,shift,32); +} + + +vuint32mf2_t test___riscv_vsrl_vx_u32mf2(vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32mf2(op1,shift,32); +} + + +vuint32m1_t test___riscv_vsrl_vx_u32m1(vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32m1(op1,shift,32); +} + + +vuint32m2_t test___riscv_vsrl_vx_u32m2(vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32m2(op1,shift,32); +} + + +vuint32m4_t test___riscv_vsrl_vx_u32m4(vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32m4(op1,shift,32); +} + + +vuint32m8_t test___riscv_vsrl_vx_u32m8(vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32m8(op1,shift,32); +} + + +vuint64m1_t test___riscv_vsrl_vx_u64m1(vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u64m1(op1,shift,32); +} + + +vuint64m2_t test___riscv_vsrl_vx_u64m2(vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u64m2(op1,shift,32); +} + + +vuint64m4_t test___riscv_vsrl_vx_u64m4(vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u64m4(op1,shift,32); +} + + +vuint64m8_t test___riscv_vsrl_vx_u64m8(vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u64m8(op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_m-1.c new file mode 100644 index 00000000000..3a9e57c13e3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_m-1.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vsrl_vx_u8mf8_m(vbool64_t mask,vuint8mf8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8mf8_m(mask,op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vsrl_vx_u8mf4_m(vbool32_t mask,vuint8mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8mf4_m(mask,op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vsrl_vx_u8mf2_m(vbool16_t mask,vuint8mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8mf2_m(mask,op1,shift,vl); +} + + +vuint8m1_t test___riscv_vsrl_vx_u8m1_m(vbool8_t mask,vuint8m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8m1_m(mask,op1,shift,vl); +} + + +vuint8m2_t test___riscv_vsrl_vx_u8m2_m(vbool4_t mask,vuint8m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8m2_m(mask,op1,shift,vl); +} + + +vuint8m4_t test___riscv_vsrl_vx_u8m4_m(vbool2_t mask,vuint8m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8m4_m(mask,op1,shift,vl); +} + + +vuint8m8_t test___riscv_vsrl_vx_u8m8_m(vbool1_t mask,vuint8m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8m8_m(mask,op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vsrl_vx_u16mf4_m(vbool64_t mask,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16mf4_m(mask,op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vsrl_vx_u16mf2_m(vbool32_t mask,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16mf2_m(mask,op1,shift,vl); +} + + +vuint16m1_t test___riscv_vsrl_vx_u16m1_m(vbool16_t mask,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16m1_m(mask,op1,shift,vl); +} + + +vuint16m2_t test___riscv_vsrl_vx_u16m2_m(vbool8_t mask,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16m2_m(mask,op1,shift,vl); +} + + +vuint16m4_t test___riscv_vsrl_vx_u16m4_m(vbool4_t mask,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16m4_m(mask,op1,shift,vl); +} + + +vuint16m8_t test___riscv_vsrl_vx_u16m8_m(vbool2_t mask,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16m8_m(mask,op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vsrl_vx_u32mf2_m(vbool64_t mask,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32mf2_m(mask,op1,shift,vl); +} + + +vuint32m1_t test___riscv_vsrl_vx_u32m1_m(vbool32_t mask,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32m1_m(mask,op1,shift,vl); +} + + +vuint32m2_t test___riscv_vsrl_vx_u32m2_m(vbool16_t mask,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32m2_m(mask,op1,shift,vl); +} + + +vuint32m4_t test___riscv_vsrl_vx_u32m4_m(vbool8_t mask,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32m4_m(mask,op1,shift,vl); +} + + +vuint32m8_t test___riscv_vsrl_vx_u32m8_m(vbool4_t mask,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32m8_m(mask,op1,shift,vl); +} + + +vuint64m1_t test___riscv_vsrl_vx_u64m1_m(vbool64_t mask,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u64m1_m(mask,op1,shift,vl); +} + + +vuint64m2_t test___riscv_vsrl_vx_u64m2_m(vbool32_t mask,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u64m2_m(mask,op1,shift,vl); +} + + +vuint64m4_t test___riscv_vsrl_vx_u64m4_m(vbool16_t mask,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u64m4_m(mask,op1,shift,vl); +} + + +vuint64m8_t test___riscv_vsrl_vx_u64m8_m(vbool8_t mask,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u64m8_m(mask,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_m-2.c new file mode 100644 index 00000000000..cb0e7796d21 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_m-2.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vsrl_vx_u8mf8_m(vbool64_t mask,vuint8mf8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8mf8_m(mask,op1,shift,31); +} + + +vuint8mf4_t test___riscv_vsrl_vx_u8mf4_m(vbool32_t mask,vuint8mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8mf4_m(mask,op1,shift,31); +} + + +vuint8mf2_t test___riscv_vsrl_vx_u8mf2_m(vbool16_t mask,vuint8mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8mf2_m(mask,op1,shift,31); +} + + +vuint8m1_t test___riscv_vsrl_vx_u8m1_m(vbool8_t mask,vuint8m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8m1_m(mask,op1,shift,31); +} + + +vuint8m2_t test___riscv_vsrl_vx_u8m2_m(vbool4_t mask,vuint8m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8m2_m(mask,op1,shift,31); +} + + +vuint8m4_t test___riscv_vsrl_vx_u8m4_m(vbool2_t mask,vuint8m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8m4_m(mask,op1,shift,31); +} + + +vuint8m8_t test___riscv_vsrl_vx_u8m8_m(vbool1_t mask,vuint8m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8m8_m(mask,op1,shift,31); +} + + +vuint16mf4_t test___riscv_vsrl_vx_u16mf4_m(vbool64_t mask,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16mf4_m(mask,op1,shift,31); +} + + +vuint16mf2_t test___riscv_vsrl_vx_u16mf2_m(vbool32_t mask,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16mf2_m(mask,op1,shift,31); +} + + +vuint16m1_t test___riscv_vsrl_vx_u16m1_m(vbool16_t mask,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16m1_m(mask,op1,shift,31); +} + + +vuint16m2_t test___riscv_vsrl_vx_u16m2_m(vbool8_t mask,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16m2_m(mask,op1,shift,31); +} + + +vuint16m4_t test___riscv_vsrl_vx_u16m4_m(vbool4_t mask,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16m4_m(mask,op1,shift,31); +} + + +vuint16m8_t test___riscv_vsrl_vx_u16m8_m(vbool2_t mask,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16m8_m(mask,op1,shift,31); +} + + +vuint32mf2_t test___riscv_vsrl_vx_u32mf2_m(vbool64_t mask,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32mf2_m(mask,op1,shift,31); +} + + +vuint32m1_t test___riscv_vsrl_vx_u32m1_m(vbool32_t mask,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32m1_m(mask,op1,shift,31); +} + + +vuint32m2_t test___riscv_vsrl_vx_u32m2_m(vbool16_t mask,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32m2_m(mask,op1,shift,31); +} + + +vuint32m4_t test___riscv_vsrl_vx_u32m4_m(vbool8_t mask,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32m4_m(mask,op1,shift,31); +} + + +vuint32m8_t test___riscv_vsrl_vx_u32m8_m(vbool4_t mask,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32m8_m(mask,op1,shift,31); +} + + +vuint64m1_t test___riscv_vsrl_vx_u64m1_m(vbool64_t mask,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u64m1_m(mask,op1,shift,31); +} + + +vuint64m2_t test___riscv_vsrl_vx_u64m2_m(vbool32_t mask,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u64m2_m(mask,op1,shift,31); +} + + +vuint64m4_t test___riscv_vsrl_vx_u64m4_m(vbool16_t mask,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u64m4_m(mask,op1,shift,31); +} + + +vuint64m8_t test___riscv_vsrl_vx_u64m8_m(vbool8_t mask,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u64m8_m(mask,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_m-3.c new file mode 100644 index 00000000000..492e0681692 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_m-3.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vsrl_vx_u8mf8_m(vbool64_t mask,vuint8mf8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8mf8_m(mask,op1,shift,32); +} + + +vuint8mf4_t test___riscv_vsrl_vx_u8mf4_m(vbool32_t mask,vuint8mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8mf4_m(mask,op1,shift,32); +} + + +vuint8mf2_t test___riscv_vsrl_vx_u8mf2_m(vbool16_t mask,vuint8mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8mf2_m(mask,op1,shift,32); +} + + +vuint8m1_t test___riscv_vsrl_vx_u8m1_m(vbool8_t mask,vuint8m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8m1_m(mask,op1,shift,32); +} + + +vuint8m2_t test___riscv_vsrl_vx_u8m2_m(vbool4_t mask,vuint8m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8m2_m(mask,op1,shift,32); +} + + +vuint8m4_t test___riscv_vsrl_vx_u8m4_m(vbool2_t mask,vuint8m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8m4_m(mask,op1,shift,32); +} + + +vuint8m8_t test___riscv_vsrl_vx_u8m8_m(vbool1_t mask,vuint8m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8m8_m(mask,op1,shift,32); +} + + +vuint16mf4_t test___riscv_vsrl_vx_u16mf4_m(vbool64_t mask,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16mf4_m(mask,op1,shift,32); +} + + +vuint16mf2_t test___riscv_vsrl_vx_u16mf2_m(vbool32_t mask,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16mf2_m(mask,op1,shift,32); +} + + +vuint16m1_t test___riscv_vsrl_vx_u16m1_m(vbool16_t mask,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16m1_m(mask,op1,shift,32); +} + + +vuint16m2_t test___riscv_vsrl_vx_u16m2_m(vbool8_t mask,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16m2_m(mask,op1,shift,32); +} + + +vuint16m4_t test___riscv_vsrl_vx_u16m4_m(vbool4_t mask,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16m4_m(mask,op1,shift,32); +} + + +vuint16m8_t test___riscv_vsrl_vx_u16m8_m(vbool2_t mask,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16m8_m(mask,op1,shift,32); +} + + +vuint32mf2_t test___riscv_vsrl_vx_u32mf2_m(vbool64_t mask,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32mf2_m(mask,op1,shift,32); +} + + +vuint32m1_t test___riscv_vsrl_vx_u32m1_m(vbool32_t mask,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32m1_m(mask,op1,shift,32); +} + + +vuint32m2_t test___riscv_vsrl_vx_u32m2_m(vbool16_t mask,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32m2_m(mask,op1,shift,32); +} + + +vuint32m4_t test___riscv_vsrl_vx_u32m4_m(vbool8_t mask,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32m4_m(mask,op1,shift,32); +} + + +vuint32m8_t test___riscv_vsrl_vx_u32m8_m(vbool4_t mask,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32m8_m(mask,op1,shift,32); +} + + +vuint64m1_t test___riscv_vsrl_vx_u64m1_m(vbool64_t mask,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u64m1_m(mask,op1,shift,32); +} + + +vuint64m2_t test___riscv_vsrl_vx_u64m2_m(vbool32_t mask,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u64m2_m(mask,op1,shift,32); +} + + +vuint64m4_t test___riscv_vsrl_vx_u64m4_m(vbool16_t mask,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u64m4_m(mask,op1,shift,32); +} + + +vuint64m8_t test___riscv_vsrl_vx_u64m8_m(vbool8_t mask,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u64m8_m(mask,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_mu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_mu-1.c new file mode 100644 index 00000000000..77e898616bb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_mu-1.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vsrl_vx_u8mf8_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8mf8_mu(mask,merge,op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vsrl_vx_u8mf4_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8mf4_mu(mask,merge,op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vsrl_vx_u8mf2_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8mf2_mu(mask,merge,op1,shift,vl); +} + + +vuint8m1_t test___riscv_vsrl_vx_u8m1_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8m1_mu(mask,merge,op1,shift,vl); +} + + +vuint8m2_t test___riscv_vsrl_vx_u8m2_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8m2_mu(mask,merge,op1,shift,vl); +} + + +vuint8m4_t test___riscv_vsrl_vx_u8m4_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8m4_mu(mask,merge,op1,shift,vl); +} + + +vuint8m8_t test___riscv_vsrl_vx_u8m8_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8m8_mu(mask,merge,op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vsrl_vx_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16mf4_mu(mask,merge,op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vsrl_vx_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16mf2_mu(mask,merge,op1,shift,vl); +} + + +vuint16m1_t test___riscv_vsrl_vx_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16m1_mu(mask,merge,op1,shift,vl); +} + + +vuint16m2_t test___riscv_vsrl_vx_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16m2_mu(mask,merge,op1,shift,vl); +} + + +vuint16m4_t test___riscv_vsrl_vx_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16m4_mu(mask,merge,op1,shift,vl); +} + + +vuint16m8_t test___riscv_vsrl_vx_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16m8_mu(mask,merge,op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vsrl_vx_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32mf2_mu(mask,merge,op1,shift,vl); +} + + +vuint32m1_t test___riscv_vsrl_vx_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32m1_mu(mask,merge,op1,shift,vl); +} + + +vuint32m2_t test___riscv_vsrl_vx_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32m2_mu(mask,merge,op1,shift,vl); +} + + +vuint32m4_t test___riscv_vsrl_vx_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32m4_mu(mask,merge,op1,shift,vl); +} + + +vuint32m8_t test___riscv_vsrl_vx_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32m8_mu(mask,merge,op1,shift,vl); +} + + +vuint64m1_t test___riscv_vsrl_vx_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u64m1_mu(mask,merge,op1,shift,vl); +} + + +vuint64m2_t test___riscv_vsrl_vx_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u64m2_mu(mask,merge,op1,shift,vl); +} + + +vuint64m4_t test___riscv_vsrl_vx_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u64m4_mu(mask,merge,op1,shift,vl); +} + + +vuint64m8_t test___riscv_vsrl_vx_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u64m8_mu(mask,merge,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_mu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_mu-2.c new file mode 100644 index 00000000000..4d300fb1c78 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_mu-2.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vsrl_vx_u8mf8_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8mf8_mu(mask,merge,op1,shift,31); +} + + +vuint8mf4_t test___riscv_vsrl_vx_u8mf4_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8mf4_mu(mask,merge,op1,shift,31); +} + + +vuint8mf2_t test___riscv_vsrl_vx_u8mf2_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8mf2_mu(mask,merge,op1,shift,31); +} + + +vuint8m1_t test___riscv_vsrl_vx_u8m1_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8m1_mu(mask,merge,op1,shift,31); +} + + +vuint8m2_t test___riscv_vsrl_vx_u8m2_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8m2_mu(mask,merge,op1,shift,31); +} + + +vuint8m4_t test___riscv_vsrl_vx_u8m4_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8m4_mu(mask,merge,op1,shift,31); +} + + +vuint8m8_t test___riscv_vsrl_vx_u8m8_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8m8_mu(mask,merge,op1,shift,31); +} + + +vuint16mf4_t test___riscv_vsrl_vx_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16mf4_mu(mask,merge,op1,shift,31); +} + + +vuint16mf2_t test___riscv_vsrl_vx_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16mf2_mu(mask,merge,op1,shift,31); +} + + +vuint16m1_t test___riscv_vsrl_vx_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16m1_mu(mask,merge,op1,shift,31); +} + + +vuint16m2_t test___riscv_vsrl_vx_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16m2_mu(mask,merge,op1,shift,31); +} + + +vuint16m4_t test___riscv_vsrl_vx_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16m4_mu(mask,merge,op1,shift,31); +} + + +vuint16m8_t test___riscv_vsrl_vx_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16m8_mu(mask,merge,op1,shift,31); +} + + +vuint32mf2_t test___riscv_vsrl_vx_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32mf2_mu(mask,merge,op1,shift,31); +} + + +vuint32m1_t test___riscv_vsrl_vx_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32m1_mu(mask,merge,op1,shift,31); +} + + +vuint32m2_t test___riscv_vsrl_vx_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32m2_mu(mask,merge,op1,shift,31); +} + + +vuint32m4_t test___riscv_vsrl_vx_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32m4_mu(mask,merge,op1,shift,31); +} + + +vuint32m8_t test___riscv_vsrl_vx_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32m8_mu(mask,merge,op1,shift,31); +} + + +vuint64m1_t test___riscv_vsrl_vx_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u64m1_mu(mask,merge,op1,shift,31); +} + + +vuint64m2_t test___riscv_vsrl_vx_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u64m2_mu(mask,merge,op1,shift,31); +} + + +vuint64m4_t test___riscv_vsrl_vx_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u64m4_mu(mask,merge,op1,shift,31); +} + + +vuint64m8_t test___riscv_vsrl_vx_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u64m8_mu(mask,merge,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_mu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_mu-3.c new file mode 100644 index 00000000000..410de104f99 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_mu-3.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vsrl_vx_u8mf8_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8mf8_mu(mask,merge,op1,shift,32); +} + + +vuint8mf4_t test___riscv_vsrl_vx_u8mf4_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8mf4_mu(mask,merge,op1,shift,32); +} + + +vuint8mf2_t test___riscv_vsrl_vx_u8mf2_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8mf2_mu(mask,merge,op1,shift,32); +} + + +vuint8m1_t test___riscv_vsrl_vx_u8m1_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8m1_mu(mask,merge,op1,shift,32); +} + + +vuint8m2_t test___riscv_vsrl_vx_u8m2_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8m2_mu(mask,merge,op1,shift,32); +} + + +vuint8m4_t test___riscv_vsrl_vx_u8m4_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8m4_mu(mask,merge,op1,shift,32); +} + + +vuint8m8_t test___riscv_vsrl_vx_u8m8_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8m8_mu(mask,merge,op1,shift,32); +} + + +vuint16mf4_t test___riscv_vsrl_vx_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16mf4_mu(mask,merge,op1,shift,32); +} + + +vuint16mf2_t test___riscv_vsrl_vx_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16mf2_mu(mask,merge,op1,shift,32); +} + + +vuint16m1_t test___riscv_vsrl_vx_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16m1_mu(mask,merge,op1,shift,32); +} + + +vuint16m2_t test___riscv_vsrl_vx_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16m2_mu(mask,merge,op1,shift,32); +} + + +vuint16m4_t test___riscv_vsrl_vx_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16m4_mu(mask,merge,op1,shift,32); +} + + +vuint16m8_t test___riscv_vsrl_vx_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16m8_mu(mask,merge,op1,shift,32); +} + + +vuint32mf2_t test___riscv_vsrl_vx_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32mf2_mu(mask,merge,op1,shift,32); +} + + +vuint32m1_t test___riscv_vsrl_vx_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32m1_mu(mask,merge,op1,shift,32); +} + + +vuint32m2_t test___riscv_vsrl_vx_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32m2_mu(mask,merge,op1,shift,32); +} + + +vuint32m4_t test___riscv_vsrl_vx_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32m4_mu(mask,merge,op1,shift,32); +} + + +vuint32m8_t test___riscv_vsrl_vx_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32m8_mu(mask,merge,op1,shift,32); +} + + +vuint64m1_t test___riscv_vsrl_vx_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u64m1_mu(mask,merge,op1,shift,32); +} + + +vuint64m2_t test___riscv_vsrl_vx_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u64m2_mu(mask,merge,op1,shift,32); +} + + +vuint64m4_t test___riscv_vsrl_vx_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u64m4_mu(mask,merge,op1,shift,32); +} + + +vuint64m8_t test___riscv_vsrl_vx_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u64m8_mu(mask,merge,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_tu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_tu-1.c new file mode 100644 index 00000000000..69fe18b20ca --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_tu-1.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vsrl_vx_u8mf8_tu(vuint8mf8_t merge,vuint8mf8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8mf8_tu(merge,op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vsrl_vx_u8mf4_tu(vuint8mf4_t merge,vuint8mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8mf4_tu(merge,op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vsrl_vx_u8mf2_tu(vuint8mf2_t merge,vuint8mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8mf2_tu(merge,op1,shift,vl); +} + + +vuint8m1_t test___riscv_vsrl_vx_u8m1_tu(vuint8m1_t merge,vuint8m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8m1_tu(merge,op1,shift,vl); +} + + +vuint8m2_t test___riscv_vsrl_vx_u8m2_tu(vuint8m2_t merge,vuint8m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8m2_tu(merge,op1,shift,vl); +} + + +vuint8m4_t test___riscv_vsrl_vx_u8m4_tu(vuint8m4_t merge,vuint8m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8m4_tu(merge,op1,shift,vl); +} + + +vuint8m8_t test___riscv_vsrl_vx_u8m8_tu(vuint8m8_t merge,vuint8m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8m8_tu(merge,op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vsrl_vx_u16mf4_tu(vuint16mf4_t merge,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16mf4_tu(merge,op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vsrl_vx_u16mf2_tu(vuint16mf2_t merge,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16mf2_tu(merge,op1,shift,vl); +} + + +vuint16m1_t test___riscv_vsrl_vx_u16m1_tu(vuint16m1_t merge,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16m1_tu(merge,op1,shift,vl); +} + + +vuint16m2_t test___riscv_vsrl_vx_u16m2_tu(vuint16m2_t merge,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16m2_tu(merge,op1,shift,vl); +} + + +vuint16m4_t test___riscv_vsrl_vx_u16m4_tu(vuint16m4_t merge,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16m4_tu(merge,op1,shift,vl); +} + + +vuint16m8_t test___riscv_vsrl_vx_u16m8_tu(vuint16m8_t merge,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16m8_tu(merge,op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vsrl_vx_u32mf2_tu(vuint32mf2_t merge,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32mf2_tu(merge,op1,shift,vl); +} + + +vuint32m1_t test___riscv_vsrl_vx_u32m1_tu(vuint32m1_t merge,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32m1_tu(merge,op1,shift,vl); +} + + +vuint32m2_t test___riscv_vsrl_vx_u32m2_tu(vuint32m2_t merge,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32m2_tu(merge,op1,shift,vl); +} + + +vuint32m4_t test___riscv_vsrl_vx_u32m4_tu(vuint32m4_t merge,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32m4_tu(merge,op1,shift,vl); +} + + +vuint32m8_t test___riscv_vsrl_vx_u32m8_tu(vuint32m8_t merge,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32m8_tu(merge,op1,shift,vl); +} + + +vuint64m1_t test___riscv_vsrl_vx_u64m1_tu(vuint64m1_t merge,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u64m1_tu(merge,op1,shift,vl); +} + + +vuint64m2_t test___riscv_vsrl_vx_u64m2_tu(vuint64m2_t merge,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u64m2_tu(merge,op1,shift,vl); +} + + +vuint64m4_t test___riscv_vsrl_vx_u64m4_tu(vuint64m4_t merge,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u64m4_tu(merge,op1,shift,vl); +} + + +vuint64m8_t test___riscv_vsrl_vx_u64m8_tu(vuint64m8_t merge,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u64m8_tu(merge,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_tu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_tu-2.c new file mode 100644 index 00000000000..105930eb28a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_tu-2.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vsrl_vx_u8mf8_tu(vuint8mf8_t merge,vuint8mf8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8mf8_tu(merge,op1,shift,31); +} + + +vuint8mf4_t test___riscv_vsrl_vx_u8mf4_tu(vuint8mf4_t merge,vuint8mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8mf4_tu(merge,op1,shift,31); +} + + +vuint8mf2_t test___riscv_vsrl_vx_u8mf2_tu(vuint8mf2_t merge,vuint8mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8mf2_tu(merge,op1,shift,31); +} + + +vuint8m1_t test___riscv_vsrl_vx_u8m1_tu(vuint8m1_t merge,vuint8m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8m1_tu(merge,op1,shift,31); +} + + +vuint8m2_t test___riscv_vsrl_vx_u8m2_tu(vuint8m2_t merge,vuint8m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8m2_tu(merge,op1,shift,31); +} + + +vuint8m4_t test___riscv_vsrl_vx_u8m4_tu(vuint8m4_t merge,vuint8m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8m4_tu(merge,op1,shift,31); +} + + +vuint8m8_t test___riscv_vsrl_vx_u8m8_tu(vuint8m8_t merge,vuint8m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8m8_tu(merge,op1,shift,31); +} + + +vuint16mf4_t test___riscv_vsrl_vx_u16mf4_tu(vuint16mf4_t merge,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16mf4_tu(merge,op1,shift,31); +} + + +vuint16mf2_t test___riscv_vsrl_vx_u16mf2_tu(vuint16mf2_t merge,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16mf2_tu(merge,op1,shift,31); +} + + +vuint16m1_t test___riscv_vsrl_vx_u16m1_tu(vuint16m1_t merge,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16m1_tu(merge,op1,shift,31); +} + + +vuint16m2_t test___riscv_vsrl_vx_u16m2_tu(vuint16m2_t merge,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16m2_tu(merge,op1,shift,31); +} + + +vuint16m4_t test___riscv_vsrl_vx_u16m4_tu(vuint16m4_t merge,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16m4_tu(merge,op1,shift,31); +} + + +vuint16m8_t test___riscv_vsrl_vx_u16m8_tu(vuint16m8_t merge,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16m8_tu(merge,op1,shift,31); +} + + +vuint32mf2_t test___riscv_vsrl_vx_u32mf2_tu(vuint32mf2_t merge,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32mf2_tu(merge,op1,shift,31); +} + + +vuint32m1_t test___riscv_vsrl_vx_u32m1_tu(vuint32m1_t merge,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32m1_tu(merge,op1,shift,31); +} + + +vuint32m2_t test___riscv_vsrl_vx_u32m2_tu(vuint32m2_t merge,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32m2_tu(merge,op1,shift,31); +} + + +vuint32m4_t test___riscv_vsrl_vx_u32m4_tu(vuint32m4_t merge,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32m4_tu(merge,op1,shift,31); +} + + +vuint32m8_t test___riscv_vsrl_vx_u32m8_tu(vuint32m8_t merge,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32m8_tu(merge,op1,shift,31); +} + + +vuint64m1_t test___riscv_vsrl_vx_u64m1_tu(vuint64m1_t merge,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u64m1_tu(merge,op1,shift,31); +} + + +vuint64m2_t test___riscv_vsrl_vx_u64m2_tu(vuint64m2_t merge,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u64m2_tu(merge,op1,shift,31); +} + + +vuint64m4_t test___riscv_vsrl_vx_u64m4_tu(vuint64m4_t merge,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u64m4_tu(merge,op1,shift,31); +} + + +vuint64m8_t test___riscv_vsrl_vx_u64m8_tu(vuint64m8_t merge,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u64m8_tu(merge,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_tu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_tu-3.c new file mode 100644 index 00000000000..3a7c8f54102 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_tu-3.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vsrl_vx_u8mf8_tu(vuint8mf8_t merge,vuint8mf8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8mf8_tu(merge,op1,shift,32); +} + + +vuint8mf4_t test___riscv_vsrl_vx_u8mf4_tu(vuint8mf4_t merge,vuint8mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8mf4_tu(merge,op1,shift,32); +} + + +vuint8mf2_t test___riscv_vsrl_vx_u8mf2_tu(vuint8mf2_t merge,vuint8mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8mf2_tu(merge,op1,shift,32); +} + + +vuint8m1_t test___riscv_vsrl_vx_u8m1_tu(vuint8m1_t merge,vuint8m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8m1_tu(merge,op1,shift,32); +} + + +vuint8m2_t test___riscv_vsrl_vx_u8m2_tu(vuint8m2_t merge,vuint8m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8m2_tu(merge,op1,shift,32); +} + + +vuint8m4_t test___riscv_vsrl_vx_u8m4_tu(vuint8m4_t merge,vuint8m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8m4_tu(merge,op1,shift,32); +} + + +vuint8m8_t test___riscv_vsrl_vx_u8m8_tu(vuint8m8_t merge,vuint8m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8m8_tu(merge,op1,shift,32); +} + + +vuint16mf4_t test___riscv_vsrl_vx_u16mf4_tu(vuint16mf4_t merge,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16mf4_tu(merge,op1,shift,32); +} + + +vuint16mf2_t test___riscv_vsrl_vx_u16mf2_tu(vuint16mf2_t merge,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16mf2_tu(merge,op1,shift,32); +} + + +vuint16m1_t test___riscv_vsrl_vx_u16m1_tu(vuint16m1_t merge,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16m1_tu(merge,op1,shift,32); +} + + +vuint16m2_t test___riscv_vsrl_vx_u16m2_tu(vuint16m2_t merge,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16m2_tu(merge,op1,shift,32); +} + + +vuint16m4_t test___riscv_vsrl_vx_u16m4_tu(vuint16m4_t merge,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16m4_tu(merge,op1,shift,32); +} + + +vuint16m8_t test___riscv_vsrl_vx_u16m8_tu(vuint16m8_t merge,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16m8_tu(merge,op1,shift,32); +} + + +vuint32mf2_t test___riscv_vsrl_vx_u32mf2_tu(vuint32mf2_t merge,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32mf2_tu(merge,op1,shift,32); +} + + +vuint32m1_t test___riscv_vsrl_vx_u32m1_tu(vuint32m1_t merge,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32m1_tu(merge,op1,shift,32); +} + + +vuint32m2_t test___riscv_vsrl_vx_u32m2_tu(vuint32m2_t merge,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32m2_tu(merge,op1,shift,32); +} + + +vuint32m4_t test___riscv_vsrl_vx_u32m4_tu(vuint32m4_t merge,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32m4_tu(merge,op1,shift,32); +} + + +vuint32m8_t test___riscv_vsrl_vx_u32m8_tu(vuint32m8_t merge,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32m8_tu(merge,op1,shift,32); +} + + +vuint64m1_t test___riscv_vsrl_vx_u64m1_tu(vuint64m1_t merge,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u64m1_tu(merge,op1,shift,32); +} + + +vuint64m2_t test___riscv_vsrl_vx_u64m2_tu(vuint64m2_t merge,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u64m2_tu(merge,op1,shift,32); +} + + +vuint64m4_t test___riscv_vsrl_vx_u64m4_tu(vuint64m4_t merge,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u64m4_tu(merge,op1,shift,32); +} + + +vuint64m8_t test___riscv_vsrl_vx_u64m8_tu(vuint64m8_t merge,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u64m8_tu(merge,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_tum-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_tum-1.c new file mode 100644 index 00000000000..749e76fc9ac --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_tum-1.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vsrl_vx_u8mf8_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8mf8_tum(mask,merge,op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vsrl_vx_u8mf4_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8mf4_tum(mask,merge,op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vsrl_vx_u8mf2_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8mf2_tum(mask,merge,op1,shift,vl); +} + + +vuint8m1_t test___riscv_vsrl_vx_u8m1_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8m1_tum(mask,merge,op1,shift,vl); +} + + +vuint8m2_t test___riscv_vsrl_vx_u8m2_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8m2_tum(mask,merge,op1,shift,vl); +} + + +vuint8m4_t test___riscv_vsrl_vx_u8m4_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8m4_tum(mask,merge,op1,shift,vl); +} + + +vuint8m8_t test___riscv_vsrl_vx_u8m8_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8m8_tum(mask,merge,op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vsrl_vx_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16mf4_tum(mask,merge,op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vsrl_vx_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16mf2_tum(mask,merge,op1,shift,vl); +} + + +vuint16m1_t test___riscv_vsrl_vx_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16m1_tum(mask,merge,op1,shift,vl); +} + + +vuint16m2_t test___riscv_vsrl_vx_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16m2_tum(mask,merge,op1,shift,vl); +} + + +vuint16m4_t test___riscv_vsrl_vx_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16m4_tum(mask,merge,op1,shift,vl); +} + + +vuint16m8_t test___riscv_vsrl_vx_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16m8_tum(mask,merge,op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vsrl_vx_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32mf2_tum(mask,merge,op1,shift,vl); +} + + +vuint32m1_t test___riscv_vsrl_vx_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32m1_tum(mask,merge,op1,shift,vl); +} + + +vuint32m2_t test___riscv_vsrl_vx_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32m2_tum(mask,merge,op1,shift,vl); +} + + +vuint32m4_t test___riscv_vsrl_vx_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32m4_tum(mask,merge,op1,shift,vl); +} + + +vuint32m8_t test___riscv_vsrl_vx_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32m8_tum(mask,merge,op1,shift,vl); +} + + +vuint64m1_t test___riscv_vsrl_vx_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u64m1_tum(mask,merge,op1,shift,vl); +} + + +vuint64m2_t test___riscv_vsrl_vx_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u64m2_tum(mask,merge,op1,shift,vl); +} + + +vuint64m4_t test___riscv_vsrl_vx_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u64m4_tum(mask,merge,op1,shift,vl); +} + + +vuint64m8_t test___riscv_vsrl_vx_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u64m8_tum(mask,merge,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_tum-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_tum-2.c new file mode 100644 index 00000000000..3ac9579547b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_tum-2.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vsrl_vx_u8mf8_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8mf8_tum(mask,merge,op1,shift,31); +} + + +vuint8mf4_t test___riscv_vsrl_vx_u8mf4_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8mf4_tum(mask,merge,op1,shift,31); +} + + +vuint8mf2_t test___riscv_vsrl_vx_u8mf2_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8mf2_tum(mask,merge,op1,shift,31); +} + + +vuint8m1_t test___riscv_vsrl_vx_u8m1_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8m1_tum(mask,merge,op1,shift,31); +} + + +vuint8m2_t test___riscv_vsrl_vx_u8m2_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8m2_tum(mask,merge,op1,shift,31); +} + + +vuint8m4_t test___riscv_vsrl_vx_u8m4_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8m4_tum(mask,merge,op1,shift,31); +} + + +vuint8m8_t test___riscv_vsrl_vx_u8m8_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8m8_tum(mask,merge,op1,shift,31); +} + + +vuint16mf4_t test___riscv_vsrl_vx_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16mf4_tum(mask,merge,op1,shift,31); +} + + +vuint16mf2_t test___riscv_vsrl_vx_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16mf2_tum(mask,merge,op1,shift,31); +} + + +vuint16m1_t test___riscv_vsrl_vx_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16m1_tum(mask,merge,op1,shift,31); +} + + +vuint16m2_t test___riscv_vsrl_vx_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16m2_tum(mask,merge,op1,shift,31); +} + + +vuint16m4_t test___riscv_vsrl_vx_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16m4_tum(mask,merge,op1,shift,31); +} + + +vuint16m8_t test___riscv_vsrl_vx_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16m8_tum(mask,merge,op1,shift,31); +} + + +vuint32mf2_t test___riscv_vsrl_vx_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32mf2_tum(mask,merge,op1,shift,31); +} + + +vuint32m1_t test___riscv_vsrl_vx_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32m1_tum(mask,merge,op1,shift,31); +} + + +vuint32m2_t test___riscv_vsrl_vx_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32m2_tum(mask,merge,op1,shift,31); +} + + +vuint32m4_t test___riscv_vsrl_vx_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32m4_tum(mask,merge,op1,shift,31); +} + + +vuint32m8_t test___riscv_vsrl_vx_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32m8_tum(mask,merge,op1,shift,31); +} + + +vuint64m1_t test___riscv_vsrl_vx_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u64m1_tum(mask,merge,op1,shift,31); +} + + +vuint64m2_t test___riscv_vsrl_vx_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u64m2_tum(mask,merge,op1,shift,31); +} + + +vuint64m4_t test___riscv_vsrl_vx_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u64m4_tum(mask,merge,op1,shift,31); +} + + +vuint64m8_t test___riscv_vsrl_vx_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u64m8_tum(mask,merge,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_tum-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_tum-3.c new file mode 100644 index 00000000000..f12df7d9c1c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_tum-3.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vsrl_vx_u8mf8_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8mf8_tum(mask,merge,op1,shift,32); +} + + +vuint8mf4_t test___riscv_vsrl_vx_u8mf4_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8mf4_tum(mask,merge,op1,shift,32); +} + + +vuint8mf2_t test___riscv_vsrl_vx_u8mf2_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8mf2_tum(mask,merge,op1,shift,32); +} + + +vuint8m1_t test___riscv_vsrl_vx_u8m1_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8m1_tum(mask,merge,op1,shift,32); +} + + +vuint8m2_t test___riscv_vsrl_vx_u8m2_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8m2_tum(mask,merge,op1,shift,32); +} + + +vuint8m4_t test___riscv_vsrl_vx_u8m4_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8m4_tum(mask,merge,op1,shift,32); +} + + +vuint8m8_t test___riscv_vsrl_vx_u8m8_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8m8_tum(mask,merge,op1,shift,32); +} + + +vuint16mf4_t test___riscv_vsrl_vx_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16mf4_tum(mask,merge,op1,shift,32); +} + + +vuint16mf2_t test___riscv_vsrl_vx_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16mf2_tum(mask,merge,op1,shift,32); +} + + +vuint16m1_t test___riscv_vsrl_vx_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16m1_tum(mask,merge,op1,shift,32); +} + + +vuint16m2_t test___riscv_vsrl_vx_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16m2_tum(mask,merge,op1,shift,32); +} + + +vuint16m4_t test___riscv_vsrl_vx_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16m4_tum(mask,merge,op1,shift,32); +} + + +vuint16m8_t test___riscv_vsrl_vx_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16m8_tum(mask,merge,op1,shift,32); +} + + +vuint32mf2_t test___riscv_vsrl_vx_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32mf2_tum(mask,merge,op1,shift,32); +} + + +vuint32m1_t test___riscv_vsrl_vx_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32m1_tum(mask,merge,op1,shift,32); +} + + +vuint32m2_t test___riscv_vsrl_vx_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32m2_tum(mask,merge,op1,shift,32); +} + + +vuint32m4_t test___riscv_vsrl_vx_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32m4_tum(mask,merge,op1,shift,32); +} + + +vuint32m8_t test___riscv_vsrl_vx_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32m8_tum(mask,merge,op1,shift,32); +} + + +vuint64m1_t test___riscv_vsrl_vx_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u64m1_tum(mask,merge,op1,shift,32); +} + + +vuint64m2_t test___riscv_vsrl_vx_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u64m2_tum(mask,merge,op1,shift,32); +} + + +vuint64m4_t test___riscv_vsrl_vx_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u64m4_tum(mask,merge,op1,shift,32); +} + + +vuint64m8_t test___riscv_vsrl_vx_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u64m8_tum(mask,merge,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_tumu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_tumu-1.c new file mode 100644 index 00000000000..db7de74015b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_tumu-1.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vsrl_vx_u8mf8_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8mf8_tumu(mask,merge,op1,shift,vl); +} + + +vuint8mf4_t test___riscv_vsrl_vx_u8mf4_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8mf4_tumu(mask,merge,op1,shift,vl); +} + + +vuint8mf2_t test___riscv_vsrl_vx_u8mf2_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8mf2_tumu(mask,merge,op1,shift,vl); +} + + +vuint8m1_t test___riscv_vsrl_vx_u8m1_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8m1_tumu(mask,merge,op1,shift,vl); +} + + +vuint8m2_t test___riscv_vsrl_vx_u8m2_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8m2_tumu(mask,merge,op1,shift,vl); +} + + +vuint8m4_t test___riscv_vsrl_vx_u8m4_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8m4_tumu(mask,merge,op1,shift,vl); +} + + +vuint8m8_t test___riscv_vsrl_vx_u8m8_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8m8_tumu(mask,merge,op1,shift,vl); +} + + +vuint16mf4_t test___riscv_vsrl_vx_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16mf4_tumu(mask,merge,op1,shift,vl); +} + + +vuint16mf2_t test___riscv_vsrl_vx_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16mf2_tumu(mask,merge,op1,shift,vl); +} + + +vuint16m1_t test___riscv_vsrl_vx_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16m1_tumu(mask,merge,op1,shift,vl); +} + + +vuint16m2_t test___riscv_vsrl_vx_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16m2_tumu(mask,merge,op1,shift,vl); +} + + +vuint16m4_t test___riscv_vsrl_vx_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16m4_tumu(mask,merge,op1,shift,vl); +} + + +vuint16m8_t test___riscv_vsrl_vx_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16m8_tumu(mask,merge,op1,shift,vl); +} + + +vuint32mf2_t test___riscv_vsrl_vx_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32mf2_tumu(mask,merge,op1,shift,vl); +} + + +vuint32m1_t test___riscv_vsrl_vx_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32m1_tumu(mask,merge,op1,shift,vl); +} + + +vuint32m2_t test___riscv_vsrl_vx_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32m2_tumu(mask,merge,op1,shift,vl); +} + + +vuint32m4_t test___riscv_vsrl_vx_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32m4_tumu(mask,merge,op1,shift,vl); +} + + +vuint32m8_t test___riscv_vsrl_vx_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32m8_tumu(mask,merge,op1,shift,vl); +} + + +vuint64m1_t test___riscv_vsrl_vx_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u64m1_tumu(mask,merge,op1,shift,vl); +} + + +vuint64m2_t test___riscv_vsrl_vx_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u64m2_tumu(mask,merge,op1,shift,vl); +} + + +vuint64m4_t test___riscv_vsrl_vx_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u64m4_tumu(mask,merge,op1,shift,vl); +} + + +vuint64m8_t test___riscv_vsrl_vx_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u64m8_tumu(mask,merge,op1,shift,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_tumu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_tumu-2.c new file mode 100644 index 00000000000..935e18f9e73 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_tumu-2.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vsrl_vx_u8mf8_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8mf8_tumu(mask,merge,op1,shift,31); +} + + +vuint8mf4_t test___riscv_vsrl_vx_u8mf4_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8mf4_tumu(mask,merge,op1,shift,31); +} + + +vuint8mf2_t test___riscv_vsrl_vx_u8mf2_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8mf2_tumu(mask,merge,op1,shift,31); +} + + +vuint8m1_t test___riscv_vsrl_vx_u8m1_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8m1_tumu(mask,merge,op1,shift,31); +} + + +vuint8m2_t test___riscv_vsrl_vx_u8m2_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8m2_tumu(mask,merge,op1,shift,31); +} + + +vuint8m4_t test___riscv_vsrl_vx_u8m4_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8m4_tumu(mask,merge,op1,shift,31); +} + + +vuint8m8_t test___riscv_vsrl_vx_u8m8_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8m8_tumu(mask,merge,op1,shift,31); +} + + +vuint16mf4_t test___riscv_vsrl_vx_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16mf4_tumu(mask,merge,op1,shift,31); +} + + +vuint16mf2_t test___riscv_vsrl_vx_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16mf2_tumu(mask,merge,op1,shift,31); +} + + +vuint16m1_t test___riscv_vsrl_vx_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16m1_tumu(mask,merge,op1,shift,31); +} + + +vuint16m2_t test___riscv_vsrl_vx_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16m2_tumu(mask,merge,op1,shift,31); +} + + +vuint16m4_t test___riscv_vsrl_vx_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16m4_tumu(mask,merge,op1,shift,31); +} + + +vuint16m8_t test___riscv_vsrl_vx_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16m8_tumu(mask,merge,op1,shift,31); +} + + +vuint32mf2_t test___riscv_vsrl_vx_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32mf2_tumu(mask,merge,op1,shift,31); +} + + +vuint32m1_t test___riscv_vsrl_vx_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32m1_tumu(mask,merge,op1,shift,31); +} + + +vuint32m2_t test___riscv_vsrl_vx_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32m2_tumu(mask,merge,op1,shift,31); +} + + +vuint32m4_t test___riscv_vsrl_vx_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32m4_tumu(mask,merge,op1,shift,31); +} + + +vuint32m8_t test___riscv_vsrl_vx_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32m8_tumu(mask,merge,op1,shift,31); +} + + +vuint64m1_t test___riscv_vsrl_vx_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u64m1_tumu(mask,merge,op1,shift,31); +} + + +vuint64m2_t test___riscv_vsrl_vx_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u64m2_tumu(mask,merge,op1,shift,31); +} + + +vuint64m4_t test___riscv_vsrl_vx_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u64m4_tumu(mask,merge,op1,shift,31); +} + + +vuint64m8_t test___riscv_vsrl_vx_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u64m8_tumu(mask,merge,op1,shift,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_tumu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_tumu-3.c new file mode 100644 index 00000000000..3fbc48c1968 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsrl_vx_tumu-3.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vsrl_vx_u8mf8_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8mf8_tumu(mask,merge,op1,shift,32); +} + + +vuint8mf4_t test___riscv_vsrl_vx_u8mf4_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8mf4_tumu(mask,merge,op1,shift,32); +} + + +vuint8mf2_t test___riscv_vsrl_vx_u8mf2_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8mf2_tumu(mask,merge,op1,shift,32); +} + + +vuint8m1_t test___riscv_vsrl_vx_u8m1_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8m1_tumu(mask,merge,op1,shift,32); +} + + +vuint8m2_t test___riscv_vsrl_vx_u8m2_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8m2_tumu(mask,merge,op1,shift,32); +} + + +vuint8m4_t test___riscv_vsrl_vx_u8m4_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8m4_tumu(mask,merge,op1,shift,32); +} + + +vuint8m8_t test___riscv_vsrl_vx_u8m8_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u8m8_tumu(mask,merge,op1,shift,32); +} + + +vuint16mf4_t test___riscv_vsrl_vx_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16mf4_tumu(mask,merge,op1,shift,32); +} + + +vuint16mf2_t test___riscv_vsrl_vx_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16mf2_tumu(mask,merge,op1,shift,32); +} + + +vuint16m1_t test___riscv_vsrl_vx_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16m1_tumu(mask,merge,op1,shift,32); +} + + +vuint16m2_t test___riscv_vsrl_vx_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16m2_tumu(mask,merge,op1,shift,32); +} + + +vuint16m4_t test___riscv_vsrl_vx_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16m4_tumu(mask,merge,op1,shift,32); +} + + +vuint16m8_t test___riscv_vsrl_vx_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u16m8_tumu(mask,merge,op1,shift,32); +} + + +vuint32mf2_t test___riscv_vsrl_vx_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32mf2_tumu(mask,merge,op1,shift,32); +} + + +vuint32m1_t test___riscv_vsrl_vx_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32m1_tumu(mask,merge,op1,shift,32); +} + + +vuint32m2_t test___riscv_vsrl_vx_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32m2_tumu(mask,merge,op1,shift,32); +} + + +vuint32m4_t test___riscv_vsrl_vx_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32m4_tumu(mask,merge,op1,shift,32); +} + + +vuint32m8_t test___riscv_vsrl_vx_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u32m8_tumu(mask,merge,op1,shift,32); +} + + +vuint64m1_t test___riscv_vsrl_vx_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u64m1_tumu(mask,merge,op1,shift,32); +} + + +vuint64m2_t test___riscv_vsrl_vx_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u64m2_tumu(mask,merge,op1,shift,32); +} + + +vuint64m4_t test___riscv_vsrl_vx_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u64m4_tumu(mask,merge,op1,shift,32); +} + + +vuint64m8_t test___riscv_vsrl_vx_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,size_t shift,size_t vl) +{ + return __riscv_vsrl_vx_u64m8_tumu(mask,merge,op1,shift,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vsrl\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */ -- 2.36.3