[PATCH] RISC-V: Add vsra.vx C API tests

[juzhe.zhong@rivai.ai]

From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/rvv/base/vsra_vx-1.c: New test.
        * gcc.target/riscv/rvv/base/vsra_vx-2.c: New test.
        * gcc.target/riscv/rvv/base/vsra_vx-3.c: New test.
        * gcc.target/riscv/rvv/base/vsra_vx_m-1.c: New test.
        * gcc.target/riscv/rvv/base/vsra_vx_m-2.c: New test.
        * gcc.target/riscv/rvv/base/vsra_vx_m-3.c: New test.
        * gcc.target/riscv/rvv/base/vsra_vx_mu-1.c: New test.
        * gcc.target/riscv/rvv/base/vsra_vx_mu-2.c: New test.
        * gcc.target/riscv/rvv/base/vsra_vx_mu-3.c: New test.
        * gcc.target/riscv/rvv/base/vsra_vx_tu-1.c: New test.
        * gcc.target/riscv/rvv/base/vsra_vx_tu-2.c: New test.
        * gcc.target/riscv/rvv/base/vsra_vx_tu-3.c: New test.
        * gcc.target/riscv/rvv/base/vsra_vx_tum-1.c: New test.
        * gcc.target/riscv/rvv/base/vsra_vx_tum-2.c: New test.
        * gcc.target/riscv/rvv/base/vsra_vx_tum-3.c: New test.
        * gcc.target/riscv/rvv/base/vsra_vx_tumu-1.c: New test.
        * gcc.target/riscv/rvv/base/vsra_vx_tumu-2.c: New test.
        * gcc.target/riscv/rvv/base/vsra_vx_tumu-3.c: New test.

---
 .../gcc.target/riscv/rvv/base/vsra_vx-1.c     | 160 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vsra_vx-2.c     | 160 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vsra_vx-3.c     | 160 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vsra_vx_m-1.c   | 160 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vsra_vx_m-2.c   | 160 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vsra_vx_m-3.c   | 160 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vsra_vx_mu-1.c  | 160 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vsra_vx_mu-2.c  | 160 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vsra_vx_mu-3.c  | 160 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vsra_vx_tu-1.c  | 160 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vsra_vx_tu-2.c  | 160 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vsra_vx_tu-3.c  | 160 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vsra_vx_tum-1.c | 160 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vsra_vx_tum-2.c | 160 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vsra_vx_tum-3.c | 160 ++++++++++++++++++
 .../riscv/rvv/base/vsra_vx_tumu-1.c           | 160 ++++++++++++++++++
 .../riscv/rvv/base/vsra_vx_tumu-2.c           | 160 ++++++++++++++++++
 .../riscv/rvv/base/vsra_vx_tumu-3.c           | 160 ++++++++++++++++++
 18 files changed, 2880 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_m-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_m-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_m-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_mu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_mu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_mu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tum-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tum-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tum-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tumu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tumu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tumu-3.c

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx-1.c
new file mode 100644
index 00000000000..7a7a5a1a933
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx-1.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsra_vx_i8mf8(vint8mf8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8mf8(op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vsra_vx_i8mf4(vint8mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8mf4(op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vsra_vx_i8mf2(vint8mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8mf2(op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vsra_vx_i8m1(vint8m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8m1(op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vsra_vx_i8m2(vint8m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8m2(op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vsra_vx_i8m4(vint8m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8m4(op1,shift,vl);
+}
+
+
+vint8m8_t test___riscv_vsra_vx_i8m8(vint8m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8m8(op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vsra_vx_i16mf4(vint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16mf4(op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vsra_vx_i16mf2(vint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16mf2(op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vsra_vx_i16m1(vint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16m1(op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vsra_vx_i16m2(vint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16m2(op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vsra_vx_i16m4(vint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16m4(op1,shift,vl);
+}
+
+
+vint16m8_t test___riscv_vsra_vx_i16m8(vint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16m8(op1,shift,vl);
+}
+
+
+vint32mf2_t test___riscv_vsra_vx_i32mf2(vint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32mf2(op1,shift,vl);
+}
+
+
+vint32m1_t test___riscv_vsra_vx_i32m1(vint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32m1(op1,shift,vl);
+}
+
+
+vint32m2_t test___riscv_vsra_vx_i32m2(vint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32m2(op1,shift,vl);
+}
+
+
+vint32m4_t test___riscv_vsra_vx_i32m4(vint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32m4(op1,shift,vl);
+}
+
+
+vint32m8_t test___riscv_vsra_vx_i32m8(vint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32m8(op1,shift,vl);
+}
+
+
+vint64m1_t test___riscv_vsra_vx_i64m1(vint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i64m1(op1,shift,vl);
+}
+
+
+vint64m2_t test___riscv_vsra_vx_i64m2(vint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i64m2(op1,shift,vl);
+}
+
+
+vint64m4_t test___riscv_vsra_vx_i64m4(vint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i64m4(op1,shift,vl);
+}
+
+
+vint64m8_t test___riscv_vsra_vx_i64m8(vint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i64m8(op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx-2.c
new file mode 100644
index 00000000000..d9d8381297f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx-2.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsra_vx_i8mf8(vint8mf8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8mf8(op1,shift,31);
+}
+
+
+vint8mf4_t test___riscv_vsra_vx_i8mf4(vint8mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8mf4(op1,shift,31);
+}
+
+
+vint8mf2_t test___riscv_vsra_vx_i8mf2(vint8mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8mf2(op1,shift,31);
+}
+
+
+vint8m1_t test___riscv_vsra_vx_i8m1(vint8m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8m1(op1,shift,31);
+}
+
+
+vint8m2_t test___riscv_vsra_vx_i8m2(vint8m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8m2(op1,shift,31);
+}
+
+
+vint8m4_t test___riscv_vsra_vx_i8m4(vint8m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8m4(op1,shift,31);
+}
+
+
+vint8m8_t test___riscv_vsra_vx_i8m8(vint8m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8m8(op1,shift,31);
+}
+
+
+vint16mf4_t test___riscv_vsra_vx_i16mf4(vint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16mf4(op1,shift,31);
+}
+
+
+vint16mf2_t test___riscv_vsra_vx_i16mf2(vint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16mf2(op1,shift,31);
+}
+
+
+vint16m1_t test___riscv_vsra_vx_i16m1(vint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16m1(op1,shift,31);
+}
+
+
+vint16m2_t test___riscv_vsra_vx_i16m2(vint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16m2(op1,shift,31);
+}
+
+
+vint16m4_t test___riscv_vsra_vx_i16m4(vint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16m4(op1,shift,31);
+}
+
+
+vint16m8_t test___riscv_vsra_vx_i16m8(vint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16m8(op1,shift,31);
+}
+
+
+vint32mf2_t test___riscv_vsra_vx_i32mf2(vint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32mf2(op1,shift,31);
+}
+
+
+vint32m1_t test___riscv_vsra_vx_i32m1(vint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32m1(op1,shift,31);
+}
+
+
+vint32m2_t test___riscv_vsra_vx_i32m2(vint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32m2(op1,shift,31);
+}
+
+
+vint32m4_t test___riscv_vsra_vx_i32m4(vint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32m4(op1,shift,31);
+}
+
+
+vint32m8_t test___riscv_vsra_vx_i32m8(vint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32m8(op1,shift,31);
+}
+
+
+vint64m1_t test___riscv_vsra_vx_i64m1(vint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i64m1(op1,shift,31);
+}
+
+
+vint64m2_t test___riscv_vsra_vx_i64m2(vint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i64m2(op1,shift,31);
+}
+
+
+vint64m4_t test___riscv_vsra_vx_i64m4(vint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i64m4(op1,shift,31);
+}
+
+
+vint64m8_t test___riscv_vsra_vx_i64m8(vint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i64m8(op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx-3.c
new file mode 100644
index 00000000000..543b4502686
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx-3.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsra_vx_i8mf8(vint8mf8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8mf8(op1,shift,32);
+}
+
+
+vint8mf4_t test___riscv_vsra_vx_i8mf4(vint8mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8mf4(op1,shift,32);
+}
+
+
+vint8mf2_t test___riscv_vsra_vx_i8mf2(vint8mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8mf2(op1,shift,32);
+}
+
+
+vint8m1_t test___riscv_vsra_vx_i8m1(vint8m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8m1(op1,shift,32);
+}
+
+
+vint8m2_t test___riscv_vsra_vx_i8m2(vint8m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8m2(op1,shift,32);
+}
+
+
+vint8m4_t test___riscv_vsra_vx_i8m4(vint8m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8m4(op1,shift,32);
+}
+
+
+vint8m8_t test___riscv_vsra_vx_i8m8(vint8m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8m8(op1,shift,32);
+}
+
+
+vint16mf4_t test___riscv_vsra_vx_i16mf4(vint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16mf4(op1,shift,32);
+}
+
+
+vint16mf2_t test___riscv_vsra_vx_i16mf2(vint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16mf2(op1,shift,32);
+}
+
+
+vint16m1_t test___riscv_vsra_vx_i16m1(vint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16m1(op1,shift,32);
+}
+
+
+vint16m2_t test___riscv_vsra_vx_i16m2(vint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16m2(op1,shift,32);
+}
+
+
+vint16m4_t test___riscv_vsra_vx_i16m4(vint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16m4(op1,shift,32);
+}
+
+
+vint16m8_t test___riscv_vsra_vx_i16m8(vint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16m8(op1,shift,32);
+}
+
+
+vint32mf2_t test___riscv_vsra_vx_i32mf2(vint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32mf2(op1,shift,32);
+}
+
+
+vint32m1_t test___riscv_vsra_vx_i32m1(vint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32m1(op1,shift,32);
+}
+
+
+vint32m2_t test___riscv_vsra_vx_i32m2(vint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32m2(op1,shift,32);
+}
+
+
+vint32m4_t test___riscv_vsra_vx_i32m4(vint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32m4(op1,shift,32);
+}
+
+
+vint32m8_t test___riscv_vsra_vx_i32m8(vint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32m8(op1,shift,32);
+}
+
+
+vint64m1_t test___riscv_vsra_vx_i64m1(vint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i64m1(op1,shift,32);
+}
+
+
+vint64m2_t test___riscv_vsra_vx_i64m2(vint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i64m2(op1,shift,32);
+}
+
+
+vint64m4_t test___riscv_vsra_vx_i64m4(vint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i64m4(op1,shift,32);
+}
+
+
+vint64m8_t test___riscv_vsra_vx_i64m8(vint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i64m8(op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_m-1.c
new file mode 100644
index 00000000000..bab2ec44f2b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_m-1.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsra_vx_i8mf8_m(vbool64_t mask,vint8mf8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8mf8_m(mask,op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vsra_vx_i8mf4_m(vbool32_t mask,vint8mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8mf4_m(mask,op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vsra_vx_i8mf2_m(vbool16_t mask,vint8mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8mf2_m(mask,op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vsra_vx_i8m1_m(vbool8_t mask,vint8m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8m1_m(mask,op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vsra_vx_i8m2_m(vbool4_t mask,vint8m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8m2_m(mask,op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vsra_vx_i8m4_m(vbool2_t mask,vint8m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8m4_m(mask,op1,shift,vl);
+}
+
+
+vint8m8_t test___riscv_vsra_vx_i8m8_m(vbool1_t mask,vint8m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8m8_m(mask,op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vsra_vx_i16mf4_m(vbool64_t mask,vint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16mf4_m(mask,op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vsra_vx_i16mf2_m(vbool32_t mask,vint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16mf2_m(mask,op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vsra_vx_i16m1_m(vbool16_t mask,vint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16m1_m(mask,op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vsra_vx_i16m2_m(vbool8_t mask,vint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16m2_m(mask,op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vsra_vx_i16m4_m(vbool4_t mask,vint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16m4_m(mask,op1,shift,vl);
+}
+
+
+vint16m8_t test___riscv_vsra_vx_i16m8_m(vbool2_t mask,vint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16m8_m(mask,op1,shift,vl);
+}
+
+
+vint32mf2_t test___riscv_vsra_vx_i32mf2_m(vbool64_t mask,vint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32mf2_m(mask,op1,shift,vl);
+}
+
+
+vint32m1_t test___riscv_vsra_vx_i32m1_m(vbool32_t mask,vint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32m1_m(mask,op1,shift,vl);
+}
+
+
+vint32m2_t test___riscv_vsra_vx_i32m2_m(vbool16_t mask,vint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32m2_m(mask,op1,shift,vl);
+}
+
+
+vint32m4_t test___riscv_vsra_vx_i32m4_m(vbool8_t mask,vint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32m4_m(mask,op1,shift,vl);
+}
+
+
+vint32m8_t test___riscv_vsra_vx_i32m8_m(vbool4_t mask,vint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32m8_m(mask,op1,shift,vl);
+}
+
+
+vint64m1_t test___riscv_vsra_vx_i64m1_m(vbool64_t mask,vint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i64m1_m(mask,op1,shift,vl);
+}
+
+
+vint64m2_t test___riscv_vsra_vx_i64m2_m(vbool32_t mask,vint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i64m2_m(mask,op1,shift,vl);
+}
+
+
+vint64m4_t test___riscv_vsra_vx_i64m4_m(vbool16_t mask,vint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i64m4_m(mask,op1,shift,vl);
+}
+
+
+vint64m8_t test___riscv_vsra_vx_i64m8_m(vbool8_t mask,vint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i64m8_m(mask,op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_m-2.c
new file mode 100644
index 00000000000..bb5c9f93798
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_m-2.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsra_vx_i8mf8_m(vbool64_t mask,vint8mf8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8mf8_m(mask,op1,shift,31);
+}
+
+
+vint8mf4_t test___riscv_vsra_vx_i8mf4_m(vbool32_t mask,vint8mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8mf4_m(mask,op1,shift,31);
+}
+
+
+vint8mf2_t test___riscv_vsra_vx_i8mf2_m(vbool16_t mask,vint8mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8mf2_m(mask,op1,shift,31);
+}
+
+
+vint8m1_t test___riscv_vsra_vx_i8m1_m(vbool8_t mask,vint8m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8m1_m(mask,op1,shift,31);
+}
+
+
+vint8m2_t test___riscv_vsra_vx_i8m2_m(vbool4_t mask,vint8m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8m2_m(mask,op1,shift,31);
+}
+
+
+vint8m4_t test___riscv_vsra_vx_i8m4_m(vbool2_t mask,vint8m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8m4_m(mask,op1,shift,31);
+}
+
+
+vint8m8_t test___riscv_vsra_vx_i8m8_m(vbool1_t mask,vint8m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8m8_m(mask,op1,shift,31);
+}
+
+
+vint16mf4_t test___riscv_vsra_vx_i16mf4_m(vbool64_t mask,vint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16mf4_m(mask,op1,shift,31);
+}
+
+
+vint16mf2_t test___riscv_vsra_vx_i16mf2_m(vbool32_t mask,vint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16mf2_m(mask,op1,shift,31);
+}
+
+
+vint16m1_t test___riscv_vsra_vx_i16m1_m(vbool16_t mask,vint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16m1_m(mask,op1,shift,31);
+}
+
+
+vint16m2_t test___riscv_vsra_vx_i16m2_m(vbool8_t mask,vint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16m2_m(mask,op1,shift,31);
+}
+
+
+vint16m4_t test___riscv_vsra_vx_i16m4_m(vbool4_t mask,vint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16m4_m(mask,op1,shift,31);
+}
+
+
+vint16m8_t test___riscv_vsra_vx_i16m8_m(vbool2_t mask,vint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16m8_m(mask,op1,shift,31);
+}
+
+
+vint32mf2_t test___riscv_vsra_vx_i32mf2_m(vbool64_t mask,vint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32mf2_m(mask,op1,shift,31);
+}
+
+
+vint32m1_t test___riscv_vsra_vx_i32m1_m(vbool32_t mask,vint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32m1_m(mask,op1,shift,31);
+}
+
+
+vint32m2_t test___riscv_vsra_vx_i32m2_m(vbool16_t mask,vint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32m2_m(mask,op1,shift,31);
+}
+
+
+vint32m4_t test___riscv_vsra_vx_i32m4_m(vbool8_t mask,vint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32m4_m(mask,op1,shift,31);
+}
+
+
+vint32m8_t test___riscv_vsra_vx_i32m8_m(vbool4_t mask,vint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32m8_m(mask,op1,shift,31);
+}
+
+
+vint64m1_t test___riscv_vsra_vx_i64m1_m(vbool64_t mask,vint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i64m1_m(mask,op1,shift,31);
+}
+
+
+vint64m2_t test___riscv_vsra_vx_i64m2_m(vbool32_t mask,vint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i64m2_m(mask,op1,shift,31);
+}
+
+
+vint64m4_t test___riscv_vsra_vx_i64m4_m(vbool16_t mask,vint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i64m4_m(mask,op1,shift,31);
+}
+
+
+vint64m8_t test___riscv_vsra_vx_i64m8_m(vbool8_t mask,vint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i64m8_m(mask,op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_m-3.c
new file mode 100644
index 00000000000..1d088c5021b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_m-3.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsra_vx_i8mf8_m(vbool64_t mask,vint8mf8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8mf8_m(mask,op1,shift,32);
+}
+
+
+vint8mf4_t test___riscv_vsra_vx_i8mf4_m(vbool32_t mask,vint8mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8mf4_m(mask,op1,shift,32);
+}
+
+
+vint8mf2_t test___riscv_vsra_vx_i8mf2_m(vbool16_t mask,vint8mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8mf2_m(mask,op1,shift,32);
+}
+
+
+vint8m1_t test___riscv_vsra_vx_i8m1_m(vbool8_t mask,vint8m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8m1_m(mask,op1,shift,32);
+}
+
+
+vint8m2_t test___riscv_vsra_vx_i8m2_m(vbool4_t mask,vint8m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8m2_m(mask,op1,shift,32);
+}
+
+
+vint8m4_t test___riscv_vsra_vx_i8m4_m(vbool2_t mask,vint8m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8m4_m(mask,op1,shift,32);
+}
+
+
+vint8m8_t test___riscv_vsra_vx_i8m8_m(vbool1_t mask,vint8m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8m8_m(mask,op1,shift,32);
+}
+
+
+vint16mf4_t test___riscv_vsra_vx_i16mf4_m(vbool64_t mask,vint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16mf4_m(mask,op1,shift,32);
+}
+
+
+vint16mf2_t test___riscv_vsra_vx_i16mf2_m(vbool32_t mask,vint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16mf2_m(mask,op1,shift,32);
+}
+
+
+vint16m1_t test___riscv_vsra_vx_i16m1_m(vbool16_t mask,vint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16m1_m(mask,op1,shift,32);
+}
+
+
+vint16m2_t test___riscv_vsra_vx_i16m2_m(vbool8_t mask,vint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16m2_m(mask,op1,shift,32);
+}
+
+
+vint16m4_t test___riscv_vsra_vx_i16m4_m(vbool4_t mask,vint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16m4_m(mask,op1,shift,32);
+}
+
+
+vint16m8_t test___riscv_vsra_vx_i16m8_m(vbool2_t mask,vint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16m8_m(mask,op1,shift,32);
+}
+
+
+vint32mf2_t test___riscv_vsra_vx_i32mf2_m(vbool64_t mask,vint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32mf2_m(mask,op1,shift,32);
+}
+
+
+vint32m1_t test___riscv_vsra_vx_i32m1_m(vbool32_t mask,vint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32m1_m(mask,op1,shift,32);
+}
+
+
+vint32m2_t test___riscv_vsra_vx_i32m2_m(vbool16_t mask,vint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32m2_m(mask,op1,shift,32);
+}
+
+
+vint32m4_t test___riscv_vsra_vx_i32m4_m(vbool8_t mask,vint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32m4_m(mask,op1,shift,32);
+}
+
+
+vint32m8_t test___riscv_vsra_vx_i32m8_m(vbool4_t mask,vint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32m8_m(mask,op1,shift,32);
+}
+
+
+vint64m1_t test___riscv_vsra_vx_i64m1_m(vbool64_t mask,vint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i64m1_m(mask,op1,shift,32);
+}
+
+
+vint64m2_t test___riscv_vsra_vx_i64m2_m(vbool32_t mask,vint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i64m2_m(mask,op1,shift,32);
+}
+
+
+vint64m4_t test___riscv_vsra_vx_i64m4_m(vbool16_t mask,vint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i64m4_m(mask,op1,shift,32);
+}
+
+
+vint64m8_t test___riscv_vsra_vx_i64m8_m(vbool8_t mask,vint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i64m8_m(mask,op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_mu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_mu-1.c
new file mode 100644
index 00000000000..2885dc57793
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_mu-1.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsra_vx_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8mf8_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vsra_vx_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8mf4_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vsra_vx_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8mf2_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vsra_vx_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8m1_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vsra_vx_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8m2_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vsra_vx_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8m4_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m8_t test___riscv_vsra_vx_i8m8_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8m8_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vsra_vx_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16mf4_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vsra_vx_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16mf2_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vsra_vx_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16m1_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vsra_vx_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16m2_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vsra_vx_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16m4_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m8_t test___riscv_vsra_vx_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16m8_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint32mf2_t test___riscv_vsra_vx_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32mf2_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m1_t test___riscv_vsra_vx_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32m1_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m2_t test___riscv_vsra_vx_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32m2_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m4_t test___riscv_vsra_vx_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32m4_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m8_t test___riscv_vsra_vx_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32m8_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint64m1_t test___riscv_vsra_vx_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i64m1_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint64m2_t test___riscv_vsra_vx_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i64m2_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint64m4_t test___riscv_vsra_vx_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i64m4_mu(mask,merge,op1,shift,vl);
+}
+
+
+vint64m8_t test___riscv_vsra_vx_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i64m8_mu(mask,merge,op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_mu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_mu-2.c
new file mode 100644
index 00000000000..467a513587f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_mu-2.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsra_vx_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8mf8_mu(mask,merge,op1,shift,31);
+}
+
+
+vint8mf4_t test___riscv_vsra_vx_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8mf4_mu(mask,merge,op1,shift,31);
+}
+
+
+vint8mf2_t test___riscv_vsra_vx_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8mf2_mu(mask,merge,op1,shift,31);
+}
+
+
+vint8m1_t test___riscv_vsra_vx_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8m1_mu(mask,merge,op1,shift,31);
+}
+
+
+vint8m2_t test___riscv_vsra_vx_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8m2_mu(mask,merge,op1,shift,31);
+}
+
+
+vint8m4_t test___riscv_vsra_vx_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8m4_mu(mask,merge,op1,shift,31);
+}
+
+
+vint8m8_t test___riscv_vsra_vx_i8m8_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8m8_mu(mask,merge,op1,shift,31);
+}
+
+
+vint16mf4_t test___riscv_vsra_vx_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16mf4_mu(mask,merge,op1,shift,31);
+}
+
+
+vint16mf2_t test___riscv_vsra_vx_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16mf2_mu(mask,merge,op1,shift,31);
+}
+
+
+vint16m1_t test___riscv_vsra_vx_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16m1_mu(mask,merge,op1,shift,31);
+}
+
+
+vint16m2_t test___riscv_vsra_vx_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16m2_mu(mask,merge,op1,shift,31);
+}
+
+
+vint16m4_t test___riscv_vsra_vx_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16m4_mu(mask,merge,op1,shift,31);
+}
+
+
+vint16m8_t test___riscv_vsra_vx_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16m8_mu(mask,merge,op1,shift,31);
+}
+
+
+vint32mf2_t test___riscv_vsra_vx_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32mf2_mu(mask,merge,op1,shift,31);
+}
+
+
+vint32m1_t test___riscv_vsra_vx_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32m1_mu(mask,merge,op1,shift,31);
+}
+
+
+vint32m2_t test___riscv_vsra_vx_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32m2_mu(mask,merge,op1,shift,31);
+}
+
+
+vint32m4_t test___riscv_vsra_vx_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32m4_mu(mask,merge,op1,shift,31);
+}
+
+
+vint32m8_t test___riscv_vsra_vx_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32m8_mu(mask,merge,op1,shift,31);
+}
+
+
+vint64m1_t test___riscv_vsra_vx_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i64m1_mu(mask,merge,op1,shift,31);
+}
+
+
+vint64m2_t test___riscv_vsra_vx_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i64m2_mu(mask,merge,op1,shift,31);
+}
+
+
+vint64m4_t test___riscv_vsra_vx_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i64m4_mu(mask,merge,op1,shift,31);
+}
+
+
+vint64m8_t test___riscv_vsra_vx_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i64m8_mu(mask,merge,op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_mu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_mu-3.c
new file mode 100644
index 00000000000..ca8882a3ef4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_mu-3.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsra_vx_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8mf8_mu(mask,merge,op1,shift,32);
+}
+
+
+vint8mf4_t test___riscv_vsra_vx_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8mf4_mu(mask,merge,op1,shift,32);
+}
+
+
+vint8mf2_t test___riscv_vsra_vx_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8mf2_mu(mask,merge,op1,shift,32);
+}
+
+
+vint8m1_t test___riscv_vsra_vx_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8m1_mu(mask,merge,op1,shift,32);
+}
+
+
+vint8m2_t test___riscv_vsra_vx_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8m2_mu(mask,merge,op1,shift,32);
+}
+
+
+vint8m4_t test___riscv_vsra_vx_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8m4_mu(mask,merge,op1,shift,32);
+}
+
+
+vint8m8_t test___riscv_vsra_vx_i8m8_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8m8_mu(mask,merge,op1,shift,32);
+}
+
+
+vint16mf4_t test___riscv_vsra_vx_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16mf4_mu(mask,merge,op1,shift,32);
+}
+
+
+vint16mf2_t test___riscv_vsra_vx_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16mf2_mu(mask,merge,op1,shift,32);
+}
+
+
+vint16m1_t test___riscv_vsra_vx_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16m1_mu(mask,merge,op1,shift,32);
+}
+
+
+vint16m2_t test___riscv_vsra_vx_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16m2_mu(mask,merge,op1,shift,32);
+}
+
+
+vint16m4_t test___riscv_vsra_vx_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16m4_mu(mask,merge,op1,shift,32);
+}
+
+
+vint16m8_t test___riscv_vsra_vx_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16m8_mu(mask,merge,op1,shift,32);
+}
+
+
+vint32mf2_t test___riscv_vsra_vx_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32mf2_mu(mask,merge,op1,shift,32);
+}
+
+
+vint32m1_t test___riscv_vsra_vx_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32m1_mu(mask,merge,op1,shift,32);
+}
+
+
+vint32m2_t test___riscv_vsra_vx_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32m2_mu(mask,merge,op1,shift,32);
+}
+
+
+vint32m4_t test___riscv_vsra_vx_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32m4_mu(mask,merge,op1,shift,32);
+}
+
+
+vint32m8_t test___riscv_vsra_vx_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32m8_mu(mask,merge,op1,shift,32);
+}
+
+
+vint64m1_t test___riscv_vsra_vx_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i64m1_mu(mask,merge,op1,shift,32);
+}
+
+
+vint64m2_t test___riscv_vsra_vx_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i64m2_mu(mask,merge,op1,shift,32);
+}
+
+
+vint64m4_t test___riscv_vsra_vx_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i64m4_mu(mask,merge,op1,shift,32);
+}
+
+
+vint64m8_t test___riscv_vsra_vx_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i64m8_mu(mask,merge,op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tu-1.c
new file mode 100644
index 00000000000..3d3bf5cae89
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tu-1.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsra_vx_i8mf8_tu(vint8mf8_t merge,vint8mf8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8mf8_tu(merge,op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vsra_vx_i8mf4_tu(vint8mf4_t merge,vint8mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8mf4_tu(merge,op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vsra_vx_i8mf2_tu(vint8mf2_t merge,vint8mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8mf2_tu(merge,op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vsra_vx_i8m1_tu(vint8m1_t merge,vint8m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8m1_tu(merge,op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vsra_vx_i8m2_tu(vint8m2_t merge,vint8m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8m2_tu(merge,op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vsra_vx_i8m4_tu(vint8m4_t merge,vint8m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8m4_tu(merge,op1,shift,vl);
+}
+
+
+vint8m8_t test___riscv_vsra_vx_i8m8_tu(vint8m8_t merge,vint8m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8m8_tu(merge,op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vsra_vx_i16mf4_tu(vint16mf4_t merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16mf4_tu(merge,op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vsra_vx_i16mf2_tu(vint16mf2_t merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16mf2_tu(merge,op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vsra_vx_i16m1_tu(vint16m1_t merge,vint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16m1_tu(merge,op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vsra_vx_i16m2_tu(vint16m2_t merge,vint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16m2_tu(merge,op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vsra_vx_i16m4_tu(vint16m4_t merge,vint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16m4_tu(merge,op1,shift,vl);
+}
+
+
+vint16m8_t test___riscv_vsra_vx_i16m8_tu(vint16m8_t merge,vint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16m8_tu(merge,op1,shift,vl);
+}
+
+
+vint32mf2_t test___riscv_vsra_vx_i32mf2_tu(vint32mf2_t merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32mf2_tu(merge,op1,shift,vl);
+}
+
+
+vint32m1_t test___riscv_vsra_vx_i32m1_tu(vint32m1_t merge,vint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32m1_tu(merge,op1,shift,vl);
+}
+
+
+vint32m2_t test___riscv_vsra_vx_i32m2_tu(vint32m2_t merge,vint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32m2_tu(merge,op1,shift,vl);
+}
+
+
+vint32m4_t test___riscv_vsra_vx_i32m4_tu(vint32m4_t merge,vint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32m4_tu(merge,op1,shift,vl);
+}
+
+
+vint32m8_t test___riscv_vsra_vx_i32m8_tu(vint32m8_t merge,vint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32m8_tu(merge,op1,shift,vl);
+}
+
+
+vint64m1_t test___riscv_vsra_vx_i64m1_tu(vint64m1_t merge,vint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i64m1_tu(merge,op1,shift,vl);
+}
+
+
+vint64m2_t test___riscv_vsra_vx_i64m2_tu(vint64m2_t merge,vint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i64m2_tu(merge,op1,shift,vl);
+}
+
+
+vint64m4_t test___riscv_vsra_vx_i64m4_tu(vint64m4_t merge,vint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i64m4_tu(merge,op1,shift,vl);
+}
+
+
+vint64m8_t test___riscv_vsra_vx_i64m8_tu(vint64m8_t merge,vint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i64m8_tu(merge,op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tu-2.c
new file mode 100644
index 00000000000..1bbc62eec7a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tu-2.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsra_vx_i8mf8_tu(vint8mf8_t merge,vint8mf8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8mf8_tu(merge,op1,shift,31);
+}
+
+
+vint8mf4_t test___riscv_vsra_vx_i8mf4_tu(vint8mf4_t merge,vint8mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8mf4_tu(merge,op1,shift,31);
+}
+
+
+vint8mf2_t test___riscv_vsra_vx_i8mf2_tu(vint8mf2_t merge,vint8mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8mf2_tu(merge,op1,shift,31);
+}
+
+
+vint8m1_t test___riscv_vsra_vx_i8m1_tu(vint8m1_t merge,vint8m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8m1_tu(merge,op1,shift,31);
+}
+
+
+vint8m2_t test___riscv_vsra_vx_i8m2_tu(vint8m2_t merge,vint8m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8m2_tu(merge,op1,shift,31);
+}
+
+
+vint8m4_t test___riscv_vsra_vx_i8m4_tu(vint8m4_t merge,vint8m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8m4_tu(merge,op1,shift,31);
+}
+
+
+vint8m8_t test___riscv_vsra_vx_i8m8_tu(vint8m8_t merge,vint8m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8m8_tu(merge,op1,shift,31);
+}
+
+
+vint16mf4_t test___riscv_vsra_vx_i16mf4_tu(vint16mf4_t merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16mf4_tu(merge,op1,shift,31);
+}
+
+
+vint16mf2_t test___riscv_vsra_vx_i16mf2_tu(vint16mf2_t merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16mf2_tu(merge,op1,shift,31);
+}
+
+
+vint16m1_t test___riscv_vsra_vx_i16m1_tu(vint16m1_t merge,vint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16m1_tu(merge,op1,shift,31);
+}
+
+
+vint16m2_t test___riscv_vsra_vx_i16m2_tu(vint16m2_t merge,vint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16m2_tu(merge,op1,shift,31);
+}
+
+
+vint16m4_t test___riscv_vsra_vx_i16m4_tu(vint16m4_t merge,vint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16m4_tu(merge,op1,shift,31);
+}
+
+
+vint16m8_t test___riscv_vsra_vx_i16m8_tu(vint16m8_t merge,vint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16m8_tu(merge,op1,shift,31);
+}
+
+
+vint32mf2_t test___riscv_vsra_vx_i32mf2_tu(vint32mf2_t merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32mf2_tu(merge,op1,shift,31);
+}
+
+
+vint32m1_t test___riscv_vsra_vx_i32m1_tu(vint32m1_t merge,vint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32m1_tu(merge,op1,shift,31);
+}
+
+
+vint32m2_t test___riscv_vsra_vx_i32m2_tu(vint32m2_t merge,vint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32m2_tu(merge,op1,shift,31);
+}
+
+
+vint32m4_t test___riscv_vsra_vx_i32m4_tu(vint32m4_t merge,vint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32m4_tu(merge,op1,shift,31);
+}
+
+
+vint32m8_t test___riscv_vsra_vx_i32m8_tu(vint32m8_t merge,vint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32m8_tu(merge,op1,shift,31);
+}
+
+
+vint64m1_t test___riscv_vsra_vx_i64m1_tu(vint64m1_t merge,vint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i64m1_tu(merge,op1,shift,31);
+}
+
+
+vint64m2_t test___riscv_vsra_vx_i64m2_tu(vint64m2_t merge,vint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i64m2_tu(merge,op1,shift,31);
+}
+
+
+vint64m4_t test___riscv_vsra_vx_i64m4_tu(vint64m4_t merge,vint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i64m4_tu(merge,op1,shift,31);
+}
+
+
+vint64m8_t test___riscv_vsra_vx_i64m8_tu(vint64m8_t merge,vint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i64m8_tu(merge,op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tu-3.c
new file mode 100644
index 00000000000..40d93cd4819
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tu-3.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsra_vx_i8mf8_tu(vint8mf8_t merge,vint8mf8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8mf8_tu(merge,op1,shift,32);
+}
+
+
+vint8mf4_t test___riscv_vsra_vx_i8mf4_tu(vint8mf4_t merge,vint8mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8mf4_tu(merge,op1,shift,32);
+}
+
+
+vint8mf2_t test___riscv_vsra_vx_i8mf2_tu(vint8mf2_t merge,vint8mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8mf2_tu(merge,op1,shift,32);
+}
+
+
+vint8m1_t test___riscv_vsra_vx_i8m1_tu(vint8m1_t merge,vint8m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8m1_tu(merge,op1,shift,32);
+}
+
+
+vint8m2_t test___riscv_vsra_vx_i8m2_tu(vint8m2_t merge,vint8m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8m2_tu(merge,op1,shift,32);
+}
+
+
+vint8m4_t test___riscv_vsra_vx_i8m4_tu(vint8m4_t merge,vint8m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8m4_tu(merge,op1,shift,32);
+}
+
+
+vint8m8_t test___riscv_vsra_vx_i8m8_tu(vint8m8_t merge,vint8m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8m8_tu(merge,op1,shift,32);
+}
+
+
+vint16mf4_t test___riscv_vsra_vx_i16mf4_tu(vint16mf4_t merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16mf4_tu(merge,op1,shift,32);
+}
+
+
+vint16mf2_t test___riscv_vsra_vx_i16mf2_tu(vint16mf2_t merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16mf2_tu(merge,op1,shift,32);
+}
+
+
+vint16m1_t test___riscv_vsra_vx_i16m1_tu(vint16m1_t merge,vint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16m1_tu(merge,op1,shift,32);
+}
+
+
+vint16m2_t test___riscv_vsra_vx_i16m2_tu(vint16m2_t merge,vint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16m2_tu(merge,op1,shift,32);
+}
+
+
+vint16m4_t test___riscv_vsra_vx_i16m4_tu(vint16m4_t merge,vint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16m4_tu(merge,op1,shift,32);
+}
+
+
+vint16m8_t test___riscv_vsra_vx_i16m8_tu(vint16m8_t merge,vint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16m8_tu(merge,op1,shift,32);
+}
+
+
+vint32mf2_t test___riscv_vsra_vx_i32mf2_tu(vint32mf2_t merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32mf2_tu(merge,op1,shift,32);
+}
+
+
+vint32m1_t test___riscv_vsra_vx_i32m1_tu(vint32m1_t merge,vint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32m1_tu(merge,op1,shift,32);
+}
+
+
+vint32m2_t test___riscv_vsra_vx_i32m2_tu(vint32m2_t merge,vint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32m2_tu(merge,op1,shift,32);
+}
+
+
+vint32m4_t test___riscv_vsra_vx_i32m4_tu(vint32m4_t merge,vint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32m4_tu(merge,op1,shift,32);
+}
+
+
+vint32m8_t test___riscv_vsra_vx_i32m8_tu(vint32m8_t merge,vint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32m8_tu(merge,op1,shift,32);
+}
+
+
+vint64m1_t test___riscv_vsra_vx_i64m1_tu(vint64m1_t merge,vint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i64m1_tu(merge,op1,shift,32);
+}
+
+
+vint64m2_t test___riscv_vsra_vx_i64m2_tu(vint64m2_t merge,vint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i64m2_tu(merge,op1,shift,32);
+}
+
+
+vint64m4_t test___riscv_vsra_vx_i64m4_tu(vint64m4_t merge,vint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i64m4_tu(merge,op1,shift,32);
+}
+
+
+vint64m8_t test___riscv_vsra_vx_i64m8_tu(vint64m8_t merge,vint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i64m8_tu(merge,op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tum-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tum-1.c
new file mode 100644
index 00000000000..13733ab5790
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tum-1.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsra_vx_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8mf8_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vsra_vx_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8mf4_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vsra_vx_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8mf2_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vsra_vx_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8m1_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vsra_vx_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8m2_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vsra_vx_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8m4_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint8m8_t test___riscv_vsra_vx_i8m8_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8m8_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vsra_vx_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16mf4_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vsra_vx_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16mf2_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vsra_vx_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16m1_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vsra_vx_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16m2_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vsra_vx_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16m4_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint16m8_t test___riscv_vsra_vx_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16m8_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint32mf2_t test___riscv_vsra_vx_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32mf2_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint32m1_t test___riscv_vsra_vx_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32m1_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint32m2_t test___riscv_vsra_vx_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32m2_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint32m4_t test___riscv_vsra_vx_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32m4_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint32m8_t test___riscv_vsra_vx_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32m8_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint64m1_t test___riscv_vsra_vx_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i64m1_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint64m2_t test___riscv_vsra_vx_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i64m2_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint64m4_t test___riscv_vsra_vx_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i64m4_tum(mask,merge,op1,shift,vl);
+}
+
+
+vint64m8_t test___riscv_vsra_vx_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i64m8_tum(mask,merge,op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tum-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tum-2.c
new file mode 100644
index 00000000000..de095529474
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tum-2.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsra_vx_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8mf8_tum(mask,merge,op1,shift,31);
+}
+
+
+vint8mf4_t test___riscv_vsra_vx_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8mf4_tum(mask,merge,op1,shift,31);
+}
+
+
+vint8mf2_t test___riscv_vsra_vx_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8mf2_tum(mask,merge,op1,shift,31);
+}
+
+
+vint8m1_t test___riscv_vsra_vx_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8m1_tum(mask,merge,op1,shift,31);
+}
+
+
+vint8m2_t test___riscv_vsra_vx_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8m2_tum(mask,merge,op1,shift,31);
+}
+
+
+vint8m4_t test___riscv_vsra_vx_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8m4_tum(mask,merge,op1,shift,31);
+}
+
+
+vint8m8_t test___riscv_vsra_vx_i8m8_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8m8_tum(mask,merge,op1,shift,31);
+}
+
+
+vint16mf4_t test___riscv_vsra_vx_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16mf4_tum(mask,merge,op1,shift,31);
+}
+
+
+vint16mf2_t test___riscv_vsra_vx_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16mf2_tum(mask,merge,op1,shift,31);
+}
+
+
+vint16m1_t test___riscv_vsra_vx_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16m1_tum(mask,merge,op1,shift,31);
+}
+
+
+vint16m2_t test___riscv_vsra_vx_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16m2_tum(mask,merge,op1,shift,31);
+}
+
+
+vint16m4_t test___riscv_vsra_vx_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16m4_tum(mask,merge,op1,shift,31);
+}
+
+
+vint16m8_t test___riscv_vsra_vx_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16m8_tum(mask,merge,op1,shift,31);
+}
+
+
+vint32mf2_t test___riscv_vsra_vx_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32mf2_tum(mask,merge,op1,shift,31);
+}
+
+
+vint32m1_t test___riscv_vsra_vx_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32m1_tum(mask,merge,op1,shift,31);
+}
+
+
+vint32m2_t test___riscv_vsra_vx_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32m2_tum(mask,merge,op1,shift,31);
+}
+
+
+vint32m4_t test___riscv_vsra_vx_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32m4_tum(mask,merge,op1,shift,31);
+}
+
+
+vint32m8_t test___riscv_vsra_vx_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32m8_tum(mask,merge,op1,shift,31);
+}
+
+
+vint64m1_t test___riscv_vsra_vx_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i64m1_tum(mask,merge,op1,shift,31);
+}
+
+
+vint64m2_t test___riscv_vsra_vx_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i64m2_tum(mask,merge,op1,shift,31);
+}
+
+
+vint64m4_t test___riscv_vsra_vx_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i64m4_tum(mask,merge,op1,shift,31);
+}
+
+
+vint64m8_t test___riscv_vsra_vx_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i64m8_tum(mask,merge,op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tum-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tum-3.c
new file mode 100644
index 00000000000..f3ec24517e4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tum-3.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsra_vx_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8mf8_tum(mask,merge,op1,shift,32);
+}
+
+
+vint8mf4_t test___riscv_vsra_vx_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8mf4_tum(mask,merge,op1,shift,32);
+}
+
+
+vint8mf2_t test___riscv_vsra_vx_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8mf2_tum(mask,merge,op1,shift,32);
+}
+
+
+vint8m1_t test___riscv_vsra_vx_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8m1_tum(mask,merge,op1,shift,32);
+}
+
+
+vint8m2_t test___riscv_vsra_vx_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8m2_tum(mask,merge,op1,shift,32);
+}
+
+
+vint8m4_t test___riscv_vsra_vx_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8m4_tum(mask,merge,op1,shift,32);
+}
+
+
+vint8m8_t test___riscv_vsra_vx_i8m8_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8m8_tum(mask,merge,op1,shift,32);
+}
+
+
+vint16mf4_t test___riscv_vsra_vx_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16mf4_tum(mask,merge,op1,shift,32);
+}
+
+
+vint16mf2_t test___riscv_vsra_vx_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16mf2_tum(mask,merge,op1,shift,32);
+}
+
+
+vint16m1_t test___riscv_vsra_vx_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16m1_tum(mask,merge,op1,shift,32);
+}
+
+
+vint16m2_t test___riscv_vsra_vx_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16m2_tum(mask,merge,op1,shift,32);
+}
+
+
+vint16m4_t test___riscv_vsra_vx_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16m4_tum(mask,merge,op1,shift,32);
+}
+
+
+vint16m8_t test___riscv_vsra_vx_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16m8_tum(mask,merge,op1,shift,32);
+}
+
+
+vint32mf2_t test___riscv_vsra_vx_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32mf2_tum(mask,merge,op1,shift,32);
+}
+
+
+vint32m1_t test___riscv_vsra_vx_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32m1_tum(mask,merge,op1,shift,32);
+}
+
+
+vint32m2_t test___riscv_vsra_vx_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32m2_tum(mask,merge,op1,shift,32);
+}
+
+
+vint32m4_t test___riscv_vsra_vx_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32m4_tum(mask,merge,op1,shift,32);
+}
+
+
+vint32m8_t test___riscv_vsra_vx_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32m8_tum(mask,merge,op1,shift,32);
+}
+
+
+vint64m1_t test___riscv_vsra_vx_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i64m1_tum(mask,merge,op1,shift,32);
+}
+
+
+vint64m2_t test___riscv_vsra_vx_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i64m2_tum(mask,merge,op1,shift,32);
+}
+
+
+vint64m4_t test___riscv_vsra_vx_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i64m4_tum(mask,merge,op1,shift,32);
+}
+
+
+vint64m8_t test___riscv_vsra_vx_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i64m8_tum(mask,merge,op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tumu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tumu-1.c
new file mode 100644
index 00000000000..d17fa8a8cb9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tumu-1.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsra_vx_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8mf8_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint8mf4_t test___riscv_vsra_vx_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8mf4_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint8mf2_t test___riscv_vsra_vx_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8mf2_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m1_t test___riscv_vsra_vx_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8m1_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m2_t test___riscv_vsra_vx_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8m2_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m4_t test___riscv_vsra_vx_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8m4_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint8m8_t test___riscv_vsra_vx_i8m8_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8m8_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint16mf4_t test___riscv_vsra_vx_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16mf4_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint16mf2_t test___riscv_vsra_vx_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16mf2_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m1_t test___riscv_vsra_vx_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16m1_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m2_t test___riscv_vsra_vx_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16m2_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m4_t test___riscv_vsra_vx_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16m4_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint16m8_t test___riscv_vsra_vx_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16m8_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint32mf2_t test___riscv_vsra_vx_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32mf2_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m1_t test___riscv_vsra_vx_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32m1_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m2_t test___riscv_vsra_vx_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32m2_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m4_t test___riscv_vsra_vx_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32m4_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint32m8_t test___riscv_vsra_vx_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32m8_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint64m1_t test___riscv_vsra_vx_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i64m1_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint64m2_t test___riscv_vsra_vx_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i64m2_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint64m4_t test___riscv_vsra_vx_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i64m4_tumu(mask,merge,op1,shift,vl);
+}
+
+
+vint64m8_t test___riscv_vsra_vx_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i64m8_tumu(mask,merge,op1,shift,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tumu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tumu-2.c
new file mode 100644
index 00000000000..0c3e4e408e5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tumu-2.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsra_vx_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8mf8_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint8mf4_t test___riscv_vsra_vx_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8mf4_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint8mf2_t test___riscv_vsra_vx_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8mf2_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint8m1_t test___riscv_vsra_vx_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8m1_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint8m2_t test___riscv_vsra_vx_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8m2_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint8m4_t test___riscv_vsra_vx_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8m4_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint8m8_t test___riscv_vsra_vx_i8m8_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8m8_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint16mf4_t test___riscv_vsra_vx_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16mf4_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint16mf2_t test___riscv_vsra_vx_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16mf2_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint16m1_t test___riscv_vsra_vx_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16m1_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint16m2_t test___riscv_vsra_vx_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16m2_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint16m4_t test___riscv_vsra_vx_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16m4_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint16m8_t test___riscv_vsra_vx_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16m8_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint32mf2_t test___riscv_vsra_vx_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32mf2_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint32m1_t test___riscv_vsra_vx_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32m1_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint32m2_t test___riscv_vsra_vx_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32m2_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint32m4_t test___riscv_vsra_vx_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32m4_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint32m8_t test___riscv_vsra_vx_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32m8_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint64m1_t test___riscv_vsra_vx_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i64m1_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint64m2_t test___riscv_vsra_vx_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i64m2_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint64m4_t test___riscv_vsra_vx_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i64m4_tumu(mask,merge,op1,shift,31);
+}
+
+
+vint64m8_t test___riscv_vsra_vx_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i64m8_tumu(mask,merge,op1,shift,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tumu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tumu-3.c
new file mode 100644
index 00000000000..8590c65b9f1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsra_vx_tumu-3.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsra_vx_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8mf8_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint8mf4_t test___riscv_vsra_vx_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8mf4_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint8mf2_t test___riscv_vsra_vx_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8mf2_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint8m1_t test___riscv_vsra_vx_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8m1_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint8m2_t test___riscv_vsra_vx_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8m2_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint8m4_t test___riscv_vsra_vx_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8m4_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint8m8_t test___riscv_vsra_vx_i8m8_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i8m8_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint16mf4_t test___riscv_vsra_vx_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16mf4_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint16mf2_t test___riscv_vsra_vx_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16mf2_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint16m1_t test___riscv_vsra_vx_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16m1_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint16m2_t test___riscv_vsra_vx_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16m2_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint16m4_t test___riscv_vsra_vx_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16m4_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint16m8_t test___riscv_vsra_vx_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i16m8_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint32mf2_t test___riscv_vsra_vx_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32mf2_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint32m1_t test___riscv_vsra_vx_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32m1_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint32m2_t test___riscv_vsra_vx_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32m2_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint32m4_t test___riscv_vsra_vx_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32m4_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint32m8_t test___riscv_vsra_vx_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i32m8_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint64m1_t test___riscv_vsra_vx_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i64m1_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint64m2_t test___riscv_vsra_vx_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i64m2_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint64m4_t test___riscv_vsra_vx_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i64m4_tumu(mask,merge,op1,shift,32);
+}
+
+
+vint64m8_t test___riscv_vsra_vx_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t shift,size_t vl)
+{
+    return __riscv_vsra_vx_i64m8_tumu(mask,merge,op1,shift,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vsra\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
-- 
2.36.3