* [PATCH] RISC-V: Add vsub.vx C API tests
@ 2023-02-03 7:06 juzhe.zhong
0 siblings, 0 replies; 2+ messages in thread
From: juzhe.zhong @ 2023-02-03 7:06 UTC (permalink / raw)
To: gcc-patches; +Cc: kito.cheng, Ju-Zhe Zhong
From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vsub_vx_m_rv32-1.c: New test.
* gcc.target/riscv/rvv/base/vsub_vx_m_rv32-2.c: New test.
* gcc.target/riscv/rvv/base/vsub_vx_m_rv32-3.c: New test.
* gcc.target/riscv/rvv/base/vsub_vx_m_rv64-1.c: New test.
* gcc.target/riscv/rvv/base/vsub_vx_m_rv64-2.c: New test.
* gcc.target/riscv/rvv/base/vsub_vx_m_rv64-3.c: New test.
* gcc.target/riscv/rvv/base/vsub_vx_mu_rv32-1.c: New test.
* gcc.target/riscv/rvv/base/vsub_vx_mu_rv32-2.c: New test.
* gcc.target/riscv/rvv/base/vsub_vx_mu_rv32-3.c: New test.
* gcc.target/riscv/rvv/base/vsub_vx_mu_rv64-1.c: New test.
* gcc.target/riscv/rvv/base/vsub_vx_mu_rv64-2.c: New test.
* gcc.target/riscv/rvv/base/vsub_vx_mu_rv64-3.c: New test.
* gcc.target/riscv/rvv/base/vsub_vx_rv32-1.c: New test.
* gcc.target/riscv/rvv/base/vsub_vx_rv32-2.c: New test.
* gcc.target/riscv/rvv/base/vsub_vx_rv32-3.c: New test.
* gcc.target/riscv/rvv/base/vsub_vx_rv64-1.c: New test.
* gcc.target/riscv/rvv/base/vsub_vx_rv64-2.c: New test.
* gcc.target/riscv/rvv/base/vsub_vx_rv64-3.c: New test.
* gcc.target/riscv/rvv/base/vsub_vx_tu_rv32-1.c: New test.
* gcc.target/riscv/rvv/base/vsub_vx_tu_rv32-2.c: New test.
* gcc.target/riscv/rvv/base/vsub_vx_tu_rv32-3.c: New test.
* gcc.target/riscv/rvv/base/vsub_vx_tu_rv64-1.c: New test.
* gcc.target/riscv/rvv/base/vsub_vx_tu_rv64-2.c: New test.
* gcc.target/riscv/rvv/base/vsub_vx_tu_rv64-3.c: New test.
* gcc.target/riscv/rvv/base/vsub_vx_tum_rv32-1.c: New test.
* gcc.target/riscv/rvv/base/vsub_vx_tum_rv32-2.c: New test.
* gcc.target/riscv/rvv/base/vsub_vx_tum_rv32-3.c: New test.
* gcc.target/riscv/rvv/base/vsub_vx_tum_rv64-1.c: New test.
* gcc.target/riscv/rvv/base/vsub_vx_tum_rv64-2.c: New test.
* gcc.target/riscv/rvv/base/vsub_vx_tum_rv64-3.c: New test.
* gcc.target/riscv/rvv/base/vsub_vx_tumu_rv32-1.c: New test.
* gcc.target/riscv/rvv/base/vsub_vx_tumu_rv32-2.c: New test.
* gcc.target/riscv/rvv/base/vsub_vx_tumu_rv32-3.c: New test.
* gcc.target/riscv/rvv/base/vsub_vx_tumu_rv64-1.c: New test.
* gcc.target/riscv/rvv/base/vsub_vx_tumu_rv64-2.c: New test.
* gcc.target/riscv/rvv/base/vsub_vx_tumu_rv64-3.c: New test.
---
.../riscv/rvv/base/vsub_vx_m_rv32-1.c | 289 +++++++++++++++++
.../riscv/rvv/base/vsub_vx_m_rv32-2.c | 289 +++++++++++++++++
.../riscv/rvv/base/vsub_vx_m_rv32-3.c | 289 +++++++++++++++++
.../riscv/rvv/base/vsub_vx_m_rv64-1.c | 292 ++++++++++++++++++
.../riscv/rvv/base/vsub_vx_m_rv64-2.c | 292 ++++++++++++++++++
.../riscv/rvv/base/vsub_vx_m_rv64-3.c | 292 ++++++++++++++++++
.../riscv/rvv/base/vsub_vx_mu_rv32-1.c | 289 +++++++++++++++++
.../riscv/rvv/base/vsub_vx_mu_rv32-2.c | 289 +++++++++++++++++
.../riscv/rvv/base/vsub_vx_mu_rv32-3.c | 289 +++++++++++++++++
.../riscv/rvv/base/vsub_vx_mu_rv64-1.c | 292 ++++++++++++++++++
.../riscv/rvv/base/vsub_vx_mu_rv64-2.c | 292 ++++++++++++++++++
.../riscv/rvv/base/vsub_vx_mu_rv64-3.c | 292 ++++++++++++++++++
.../riscv/rvv/base/vsub_vx_rv32-1.c | 289 +++++++++++++++++
.../riscv/rvv/base/vsub_vx_rv32-2.c | 289 +++++++++++++++++
.../riscv/rvv/base/vsub_vx_rv32-3.c | 289 +++++++++++++++++
.../riscv/rvv/base/vsub_vx_rv64-1.c | 292 ++++++++++++++++++
.../riscv/rvv/base/vsub_vx_rv64-2.c | 292 ++++++++++++++++++
.../riscv/rvv/base/vsub_vx_rv64-3.c | 292 ++++++++++++++++++
.../riscv/rvv/base/vsub_vx_tu_rv32-1.c | 289 +++++++++++++++++
.../riscv/rvv/base/vsub_vx_tu_rv32-2.c | 289 +++++++++++++++++
.../riscv/rvv/base/vsub_vx_tu_rv32-3.c | 289 +++++++++++++++++
.../riscv/rvv/base/vsub_vx_tu_rv64-1.c | 292 ++++++++++++++++++
.../riscv/rvv/base/vsub_vx_tu_rv64-2.c | 292 ++++++++++++++++++
.../riscv/rvv/base/vsub_vx_tu_rv64-3.c | 292 ++++++++++++++++++
.../riscv/rvv/base/vsub_vx_tum_rv32-1.c | 289 +++++++++++++++++
.../riscv/rvv/base/vsub_vx_tum_rv32-2.c | 289 +++++++++++++++++
.../riscv/rvv/base/vsub_vx_tum_rv32-3.c | 289 +++++++++++++++++
.../riscv/rvv/base/vsub_vx_tum_rv64-1.c | 292 ++++++++++++++++++
.../riscv/rvv/base/vsub_vx_tum_rv64-2.c | 292 ++++++++++++++++++
.../riscv/rvv/base/vsub_vx_tum_rv64-3.c | 292 ++++++++++++++++++
.../riscv/rvv/base/vsub_vx_tumu_rv32-1.c | 289 +++++++++++++++++
.../riscv/rvv/base/vsub_vx_tumu_rv32-2.c | 289 +++++++++++++++++
.../riscv/rvv/base/vsub_vx_tumu_rv32-3.c | 289 +++++++++++++++++
.../riscv/rvv/base/vsub_vx_tumu_rv64-1.c | 292 ++++++++++++++++++
.../riscv/rvv/base/vsub_vx_tumu_rv64-2.c | 292 ++++++++++++++++++
.../riscv/rvv/base/vsub_vx_tumu_rv64-3.c | 292 ++++++++++++++++++
36 files changed, 10458 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_m_rv32-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_m_rv32-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_m_rv32-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_m_rv64-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_m_rv64-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_m_rv64-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_mu_rv32-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_mu_rv32-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_mu_rv32-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_mu_rv64-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_mu_rv64-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_mu_rv64-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_rv32-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_rv32-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_rv32-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_rv64-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_rv64-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_rv64-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tu_rv32-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tu_rv32-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tu_rv32-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tu_rv64-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tu_rv64-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tu_rv64-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tum_rv32-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tum_rv32-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tum_rv32-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tum_rv64-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tum_rv64-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tum_rv64-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tumu_rv32-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tumu_rv32-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tumu_rv32-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tumu_rv64-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tumu_rv64-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tumu_rv64-3.c
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_m_rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_m_rv32-1.c
new file mode 100644
index 00000000000..b8ce383ca58
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_m_rv32-1.c
@@ -0,0 +1,289 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsub_vx_i8mf8_m(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf8_m(mask,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vsub_vx_i8mf4_m(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf4_m(mask,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vsub_vx_i8mf2_m(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf2_m(mask,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vsub_vx_i8m1_m(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m1_m(mask,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vsub_vx_i8m2_m(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m2_m(mask,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vsub_vx_i8m4_m(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m4_m(mask,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vsub_vx_i8m8_m(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m8_m(mask,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vsub_vx_i16mf4_m(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16mf4_m(mask,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vsub_vx_i16mf2_m(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16mf2_m(mask,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vsub_vx_i16m1_m(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m1_m(mask,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vsub_vx_i16m2_m(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m2_m(mask,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vsub_vx_i16m4_m(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m4_m(mask,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vsub_vx_i16m8_m(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m8_m(mask,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vsub_vx_i32mf2_m(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32mf2_m(mask,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vsub_vx_i32m1_m(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m1_m(mask,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vsub_vx_i32m2_m(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m2_m(mask,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vsub_vx_i32m4_m(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m4_m(mask,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vsub_vx_i32m8_m(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m8_m(mask,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vsub_vx_i64m1_m(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m1_m(mask,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vsub_vx_i64m2_m(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m2_m(mask,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vsub_vx_i64m4_m(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m4_m(mask,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vsub_vx_i64m8_m(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m8_m(mask,op1,op2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vsub_vx_u8mf8_m(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf8_m(mask,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vsub_vx_u8mf4_m(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf4_m(mask,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vsub_vx_u8mf2_m(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf2_m(mask,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vsub_vx_u8m1_m(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m1_m(mask,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vsub_vx_u8m2_m(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m2_m(mask,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vsub_vx_u8m4_m(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m4_m(mask,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vsub_vx_u8m8_m(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m8_m(mask,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vsub_vx_u16mf4_m(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16mf4_m(mask,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vsub_vx_u16mf2_m(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16mf2_m(mask,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vsub_vx_u16m1_m(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m1_m(mask,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vsub_vx_u16m2_m(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m2_m(mask,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vsub_vx_u16m4_m(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m4_m(mask,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vsub_vx_u16m8_m(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m8_m(mask,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vsub_vx_u32mf2_m(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32mf2_m(mask,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vsub_vx_u32m1_m(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m1_m(mask,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vsub_vx_u32m2_m(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m2_m(mask,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vsub_vx_u32m4_m(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m4_m(mask,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vsub_vx_u32m8_m(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m8_m(mask,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vsub_vx_u64m1_m(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m1_m(mask,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vsub_vx_u64m2_m(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m2_m(mask,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vsub_vx_u64m4_m(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m4_m(mask,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vsub_vx_u64m8_m(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m8_m(mask,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_m_rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_m_rv32-2.c
new file mode 100644
index 00000000000..ad171afac75
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_m_rv32-2.c
@@ -0,0 +1,289 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsub_vx_i8mf8_m(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf8_m(mask,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vsub_vx_i8mf4_m(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf4_m(mask,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vsub_vx_i8mf2_m(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf2_m(mask,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vsub_vx_i8m1_m(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m1_m(mask,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vsub_vx_i8m2_m(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m2_m(mask,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vsub_vx_i8m4_m(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m4_m(mask,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vsub_vx_i8m8_m(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m8_m(mask,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vsub_vx_i16mf4_m(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16mf4_m(mask,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vsub_vx_i16mf2_m(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16mf2_m(mask,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vsub_vx_i16m1_m(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m1_m(mask,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vsub_vx_i16m2_m(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m2_m(mask,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vsub_vx_i16m4_m(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m4_m(mask,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vsub_vx_i16m8_m(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m8_m(mask,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vsub_vx_i32mf2_m(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32mf2_m(mask,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vsub_vx_i32m1_m(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m1_m(mask,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vsub_vx_i32m2_m(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m2_m(mask,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vsub_vx_i32m4_m(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m4_m(mask,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vsub_vx_i32m8_m(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m8_m(mask,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vsub_vx_i64m1_m(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m1_m(mask,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vsub_vx_i64m2_m(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m2_m(mask,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vsub_vx_i64m4_m(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m4_m(mask,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vsub_vx_i64m8_m(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m8_m(mask,op1,op2,31);
+}
+
+
+vuint8mf8_t test___riscv_vsub_vx_u8mf8_m(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf8_m(mask,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vsub_vx_u8mf4_m(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf4_m(mask,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vsub_vx_u8mf2_m(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf2_m(mask,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vsub_vx_u8m1_m(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m1_m(mask,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vsub_vx_u8m2_m(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m2_m(mask,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vsub_vx_u8m4_m(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m4_m(mask,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vsub_vx_u8m8_m(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m8_m(mask,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vsub_vx_u16mf4_m(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16mf4_m(mask,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vsub_vx_u16mf2_m(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16mf2_m(mask,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vsub_vx_u16m1_m(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m1_m(mask,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vsub_vx_u16m2_m(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m2_m(mask,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vsub_vx_u16m4_m(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m4_m(mask,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vsub_vx_u16m8_m(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m8_m(mask,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vsub_vx_u32mf2_m(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32mf2_m(mask,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vsub_vx_u32m1_m(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m1_m(mask,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vsub_vx_u32m2_m(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m2_m(mask,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vsub_vx_u32m4_m(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m4_m(mask,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vsub_vx_u32m8_m(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m8_m(mask,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vsub_vx_u64m1_m(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m1_m(mask,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vsub_vx_u64m2_m(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m2_m(mask,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vsub_vx_u64m4_m(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m4_m(mask,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vsub_vx_u64m8_m(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m8_m(mask,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_m_rv32-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_m_rv32-3.c
new file mode 100644
index 00000000000..ae60e4e4d65
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_m_rv32-3.c
@@ -0,0 +1,289 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsub_vx_i8mf8_m(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf8_m(mask,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vsub_vx_i8mf4_m(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf4_m(mask,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vsub_vx_i8mf2_m(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf2_m(mask,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vsub_vx_i8m1_m(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m1_m(mask,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vsub_vx_i8m2_m(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m2_m(mask,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vsub_vx_i8m4_m(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m4_m(mask,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vsub_vx_i8m8_m(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m8_m(mask,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vsub_vx_i16mf4_m(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16mf4_m(mask,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vsub_vx_i16mf2_m(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16mf2_m(mask,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vsub_vx_i16m1_m(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m1_m(mask,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vsub_vx_i16m2_m(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m2_m(mask,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vsub_vx_i16m4_m(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m4_m(mask,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vsub_vx_i16m8_m(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m8_m(mask,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vsub_vx_i32mf2_m(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32mf2_m(mask,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vsub_vx_i32m1_m(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m1_m(mask,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vsub_vx_i32m2_m(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m2_m(mask,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vsub_vx_i32m4_m(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m4_m(mask,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vsub_vx_i32m8_m(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m8_m(mask,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vsub_vx_i64m1_m(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m1_m(mask,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vsub_vx_i64m2_m(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m2_m(mask,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vsub_vx_i64m4_m(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m4_m(mask,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vsub_vx_i64m8_m(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m8_m(mask,op1,op2,32);
+}
+
+
+vuint8mf8_t test___riscv_vsub_vx_u8mf8_m(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf8_m(mask,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vsub_vx_u8mf4_m(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf4_m(mask,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vsub_vx_u8mf2_m(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf2_m(mask,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vsub_vx_u8m1_m(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m1_m(mask,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vsub_vx_u8m2_m(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m2_m(mask,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vsub_vx_u8m4_m(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m4_m(mask,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vsub_vx_u8m8_m(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m8_m(mask,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vsub_vx_u16mf4_m(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16mf4_m(mask,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vsub_vx_u16mf2_m(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16mf2_m(mask,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vsub_vx_u16m1_m(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m1_m(mask,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vsub_vx_u16m2_m(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m2_m(mask,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vsub_vx_u16m4_m(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m4_m(mask,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vsub_vx_u16m8_m(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m8_m(mask,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vsub_vx_u32mf2_m(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32mf2_m(mask,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vsub_vx_u32m1_m(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m1_m(mask,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vsub_vx_u32m2_m(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m2_m(mask,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vsub_vx_u32m4_m(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m4_m(mask,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vsub_vx_u32m8_m(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m8_m(mask,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vsub_vx_u64m1_m(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m1_m(mask,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vsub_vx_u64m2_m(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m2_m(mask,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vsub_vx_u64m4_m(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m4_m(mask,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vsub_vx_u64m8_m(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m8_m(mask,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_m_rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_m_rv64-1.c
new file mode 100644
index 00000000000..aa63b1ef4e6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_m_rv64-1.c
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsub_vx_i8mf8_m(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf8_m(mask,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vsub_vx_i8mf4_m(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf4_m(mask,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vsub_vx_i8mf2_m(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf2_m(mask,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vsub_vx_i8m1_m(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m1_m(mask,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vsub_vx_i8m2_m(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m2_m(mask,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vsub_vx_i8m4_m(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m4_m(mask,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vsub_vx_i8m8_m(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m8_m(mask,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vsub_vx_i16mf4_m(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16mf4_m(mask,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vsub_vx_i16mf2_m(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16mf2_m(mask,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vsub_vx_i16m1_m(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m1_m(mask,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vsub_vx_i16m2_m(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m2_m(mask,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vsub_vx_i16m4_m(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m4_m(mask,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vsub_vx_i16m8_m(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m8_m(mask,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vsub_vx_i32mf2_m(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32mf2_m(mask,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vsub_vx_i32m1_m(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m1_m(mask,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vsub_vx_i32m2_m(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m2_m(mask,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vsub_vx_i32m4_m(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m4_m(mask,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vsub_vx_i32m8_m(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m8_m(mask,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vsub_vx_i64m1_m(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m1_m(mask,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vsub_vx_i64m2_m(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m2_m(mask,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vsub_vx_i64m4_m(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m4_m(mask,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vsub_vx_i64m8_m(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m8_m(mask,op1,op2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vsub_vx_u8mf8_m(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf8_m(mask,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vsub_vx_u8mf4_m(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf4_m(mask,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vsub_vx_u8mf2_m(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf2_m(mask,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vsub_vx_u8m1_m(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m1_m(mask,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vsub_vx_u8m2_m(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m2_m(mask,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vsub_vx_u8m4_m(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m4_m(mask,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vsub_vx_u8m8_m(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m8_m(mask,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vsub_vx_u16mf4_m(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16mf4_m(mask,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vsub_vx_u16mf2_m(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16mf2_m(mask,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vsub_vx_u16m1_m(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m1_m(mask,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vsub_vx_u16m2_m(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m2_m(mask,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vsub_vx_u16m4_m(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m4_m(mask,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vsub_vx_u16m8_m(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m8_m(mask,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vsub_vx_u32mf2_m(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32mf2_m(mask,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vsub_vx_u32m1_m(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m1_m(mask,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vsub_vx_u32m2_m(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m2_m(mask,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vsub_vx_u32m4_m(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m4_m(mask,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vsub_vx_u32m8_m(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m8_m(mask,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vsub_vx_u64m1_m(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m1_m(mask,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vsub_vx_u64m2_m(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m2_m(mask,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vsub_vx_u64m4_m(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m4_m(mask,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vsub_vx_u64m8_m(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m8_m(mask,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_m_rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_m_rv64-2.c
new file mode 100644
index 00000000000..ad1f95b5411
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_m_rv64-2.c
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsub_vx_i8mf8_m(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf8_m(mask,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vsub_vx_i8mf4_m(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf4_m(mask,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vsub_vx_i8mf2_m(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf2_m(mask,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vsub_vx_i8m1_m(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m1_m(mask,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vsub_vx_i8m2_m(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m2_m(mask,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vsub_vx_i8m4_m(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m4_m(mask,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vsub_vx_i8m8_m(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m8_m(mask,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vsub_vx_i16mf4_m(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16mf4_m(mask,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vsub_vx_i16mf2_m(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16mf2_m(mask,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vsub_vx_i16m1_m(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m1_m(mask,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vsub_vx_i16m2_m(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m2_m(mask,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vsub_vx_i16m4_m(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m4_m(mask,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vsub_vx_i16m8_m(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m8_m(mask,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vsub_vx_i32mf2_m(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32mf2_m(mask,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vsub_vx_i32m1_m(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m1_m(mask,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vsub_vx_i32m2_m(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m2_m(mask,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vsub_vx_i32m4_m(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m4_m(mask,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vsub_vx_i32m8_m(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m8_m(mask,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vsub_vx_i64m1_m(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m1_m(mask,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vsub_vx_i64m2_m(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m2_m(mask,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vsub_vx_i64m4_m(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m4_m(mask,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vsub_vx_i64m8_m(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m8_m(mask,op1,op2,31);
+}
+
+
+vuint8mf8_t test___riscv_vsub_vx_u8mf8_m(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf8_m(mask,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vsub_vx_u8mf4_m(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf4_m(mask,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vsub_vx_u8mf2_m(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf2_m(mask,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vsub_vx_u8m1_m(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m1_m(mask,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vsub_vx_u8m2_m(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m2_m(mask,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vsub_vx_u8m4_m(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m4_m(mask,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vsub_vx_u8m8_m(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m8_m(mask,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vsub_vx_u16mf4_m(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16mf4_m(mask,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vsub_vx_u16mf2_m(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16mf2_m(mask,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vsub_vx_u16m1_m(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m1_m(mask,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vsub_vx_u16m2_m(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m2_m(mask,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vsub_vx_u16m4_m(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m4_m(mask,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vsub_vx_u16m8_m(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m8_m(mask,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vsub_vx_u32mf2_m(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32mf2_m(mask,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vsub_vx_u32m1_m(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m1_m(mask,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vsub_vx_u32m2_m(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m2_m(mask,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vsub_vx_u32m4_m(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m4_m(mask,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vsub_vx_u32m8_m(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m8_m(mask,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vsub_vx_u64m1_m(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m1_m(mask,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vsub_vx_u64m2_m(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m2_m(mask,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vsub_vx_u64m4_m(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m4_m(mask,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vsub_vx_u64m8_m(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m8_m(mask,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_m_rv64-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_m_rv64-3.c
new file mode 100644
index 00000000000..8810b056880
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_m_rv64-3.c
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsub_vx_i8mf8_m(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf8_m(mask,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vsub_vx_i8mf4_m(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf4_m(mask,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vsub_vx_i8mf2_m(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf2_m(mask,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vsub_vx_i8m1_m(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m1_m(mask,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vsub_vx_i8m2_m(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m2_m(mask,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vsub_vx_i8m4_m(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m4_m(mask,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vsub_vx_i8m8_m(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m8_m(mask,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vsub_vx_i16mf4_m(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16mf4_m(mask,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vsub_vx_i16mf2_m(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16mf2_m(mask,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vsub_vx_i16m1_m(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m1_m(mask,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vsub_vx_i16m2_m(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m2_m(mask,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vsub_vx_i16m4_m(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m4_m(mask,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vsub_vx_i16m8_m(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m8_m(mask,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vsub_vx_i32mf2_m(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32mf2_m(mask,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vsub_vx_i32m1_m(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m1_m(mask,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vsub_vx_i32m2_m(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m2_m(mask,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vsub_vx_i32m4_m(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m4_m(mask,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vsub_vx_i32m8_m(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m8_m(mask,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vsub_vx_i64m1_m(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m1_m(mask,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vsub_vx_i64m2_m(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m2_m(mask,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vsub_vx_i64m4_m(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m4_m(mask,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vsub_vx_i64m8_m(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m8_m(mask,op1,op2,32);
+}
+
+
+vuint8mf8_t test___riscv_vsub_vx_u8mf8_m(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf8_m(mask,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vsub_vx_u8mf4_m(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf4_m(mask,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vsub_vx_u8mf2_m(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf2_m(mask,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vsub_vx_u8m1_m(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m1_m(mask,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vsub_vx_u8m2_m(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m2_m(mask,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vsub_vx_u8m4_m(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m4_m(mask,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vsub_vx_u8m8_m(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m8_m(mask,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vsub_vx_u16mf4_m(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16mf4_m(mask,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vsub_vx_u16mf2_m(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16mf2_m(mask,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vsub_vx_u16m1_m(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m1_m(mask,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vsub_vx_u16m2_m(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m2_m(mask,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vsub_vx_u16m4_m(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m4_m(mask,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vsub_vx_u16m8_m(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m8_m(mask,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vsub_vx_u32mf2_m(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32mf2_m(mask,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vsub_vx_u32m1_m(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m1_m(mask,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vsub_vx_u32m2_m(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m2_m(mask,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vsub_vx_u32m4_m(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m4_m(mask,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vsub_vx_u32m8_m(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m8_m(mask,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vsub_vx_u64m1_m(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m1_m(mask,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vsub_vx_u64m2_m(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m2_m(mask,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vsub_vx_u64m4_m(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m4_m(mask,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vsub_vx_u64m8_m(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m8_m(mask,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_mu_rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_mu_rv32-1.c
new file mode 100644
index 00000000000..eac64f619ad
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_mu_rv32-1.c
@@ -0,0 +1,289 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsub_vx_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vsub_vx_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vsub_vx_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vsub_vx_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m1_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vsub_vx_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vsub_vx_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vsub_vx_i8m8_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vsub_vx_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16mf4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vsub_vx_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16mf2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vsub_vx_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m1_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vsub_vx_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vsub_vx_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vsub_vx_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vsub_vx_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32mf2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vsub_vx_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m1_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vsub_vx_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vsub_vx_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vsub_vx_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vsub_vx_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m1_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vsub_vx_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vsub_vx_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vsub_vx_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vsub_vx_u8mf8_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vsub_vx_u8mf4_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vsub_vx_u8mf2_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vsub_vx_u8m1_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m1_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vsub_vx_u8m2_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vsub_vx_u8m4_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vsub_vx_u8m8_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vsub_vx_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16mf4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vsub_vx_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16mf2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vsub_vx_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m1_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vsub_vx_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vsub_vx_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vsub_vx_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vsub_vx_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32mf2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vsub_vx_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m1_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vsub_vx_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vsub_vx_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vsub_vx_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vsub_vx_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m1_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vsub_vx_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vsub_vx_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vsub_vx_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m8_mu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_mu_rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_mu_rv32-2.c
new file mode 100644
index 00000000000..ca42ca80ba7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_mu_rv32-2.c
@@ -0,0 +1,289 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsub_vx_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf8_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vsub_vx_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf4_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vsub_vx_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf2_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vsub_vx_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m1_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vsub_vx_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m2_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vsub_vx_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m4_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vsub_vx_i8m8_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m8_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vsub_vx_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16mf4_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vsub_vx_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16mf2_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vsub_vx_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m1_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vsub_vx_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m2_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vsub_vx_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m4_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vsub_vx_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m8_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vsub_vx_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32mf2_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vsub_vx_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m1_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vsub_vx_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m2_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vsub_vx_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m4_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vsub_vx_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m8_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vsub_vx_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m1_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vsub_vx_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m2_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vsub_vx_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m4_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vsub_vx_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m8_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf8_t test___riscv_vsub_vx_u8mf8_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf8_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vsub_vx_u8mf4_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf4_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vsub_vx_u8mf2_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf2_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vsub_vx_u8m1_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m1_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vsub_vx_u8m2_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m2_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vsub_vx_u8m4_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m4_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vsub_vx_u8m8_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m8_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vsub_vx_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16mf4_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vsub_vx_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16mf2_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vsub_vx_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m1_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vsub_vx_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m2_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vsub_vx_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m4_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vsub_vx_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m8_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vsub_vx_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32mf2_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vsub_vx_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m1_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vsub_vx_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m2_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vsub_vx_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m4_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vsub_vx_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m8_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vsub_vx_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m1_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vsub_vx_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m2_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vsub_vx_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m4_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vsub_vx_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m8_mu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_mu_rv32-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_mu_rv32-3.c
new file mode 100644
index 00000000000..ce8a503379d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_mu_rv32-3.c
@@ -0,0 +1,289 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsub_vx_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf8_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vsub_vx_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf4_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vsub_vx_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf2_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vsub_vx_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m1_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vsub_vx_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m2_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vsub_vx_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m4_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vsub_vx_i8m8_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m8_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vsub_vx_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16mf4_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vsub_vx_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16mf2_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vsub_vx_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m1_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vsub_vx_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m2_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vsub_vx_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m4_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vsub_vx_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m8_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vsub_vx_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32mf2_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vsub_vx_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m1_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vsub_vx_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m2_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vsub_vx_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m4_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vsub_vx_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m8_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vsub_vx_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m1_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vsub_vx_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m2_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vsub_vx_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m4_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vsub_vx_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m8_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf8_t test___riscv_vsub_vx_u8mf8_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf8_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vsub_vx_u8mf4_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf4_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vsub_vx_u8mf2_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf2_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vsub_vx_u8m1_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m1_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vsub_vx_u8m2_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m2_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vsub_vx_u8m4_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m4_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vsub_vx_u8m8_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m8_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vsub_vx_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16mf4_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vsub_vx_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16mf2_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vsub_vx_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m1_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vsub_vx_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m2_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vsub_vx_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m4_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vsub_vx_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m8_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vsub_vx_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32mf2_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vsub_vx_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m1_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vsub_vx_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m2_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vsub_vx_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m4_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vsub_vx_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m8_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vsub_vx_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m1_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vsub_vx_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m2_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vsub_vx_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m4_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vsub_vx_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m8_mu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_mu_rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_mu_rv64-1.c
new file mode 100644
index 00000000000..7776d305b8d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_mu_rv64-1.c
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsub_vx_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vsub_vx_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vsub_vx_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vsub_vx_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m1_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vsub_vx_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vsub_vx_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vsub_vx_i8m8_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vsub_vx_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16mf4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vsub_vx_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16mf2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vsub_vx_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m1_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vsub_vx_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vsub_vx_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vsub_vx_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vsub_vx_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32mf2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vsub_vx_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m1_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vsub_vx_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vsub_vx_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vsub_vx_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vsub_vx_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m1_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vsub_vx_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vsub_vx_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vsub_vx_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vsub_vx_u8mf8_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vsub_vx_u8mf4_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vsub_vx_u8mf2_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vsub_vx_u8m1_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m1_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vsub_vx_u8m2_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vsub_vx_u8m4_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vsub_vx_u8m8_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vsub_vx_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16mf4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vsub_vx_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16mf2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vsub_vx_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m1_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vsub_vx_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vsub_vx_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vsub_vx_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vsub_vx_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32mf2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vsub_vx_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m1_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vsub_vx_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vsub_vx_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vsub_vx_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vsub_vx_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m1_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vsub_vx_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vsub_vx_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vsub_vx_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m8_mu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_mu_rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_mu_rv64-2.c
new file mode 100644
index 00000000000..faa8d5a8c60
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_mu_rv64-2.c
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsub_vx_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf8_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vsub_vx_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf4_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vsub_vx_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf2_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vsub_vx_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m1_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vsub_vx_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m2_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vsub_vx_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m4_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vsub_vx_i8m8_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m8_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vsub_vx_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16mf4_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vsub_vx_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16mf2_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vsub_vx_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m1_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vsub_vx_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m2_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vsub_vx_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m4_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vsub_vx_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m8_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vsub_vx_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32mf2_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vsub_vx_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m1_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vsub_vx_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m2_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vsub_vx_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m4_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vsub_vx_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m8_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vsub_vx_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m1_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vsub_vx_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m2_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vsub_vx_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m4_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vsub_vx_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m8_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf8_t test___riscv_vsub_vx_u8mf8_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf8_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vsub_vx_u8mf4_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf4_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vsub_vx_u8mf2_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf2_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vsub_vx_u8m1_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m1_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vsub_vx_u8m2_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m2_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vsub_vx_u8m4_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m4_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vsub_vx_u8m8_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m8_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vsub_vx_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16mf4_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vsub_vx_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16mf2_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vsub_vx_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m1_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vsub_vx_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m2_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vsub_vx_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m4_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vsub_vx_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m8_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vsub_vx_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32mf2_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vsub_vx_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m1_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vsub_vx_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m2_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vsub_vx_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m4_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vsub_vx_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m8_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vsub_vx_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m1_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vsub_vx_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m2_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vsub_vx_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m4_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vsub_vx_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m8_mu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_mu_rv64-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_mu_rv64-3.c
new file mode 100644
index 00000000000..525bf626b82
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_mu_rv64-3.c
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsub_vx_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf8_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vsub_vx_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf4_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vsub_vx_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf2_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vsub_vx_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m1_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vsub_vx_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m2_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vsub_vx_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m4_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vsub_vx_i8m8_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m8_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vsub_vx_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16mf4_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vsub_vx_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16mf2_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vsub_vx_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m1_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vsub_vx_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m2_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vsub_vx_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m4_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vsub_vx_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m8_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vsub_vx_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32mf2_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vsub_vx_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m1_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vsub_vx_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m2_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vsub_vx_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m4_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vsub_vx_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m8_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vsub_vx_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m1_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vsub_vx_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m2_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vsub_vx_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m4_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vsub_vx_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m8_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf8_t test___riscv_vsub_vx_u8mf8_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf8_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vsub_vx_u8mf4_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf4_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vsub_vx_u8mf2_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf2_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vsub_vx_u8m1_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m1_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vsub_vx_u8m2_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m2_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vsub_vx_u8m4_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m4_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vsub_vx_u8m8_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m8_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vsub_vx_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16mf4_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vsub_vx_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16mf2_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vsub_vx_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m1_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vsub_vx_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m2_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vsub_vx_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m4_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vsub_vx_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m8_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vsub_vx_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32mf2_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vsub_vx_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m1_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vsub_vx_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m2_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vsub_vx_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m4_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vsub_vx_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m8_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vsub_vx_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m1_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vsub_vx_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m2_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vsub_vx_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m4_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vsub_vx_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m8_mu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_rv32-1.c
new file mode 100644
index 00000000000..1d43c6417ba
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_rv32-1.c
@@ -0,0 +1,289 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsub_vx_i8mf8(vint8mf8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf8(op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vsub_vx_i8mf4(vint8mf4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf4(op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vsub_vx_i8mf2(vint8mf2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf2(op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vsub_vx_i8m1(vint8m1_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m1(op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vsub_vx_i8m2(vint8m2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m2(op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vsub_vx_i8m4(vint8m4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m4(op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vsub_vx_i8m8(vint8m8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m8(op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vsub_vx_i16mf4(vint16mf4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16mf4(op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vsub_vx_i16mf2(vint16mf2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16mf2(op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vsub_vx_i16m1(vint16m1_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m1(op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vsub_vx_i16m2(vint16m2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m2(op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vsub_vx_i16m4(vint16m4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m4(op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vsub_vx_i16m8(vint16m8_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m8(op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vsub_vx_i32mf2(vint32mf2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32mf2(op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vsub_vx_i32m1(vint32m1_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m1(op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vsub_vx_i32m2(vint32m2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m2(op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vsub_vx_i32m4(vint32m4_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m4(op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vsub_vx_i32m8(vint32m8_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m8(op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vsub_vx_i64m1(vint64m1_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m1(op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vsub_vx_i64m2(vint64m2_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m2(op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vsub_vx_i64m4(vint64m4_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m4(op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vsub_vx_i64m8(vint64m8_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m8(op1,op2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vsub_vx_u8mf8(vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf8(op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vsub_vx_u8mf4(vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf4(op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vsub_vx_u8mf2(vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf2(op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vsub_vx_u8m1(vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m1(op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vsub_vx_u8m2(vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m2(op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vsub_vx_u8m4(vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m4(op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vsub_vx_u8m8(vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m8(op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vsub_vx_u16mf4(vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16mf4(op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vsub_vx_u16mf2(vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16mf2(op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vsub_vx_u16m1(vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m1(op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vsub_vx_u16m2(vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m2(op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vsub_vx_u16m4(vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m4(op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vsub_vx_u16m8(vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m8(op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vsub_vx_u32mf2(vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32mf2(op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vsub_vx_u32m1(vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m1(op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vsub_vx_u32m2(vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m2(op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vsub_vx_u32m4(vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m4(op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vsub_vx_u32m8(vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m8(op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vsub_vx_u64m1(vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m1(op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vsub_vx_u64m2(vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m2(op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vsub_vx_u64m4(vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m4(op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vsub_vx_u64m8(vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m8(op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_rv32-2.c
new file mode 100644
index 00000000000..1c76bb03d1d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_rv32-2.c
@@ -0,0 +1,289 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsub_vx_i8mf8(vint8mf8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf8(op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vsub_vx_i8mf4(vint8mf4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf4(op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vsub_vx_i8mf2(vint8mf2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf2(op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vsub_vx_i8m1(vint8m1_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m1(op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vsub_vx_i8m2(vint8m2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m2(op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vsub_vx_i8m4(vint8m4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m4(op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vsub_vx_i8m8(vint8m8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m8(op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vsub_vx_i16mf4(vint16mf4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16mf4(op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vsub_vx_i16mf2(vint16mf2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16mf2(op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vsub_vx_i16m1(vint16m1_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m1(op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vsub_vx_i16m2(vint16m2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m2(op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vsub_vx_i16m4(vint16m4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m4(op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vsub_vx_i16m8(vint16m8_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m8(op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vsub_vx_i32mf2(vint32mf2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32mf2(op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vsub_vx_i32m1(vint32m1_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m1(op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vsub_vx_i32m2(vint32m2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m2(op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vsub_vx_i32m4(vint32m4_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m4(op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vsub_vx_i32m8(vint32m8_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m8(op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vsub_vx_i64m1(vint64m1_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m1(op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vsub_vx_i64m2(vint64m2_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m2(op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vsub_vx_i64m4(vint64m4_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m4(op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vsub_vx_i64m8(vint64m8_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m8(op1,op2,31);
+}
+
+
+vuint8mf8_t test___riscv_vsub_vx_u8mf8(vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf8(op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vsub_vx_u8mf4(vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf4(op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vsub_vx_u8mf2(vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf2(op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vsub_vx_u8m1(vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m1(op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vsub_vx_u8m2(vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m2(op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vsub_vx_u8m4(vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m4(op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vsub_vx_u8m8(vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m8(op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vsub_vx_u16mf4(vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16mf4(op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vsub_vx_u16mf2(vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16mf2(op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vsub_vx_u16m1(vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m1(op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vsub_vx_u16m2(vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m2(op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vsub_vx_u16m4(vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m4(op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vsub_vx_u16m8(vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m8(op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vsub_vx_u32mf2(vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32mf2(op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vsub_vx_u32m1(vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m1(op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vsub_vx_u32m2(vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m2(op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vsub_vx_u32m4(vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m4(op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vsub_vx_u32m8(vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m8(op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vsub_vx_u64m1(vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m1(op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vsub_vx_u64m2(vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m2(op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vsub_vx_u64m4(vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m4(op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vsub_vx_u64m8(vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m8(op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_rv32-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_rv32-3.c
new file mode 100644
index 00000000000..2ed5d8e77df
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_rv32-3.c
@@ -0,0 +1,289 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsub_vx_i8mf8(vint8mf8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf8(op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vsub_vx_i8mf4(vint8mf4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf4(op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vsub_vx_i8mf2(vint8mf2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf2(op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vsub_vx_i8m1(vint8m1_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m1(op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vsub_vx_i8m2(vint8m2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m2(op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vsub_vx_i8m4(vint8m4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m4(op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vsub_vx_i8m8(vint8m8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m8(op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vsub_vx_i16mf4(vint16mf4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16mf4(op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vsub_vx_i16mf2(vint16mf2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16mf2(op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vsub_vx_i16m1(vint16m1_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m1(op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vsub_vx_i16m2(vint16m2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m2(op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vsub_vx_i16m4(vint16m4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m4(op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vsub_vx_i16m8(vint16m8_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m8(op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vsub_vx_i32mf2(vint32mf2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32mf2(op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vsub_vx_i32m1(vint32m1_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m1(op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vsub_vx_i32m2(vint32m2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m2(op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vsub_vx_i32m4(vint32m4_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m4(op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vsub_vx_i32m8(vint32m8_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m8(op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vsub_vx_i64m1(vint64m1_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m1(op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vsub_vx_i64m2(vint64m2_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m2(op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vsub_vx_i64m4(vint64m4_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m4(op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vsub_vx_i64m8(vint64m8_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m8(op1,op2,32);
+}
+
+
+vuint8mf8_t test___riscv_vsub_vx_u8mf8(vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf8(op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vsub_vx_u8mf4(vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf4(op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vsub_vx_u8mf2(vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf2(op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vsub_vx_u8m1(vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m1(op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vsub_vx_u8m2(vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m2(op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vsub_vx_u8m4(vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m4(op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vsub_vx_u8m8(vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m8(op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vsub_vx_u16mf4(vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16mf4(op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vsub_vx_u16mf2(vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16mf2(op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vsub_vx_u16m1(vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m1(op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vsub_vx_u16m2(vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m2(op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vsub_vx_u16m4(vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m4(op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vsub_vx_u16m8(vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m8(op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vsub_vx_u32mf2(vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32mf2(op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vsub_vx_u32m1(vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m1(op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vsub_vx_u32m2(vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m2(op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vsub_vx_u32m4(vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m4(op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vsub_vx_u32m8(vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m8(op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vsub_vx_u64m1(vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m1(op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vsub_vx_u64m2(vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m2(op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vsub_vx_u64m4(vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m4(op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vsub_vx_u64m8(vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m8(op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_rv64-1.c
new file mode 100644
index 00000000000..2c5124a472e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_rv64-1.c
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsub_vx_i8mf8(vint8mf8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf8(op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vsub_vx_i8mf4(vint8mf4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf4(op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vsub_vx_i8mf2(vint8mf2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf2(op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vsub_vx_i8m1(vint8m1_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m1(op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vsub_vx_i8m2(vint8m2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m2(op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vsub_vx_i8m4(vint8m4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m4(op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vsub_vx_i8m8(vint8m8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m8(op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vsub_vx_i16mf4(vint16mf4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16mf4(op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vsub_vx_i16mf2(vint16mf2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16mf2(op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vsub_vx_i16m1(vint16m1_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m1(op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vsub_vx_i16m2(vint16m2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m2(op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vsub_vx_i16m4(vint16m4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m4(op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vsub_vx_i16m8(vint16m8_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m8(op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vsub_vx_i32mf2(vint32mf2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32mf2(op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vsub_vx_i32m1(vint32m1_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m1(op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vsub_vx_i32m2(vint32m2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m2(op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vsub_vx_i32m4(vint32m4_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m4(op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vsub_vx_i32m8(vint32m8_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m8(op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vsub_vx_i64m1(vint64m1_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m1(op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vsub_vx_i64m2(vint64m2_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m2(op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vsub_vx_i64m4(vint64m4_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m4(op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vsub_vx_i64m8(vint64m8_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m8(op1,op2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vsub_vx_u8mf8(vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf8(op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vsub_vx_u8mf4(vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf4(op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vsub_vx_u8mf2(vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf2(op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vsub_vx_u8m1(vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m1(op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vsub_vx_u8m2(vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m2(op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vsub_vx_u8m4(vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m4(op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vsub_vx_u8m8(vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m8(op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vsub_vx_u16mf4(vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16mf4(op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vsub_vx_u16mf2(vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16mf2(op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vsub_vx_u16m1(vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m1(op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vsub_vx_u16m2(vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m2(op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vsub_vx_u16m4(vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m4(op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vsub_vx_u16m8(vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m8(op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vsub_vx_u32mf2(vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32mf2(op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vsub_vx_u32m1(vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m1(op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vsub_vx_u32m2(vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m2(op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vsub_vx_u32m4(vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m4(op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vsub_vx_u32m8(vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m8(op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vsub_vx_u64m1(vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m1(op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vsub_vx_u64m2(vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m2(op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vsub_vx_u64m4(vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m4(op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vsub_vx_u64m8(vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m8(op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_rv64-2.c
new file mode 100644
index 00000000000..c71f62aed59
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_rv64-2.c
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsub_vx_i8mf8(vint8mf8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf8(op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vsub_vx_i8mf4(vint8mf4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf4(op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vsub_vx_i8mf2(vint8mf2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf2(op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vsub_vx_i8m1(vint8m1_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m1(op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vsub_vx_i8m2(vint8m2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m2(op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vsub_vx_i8m4(vint8m4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m4(op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vsub_vx_i8m8(vint8m8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m8(op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vsub_vx_i16mf4(vint16mf4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16mf4(op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vsub_vx_i16mf2(vint16mf2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16mf2(op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vsub_vx_i16m1(vint16m1_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m1(op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vsub_vx_i16m2(vint16m2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m2(op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vsub_vx_i16m4(vint16m4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m4(op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vsub_vx_i16m8(vint16m8_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m8(op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vsub_vx_i32mf2(vint32mf2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32mf2(op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vsub_vx_i32m1(vint32m1_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m1(op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vsub_vx_i32m2(vint32m2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m2(op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vsub_vx_i32m4(vint32m4_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m4(op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vsub_vx_i32m8(vint32m8_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m8(op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vsub_vx_i64m1(vint64m1_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m1(op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vsub_vx_i64m2(vint64m2_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m2(op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vsub_vx_i64m4(vint64m4_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m4(op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vsub_vx_i64m8(vint64m8_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m8(op1,op2,31);
+}
+
+
+vuint8mf8_t test___riscv_vsub_vx_u8mf8(vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf8(op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vsub_vx_u8mf4(vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf4(op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vsub_vx_u8mf2(vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf2(op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vsub_vx_u8m1(vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m1(op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vsub_vx_u8m2(vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m2(op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vsub_vx_u8m4(vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m4(op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vsub_vx_u8m8(vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m8(op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vsub_vx_u16mf4(vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16mf4(op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vsub_vx_u16mf2(vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16mf2(op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vsub_vx_u16m1(vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m1(op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vsub_vx_u16m2(vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m2(op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vsub_vx_u16m4(vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m4(op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vsub_vx_u16m8(vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m8(op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vsub_vx_u32mf2(vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32mf2(op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vsub_vx_u32m1(vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m1(op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vsub_vx_u32m2(vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m2(op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vsub_vx_u32m4(vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m4(op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vsub_vx_u32m8(vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m8(op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vsub_vx_u64m1(vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m1(op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vsub_vx_u64m2(vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m2(op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vsub_vx_u64m4(vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m4(op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vsub_vx_u64m8(vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m8(op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_rv64-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_rv64-3.c
new file mode 100644
index 00000000000..0851b2d685e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_rv64-3.c
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsub_vx_i8mf8(vint8mf8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf8(op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vsub_vx_i8mf4(vint8mf4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf4(op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vsub_vx_i8mf2(vint8mf2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf2(op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vsub_vx_i8m1(vint8m1_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m1(op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vsub_vx_i8m2(vint8m2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m2(op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vsub_vx_i8m4(vint8m4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m4(op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vsub_vx_i8m8(vint8m8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m8(op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vsub_vx_i16mf4(vint16mf4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16mf4(op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vsub_vx_i16mf2(vint16mf2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16mf2(op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vsub_vx_i16m1(vint16m1_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m1(op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vsub_vx_i16m2(vint16m2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m2(op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vsub_vx_i16m4(vint16m4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m4(op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vsub_vx_i16m8(vint16m8_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m8(op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vsub_vx_i32mf2(vint32mf2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32mf2(op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vsub_vx_i32m1(vint32m1_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m1(op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vsub_vx_i32m2(vint32m2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m2(op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vsub_vx_i32m4(vint32m4_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m4(op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vsub_vx_i32m8(vint32m8_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m8(op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vsub_vx_i64m1(vint64m1_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m1(op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vsub_vx_i64m2(vint64m2_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m2(op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vsub_vx_i64m4(vint64m4_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m4(op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vsub_vx_i64m8(vint64m8_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m8(op1,op2,32);
+}
+
+
+vuint8mf8_t test___riscv_vsub_vx_u8mf8(vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf8(op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vsub_vx_u8mf4(vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf4(op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vsub_vx_u8mf2(vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf2(op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vsub_vx_u8m1(vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m1(op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vsub_vx_u8m2(vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m2(op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vsub_vx_u8m4(vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m4(op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vsub_vx_u8m8(vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m8(op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vsub_vx_u16mf4(vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16mf4(op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vsub_vx_u16mf2(vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16mf2(op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vsub_vx_u16m1(vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m1(op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vsub_vx_u16m2(vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m2(op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vsub_vx_u16m4(vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m4(op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vsub_vx_u16m8(vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m8(op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vsub_vx_u32mf2(vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32mf2(op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vsub_vx_u32m1(vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m1(op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vsub_vx_u32m2(vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m2(op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vsub_vx_u32m4(vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m4(op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vsub_vx_u32m8(vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m8(op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vsub_vx_u64m1(vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m1(op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vsub_vx_u64m2(vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m2(op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vsub_vx_u64m4(vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m4(op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vsub_vx_u64m8(vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m8(op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tu_rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tu_rv32-1.c
new file mode 100644
index 00000000000..6ab58f9abb6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tu_rv32-1.c
@@ -0,0 +1,289 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsub_vx_i8mf8_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf8_tu(merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vsub_vx_i8mf4_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf4_tu(merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vsub_vx_i8mf2_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf2_tu(merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vsub_vx_i8m1_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m1_tu(merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vsub_vx_i8m2_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m2_tu(merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vsub_vx_i8m4_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m4_tu(merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vsub_vx_i8m8_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m8_tu(merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vsub_vx_i16mf4_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16mf4_tu(merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vsub_vx_i16mf2_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16mf2_tu(merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vsub_vx_i16m1_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m1_tu(merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vsub_vx_i16m2_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m2_tu(merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vsub_vx_i16m4_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m4_tu(merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vsub_vx_i16m8_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m8_tu(merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vsub_vx_i32mf2_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32mf2_tu(merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vsub_vx_i32m1_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m1_tu(merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vsub_vx_i32m2_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m2_tu(merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vsub_vx_i32m4_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m4_tu(merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vsub_vx_i32m8_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m8_tu(merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vsub_vx_i64m1_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m1_tu(merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vsub_vx_i64m2_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m2_tu(merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vsub_vx_i64m4_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m4_tu(merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vsub_vx_i64m8_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m8_tu(merge,op1,op2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vsub_vx_u8mf8_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf8_tu(merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vsub_vx_u8mf4_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf4_tu(merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vsub_vx_u8mf2_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf2_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vsub_vx_u8m1_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m1_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vsub_vx_u8m2_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m2_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vsub_vx_u8m4_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m4_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vsub_vx_u8m8_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m8_tu(merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vsub_vx_u16mf4_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16mf4_tu(merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vsub_vx_u16mf2_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16mf2_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vsub_vx_u16m1_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m1_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vsub_vx_u16m2_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m2_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vsub_vx_u16m4_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m4_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vsub_vx_u16m8_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m8_tu(merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vsub_vx_u32mf2_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32mf2_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vsub_vx_u32m1_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m1_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vsub_vx_u32m2_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m2_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vsub_vx_u32m4_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m4_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vsub_vx_u32m8_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m8_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vsub_vx_u64m1_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m1_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vsub_vx_u64m2_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m2_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vsub_vx_u64m4_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m4_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vsub_vx_u64m8_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m8_tu(merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tu_rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tu_rv32-2.c
new file mode 100644
index 00000000000..cbb1e949fb3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tu_rv32-2.c
@@ -0,0 +1,289 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsub_vx_i8mf8_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf8_tu(merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vsub_vx_i8mf4_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf4_tu(merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vsub_vx_i8mf2_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf2_tu(merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vsub_vx_i8m1_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m1_tu(merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vsub_vx_i8m2_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m2_tu(merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vsub_vx_i8m4_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m4_tu(merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vsub_vx_i8m8_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m8_tu(merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vsub_vx_i16mf4_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16mf4_tu(merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vsub_vx_i16mf2_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16mf2_tu(merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vsub_vx_i16m1_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m1_tu(merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vsub_vx_i16m2_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m2_tu(merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vsub_vx_i16m4_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m4_tu(merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vsub_vx_i16m8_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m8_tu(merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vsub_vx_i32mf2_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32mf2_tu(merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vsub_vx_i32m1_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m1_tu(merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vsub_vx_i32m2_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m2_tu(merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vsub_vx_i32m4_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m4_tu(merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vsub_vx_i32m8_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m8_tu(merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vsub_vx_i64m1_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m1_tu(merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vsub_vx_i64m2_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m2_tu(merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vsub_vx_i64m4_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m4_tu(merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vsub_vx_i64m8_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m8_tu(merge,op1,op2,31);
+}
+
+
+vuint8mf8_t test___riscv_vsub_vx_u8mf8_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf8_tu(merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vsub_vx_u8mf4_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf4_tu(merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vsub_vx_u8mf2_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf2_tu(merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vsub_vx_u8m1_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m1_tu(merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vsub_vx_u8m2_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m2_tu(merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vsub_vx_u8m4_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m4_tu(merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vsub_vx_u8m8_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m8_tu(merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vsub_vx_u16mf4_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16mf4_tu(merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vsub_vx_u16mf2_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16mf2_tu(merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vsub_vx_u16m1_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m1_tu(merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vsub_vx_u16m2_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m2_tu(merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vsub_vx_u16m4_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m4_tu(merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vsub_vx_u16m8_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m8_tu(merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vsub_vx_u32mf2_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32mf2_tu(merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vsub_vx_u32m1_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m1_tu(merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vsub_vx_u32m2_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m2_tu(merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vsub_vx_u32m4_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m4_tu(merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vsub_vx_u32m8_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m8_tu(merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vsub_vx_u64m1_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m1_tu(merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vsub_vx_u64m2_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m2_tu(merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vsub_vx_u64m4_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m4_tu(merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vsub_vx_u64m8_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m8_tu(merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tu_rv32-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tu_rv32-3.c
new file mode 100644
index 00000000000..d4a12a2ba1f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tu_rv32-3.c
@@ -0,0 +1,289 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsub_vx_i8mf8_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf8_tu(merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vsub_vx_i8mf4_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf4_tu(merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vsub_vx_i8mf2_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf2_tu(merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vsub_vx_i8m1_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m1_tu(merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vsub_vx_i8m2_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m2_tu(merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vsub_vx_i8m4_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m4_tu(merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vsub_vx_i8m8_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m8_tu(merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vsub_vx_i16mf4_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16mf4_tu(merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vsub_vx_i16mf2_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16mf2_tu(merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vsub_vx_i16m1_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m1_tu(merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vsub_vx_i16m2_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m2_tu(merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vsub_vx_i16m4_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m4_tu(merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vsub_vx_i16m8_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m8_tu(merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vsub_vx_i32mf2_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32mf2_tu(merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vsub_vx_i32m1_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m1_tu(merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vsub_vx_i32m2_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m2_tu(merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vsub_vx_i32m4_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m4_tu(merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vsub_vx_i32m8_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m8_tu(merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vsub_vx_i64m1_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m1_tu(merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vsub_vx_i64m2_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m2_tu(merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vsub_vx_i64m4_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m4_tu(merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vsub_vx_i64m8_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m8_tu(merge,op1,op2,32);
+}
+
+
+vuint8mf8_t test___riscv_vsub_vx_u8mf8_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf8_tu(merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vsub_vx_u8mf4_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf4_tu(merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vsub_vx_u8mf2_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf2_tu(merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vsub_vx_u8m1_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m1_tu(merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vsub_vx_u8m2_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m2_tu(merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vsub_vx_u8m4_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m4_tu(merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vsub_vx_u8m8_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m8_tu(merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vsub_vx_u16mf4_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16mf4_tu(merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vsub_vx_u16mf2_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16mf2_tu(merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vsub_vx_u16m1_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m1_tu(merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vsub_vx_u16m2_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m2_tu(merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vsub_vx_u16m4_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m4_tu(merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vsub_vx_u16m8_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m8_tu(merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vsub_vx_u32mf2_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32mf2_tu(merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vsub_vx_u32m1_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m1_tu(merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vsub_vx_u32m2_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m2_tu(merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vsub_vx_u32m4_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m4_tu(merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vsub_vx_u32m8_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m8_tu(merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vsub_vx_u64m1_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m1_tu(merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vsub_vx_u64m2_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m2_tu(merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vsub_vx_u64m4_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m4_tu(merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vsub_vx_u64m8_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m8_tu(merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tu_rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tu_rv64-1.c
new file mode 100644
index 00000000000..dd34b654bbc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tu_rv64-1.c
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsub_vx_i8mf8_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf8_tu(merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vsub_vx_i8mf4_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf4_tu(merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vsub_vx_i8mf2_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf2_tu(merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vsub_vx_i8m1_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m1_tu(merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vsub_vx_i8m2_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m2_tu(merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vsub_vx_i8m4_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m4_tu(merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vsub_vx_i8m8_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m8_tu(merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vsub_vx_i16mf4_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16mf4_tu(merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vsub_vx_i16mf2_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16mf2_tu(merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vsub_vx_i16m1_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m1_tu(merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vsub_vx_i16m2_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m2_tu(merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vsub_vx_i16m4_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m4_tu(merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vsub_vx_i16m8_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m8_tu(merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vsub_vx_i32mf2_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32mf2_tu(merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vsub_vx_i32m1_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m1_tu(merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vsub_vx_i32m2_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m2_tu(merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vsub_vx_i32m4_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m4_tu(merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vsub_vx_i32m8_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m8_tu(merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vsub_vx_i64m1_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m1_tu(merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vsub_vx_i64m2_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m2_tu(merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vsub_vx_i64m4_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m4_tu(merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vsub_vx_i64m8_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m8_tu(merge,op1,op2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vsub_vx_u8mf8_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf8_tu(merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vsub_vx_u8mf4_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf4_tu(merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vsub_vx_u8mf2_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf2_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vsub_vx_u8m1_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m1_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vsub_vx_u8m2_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m2_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vsub_vx_u8m4_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m4_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vsub_vx_u8m8_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m8_tu(merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vsub_vx_u16mf4_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16mf4_tu(merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vsub_vx_u16mf2_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16mf2_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vsub_vx_u16m1_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m1_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vsub_vx_u16m2_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m2_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vsub_vx_u16m4_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m4_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vsub_vx_u16m8_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m8_tu(merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vsub_vx_u32mf2_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32mf2_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vsub_vx_u32m1_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m1_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vsub_vx_u32m2_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m2_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vsub_vx_u32m4_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m4_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vsub_vx_u32m8_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m8_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vsub_vx_u64m1_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m1_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vsub_vx_u64m2_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m2_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vsub_vx_u64m4_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m4_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vsub_vx_u64m8_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m8_tu(merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tu_rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tu_rv64-2.c
new file mode 100644
index 00000000000..ba01bd911fb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tu_rv64-2.c
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsub_vx_i8mf8_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf8_tu(merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vsub_vx_i8mf4_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf4_tu(merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vsub_vx_i8mf2_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf2_tu(merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vsub_vx_i8m1_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m1_tu(merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vsub_vx_i8m2_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m2_tu(merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vsub_vx_i8m4_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m4_tu(merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vsub_vx_i8m8_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m8_tu(merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vsub_vx_i16mf4_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16mf4_tu(merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vsub_vx_i16mf2_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16mf2_tu(merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vsub_vx_i16m1_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m1_tu(merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vsub_vx_i16m2_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m2_tu(merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vsub_vx_i16m4_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m4_tu(merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vsub_vx_i16m8_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m8_tu(merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vsub_vx_i32mf2_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32mf2_tu(merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vsub_vx_i32m1_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m1_tu(merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vsub_vx_i32m2_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m2_tu(merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vsub_vx_i32m4_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m4_tu(merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vsub_vx_i32m8_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m8_tu(merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vsub_vx_i64m1_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m1_tu(merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vsub_vx_i64m2_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m2_tu(merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vsub_vx_i64m4_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m4_tu(merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vsub_vx_i64m8_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m8_tu(merge,op1,op2,31);
+}
+
+
+vuint8mf8_t test___riscv_vsub_vx_u8mf8_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf8_tu(merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vsub_vx_u8mf4_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf4_tu(merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vsub_vx_u8mf2_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf2_tu(merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vsub_vx_u8m1_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m1_tu(merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vsub_vx_u8m2_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m2_tu(merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vsub_vx_u8m4_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m4_tu(merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vsub_vx_u8m8_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m8_tu(merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vsub_vx_u16mf4_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16mf4_tu(merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vsub_vx_u16mf2_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16mf2_tu(merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vsub_vx_u16m1_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m1_tu(merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vsub_vx_u16m2_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m2_tu(merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vsub_vx_u16m4_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m4_tu(merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vsub_vx_u16m8_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m8_tu(merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vsub_vx_u32mf2_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32mf2_tu(merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vsub_vx_u32m1_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m1_tu(merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vsub_vx_u32m2_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m2_tu(merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vsub_vx_u32m4_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m4_tu(merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vsub_vx_u32m8_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m8_tu(merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vsub_vx_u64m1_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m1_tu(merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vsub_vx_u64m2_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m2_tu(merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vsub_vx_u64m4_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m4_tu(merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vsub_vx_u64m8_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m8_tu(merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tu_rv64-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tu_rv64-3.c
new file mode 100644
index 00000000000..e75d10ff568
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tu_rv64-3.c
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsub_vx_i8mf8_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf8_tu(merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vsub_vx_i8mf4_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf4_tu(merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vsub_vx_i8mf2_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf2_tu(merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vsub_vx_i8m1_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m1_tu(merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vsub_vx_i8m2_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m2_tu(merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vsub_vx_i8m4_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m4_tu(merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vsub_vx_i8m8_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m8_tu(merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vsub_vx_i16mf4_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16mf4_tu(merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vsub_vx_i16mf2_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16mf2_tu(merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vsub_vx_i16m1_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m1_tu(merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vsub_vx_i16m2_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m2_tu(merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vsub_vx_i16m4_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m4_tu(merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vsub_vx_i16m8_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m8_tu(merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vsub_vx_i32mf2_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32mf2_tu(merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vsub_vx_i32m1_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m1_tu(merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vsub_vx_i32m2_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m2_tu(merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vsub_vx_i32m4_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m4_tu(merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vsub_vx_i32m8_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m8_tu(merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vsub_vx_i64m1_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m1_tu(merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vsub_vx_i64m2_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m2_tu(merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vsub_vx_i64m4_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m4_tu(merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vsub_vx_i64m8_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m8_tu(merge,op1,op2,32);
+}
+
+
+vuint8mf8_t test___riscv_vsub_vx_u8mf8_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf8_tu(merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vsub_vx_u8mf4_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf4_tu(merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vsub_vx_u8mf2_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf2_tu(merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vsub_vx_u8m1_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m1_tu(merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vsub_vx_u8m2_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m2_tu(merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vsub_vx_u8m4_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m4_tu(merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vsub_vx_u8m8_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m8_tu(merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vsub_vx_u16mf4_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16mf4_tu(merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vsub_vx_u16mf2_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16mf2_tu(merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vsub_vx_u16m1_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m1_tu(merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vsub_vx_u16m2_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m2_tu(merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vsub_vx_u16m4_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m4_tu(merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vsub_vx_u16m8_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m8_tu(merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vsub_vx_u32mf2_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32mf2_tu(merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vsub_vx_u32m1_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m1_tu(merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vsub_vx_u32m2_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m2_tu(merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vsub_vx_u32m4_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m4_tu(merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vsub_vx_u32m8_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m8_tu(merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vsub_vx_u64m1_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m1_tu(merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vsub_vx_u64m2_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m2_tu(merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vsub_vx_u64m4_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m4_tu(merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vsub_vx_u64m8_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m8_tu(merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tum_rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tum_rv32-1.c
new file mode 100644
index 00000000000..a8db1e8d39f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tum_rv32-1.c
@@ -0,0 +1,289 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsub_vx_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf8_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vsub_vx_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vsub_vx_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vsub_vx_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m1_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vsub_vx_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vsub_vx_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vsub_vx_i8m8_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m8_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vsub_vx_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16mf4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vsub_vx_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16mf2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vsub_vx_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m1_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vsub_vx_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vsub_vx_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vsub_vx_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m8_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vsub_vx_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32mf2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vsub_vx_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m1_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vsub_vx_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vsub_vx_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vsub_vx_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m8_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vsub_vx_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m1_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vsub_vx_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vsub_vx_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vsub_vx_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m8_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vsub_vx_u8mf8_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf8_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vsub_vx_u8mf4_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vsub_vx_u8mf2_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vsub_vx_u8m1_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m1_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vsub_vx_u8m2_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vsub_vx_u8m4_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vsub_vx_u8m8_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m8_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vsub_vx_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16mf4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vsub_vx_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16mf2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vsub_vx_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m1_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vsub_vx_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vsub_vx_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vsub_vx_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m8_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vsub_vx_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32mf2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vsub_vx_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m1_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vsub_vx_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vsub_vx_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vsub_vx_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m8_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vsub_vx_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m1_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vsub_vx_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vsub_vx_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vsub_vx_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m8_tum(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tum_rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tum_rv32-2.c
new file mode 100644
index 00000000000..82d51ec6796
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tum_rv32-2.c
@@ -0,0 +1,289 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsub_vx_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf8_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vsub_vx_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf4_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vsub_vx_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf2_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vsub_vx_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m1_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vsub_vx_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m2_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vsub_vx_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m4_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vsub_vx_i8m8_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m8_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vsub_vx_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16mf4_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vsub_vx_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16mf2_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vsub_vx_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m1_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vsub_vx_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m2_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vsub_vx_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m4_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vsub_vx_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m8_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vsub_vx_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32mf2_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vsub_vx_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m1_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vsub_vx_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m2_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vsub_vx_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m4_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vsub_vx_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m8_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vsub_vx_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m1_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vsub_vx_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m2_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vsub_vx_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m4_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vsub_vx_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m8_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf8_t test___riscv_vsub_vx_u8mf8_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf8_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vsub_vx_u8mf4_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf4_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vsub_vx_u8mf2_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf2_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vsub_vx_u8m1_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m1_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vsub_vx_u8m2_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m2_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vsub_vx_u8m4_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m4_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vsub_vx_u8m8_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m8_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vsub_vx_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16mf4_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vsub_vx_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16mf2_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vsub_vx_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m1_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vsub_vx_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m2_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vsub_vx_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m4_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vsub_vx_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m8_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vsub_vx_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32mf2_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vsub_vx_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m1_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vsub_vx_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m2_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vsub_vx_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m4_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vsub_vx_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m8_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vsub_vx_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m1_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vsub_vx_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m2_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vsub_vx_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m4_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vsub_vx_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m8_tum(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tum_rv32-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tum_rv32-3.c
new file mode 100644
index 00000000000..e9cc6a763d8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tum_rv32-3.c
@@ -0,0 +1,289 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsub_vx_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf8_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vsub_vx_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf4_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vsub_vx_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf2_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vsub_vx_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m1_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vsub_vx_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m2_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vsub_vx_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m4_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vsub_vx_i8m8_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m8_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vsub_vx_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16mf4_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vsub_vx_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16mf2_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vsub_vx_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m1_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vsub_vx_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m2_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vsub_vx_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m4_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vsub_vx_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m8_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vsub_vx_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32mf2_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vsub_vx_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m1_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vsub_vx_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m2_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vsub_vx_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m4_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vsub_vx_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m8_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vsub_vx_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m1_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vsub_vx_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m2_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vsub_vx_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m4_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vsub_vx_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m8_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf8_t test___riscv_vsub_vx_u8mf8_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf8_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vsub_vx_u8mf4_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf4_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vsub_vx_u8mf2_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf2_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vsub_vx_u8m1_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m1_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vsub_vx_u8m2_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m2_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vsub_vx_u8m4_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m4_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vsub_vx_u8m8_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m8_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vsub_vx_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16mf4_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vsub_vx_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16mf2_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vsub_vx_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m1_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vsub_vx_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m2_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vsub_vx_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m4_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vsub_vx_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m8_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vsub_vx_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32mf2_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vsub_vx_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m1_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vsub_vx_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m2_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vsub_vx_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m4_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vsub_vx_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m8_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vsub_vx_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m1_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vsub_vx_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m2_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vsub_vx_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m4_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vsub_vx_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m8_tum(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tum_rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tum_rv64-1.c
new file mode 100644
index 00000000000..f59d7bd69dc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tum_rv64-1.c
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsub_vx_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf8_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vsub_vx_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vsub_vx_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vsub_vx_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m1_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vsub_vx_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vsub_vx_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vsub_vx_i8m8_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m8_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vsub_vx_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16mf4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vsub_vx_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16mf2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vsub_vx_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m1_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vsub_vx_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vsub_vx_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vsub_vx_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m8_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vsub_vx_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32mf2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vsub_vx_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m1_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vsub_vx_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vsub_vx_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vsub_vx_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m8_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vsub_vx_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m1_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vsub_vx_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vsub_vx_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vsub_vx_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m8_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vsub_vx_u8mf8_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf8_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vsub_vx_u8mf4_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vsub_vx_u8mf2_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vsub_vx_u8m1_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m1_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vsub_vx_u8m2_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vsub_vx_u8m4_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vsub_vx_u8m8_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m8_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vsub_vx_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16mf4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vsub_vx_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16mf2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vsub_vx_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m1_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vsub_vx_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vsub_vx_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vsub_vx_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m8_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vsub_vx_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32mf2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vsub_vx_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m1_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vsub_vx_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vsub_vx_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vsub_vx_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m8_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vsub_vx_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m1_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vsub_vx_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vsub_vx_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vsub_vx_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m8_tum(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tum_rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tum_rv64-2.c
new file mode 100644
index 00000000000..74518321c4a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tum_rv64-2.c
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsub_vx_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf8_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vsub_vx_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf4_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vsub_vx_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf2_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vsub_vx_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m1_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vsub_vx_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m2_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vsub_vx_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m4_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vsub_vx_i8m8_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m8_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vsub_vx_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16mf4_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vsub_vx_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16mf2_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vsub_vx_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m1_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vsub_vx_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m2_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vsub_vx_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m4_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vsub_vx_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m8_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vsub_vx_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32mf2_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vsub_vx_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m1_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vsub_vx_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m2_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vsub_vx_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m4_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vsub_vx_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m8_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vsub_vx_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m1_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vsub_vx_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m2_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vsub_vx_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m4_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vsub_vx_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m8_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf8_t test___riscv_vsub_vx_u8mf8_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf8_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vsub_vx_u8mf4_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf4_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vsub_vx_u8mf2_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf2_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vsub_vx_u8m1_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m1_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vsub_vx_u8m2_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m2_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vsub_vx_u8m4_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m4_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vsub_vx_u8m8_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m8_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vsub_vx_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16mf4_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vsub_vx_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16mf2_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vsub_vx_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m1_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vsub_vx_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m2_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vsub_vx_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m4_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vsub_vx_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m8_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vsub_vx_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32mf2_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vsub_vx_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m1_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vsub_vx_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m2_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vsub_vx_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m4_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vsub_vx_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m8_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vsub_vx_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m1_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vsub_vx_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m2_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vsub_vx_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m4_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vsub_vx_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m8_tum(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tum_rv64-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tum_rv64-3.c
new file mode 100644
index 00000000000..889d18ab481
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tum_rv64-3.c
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsub_vx_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf8_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vsub_vx_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf4_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vsub_vx_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf2_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vsub_vx_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m1_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vsub_vx_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m2_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vsub_vx_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m4_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vsub_vx_i8m8_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m8_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vsub_vx_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16mf4_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vsub_vx_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16mf2_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vsub_vx_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m1_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vsub_vx_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m2_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vsub_vx_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m4_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vsub_vx_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m8_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vsub_vx_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32mf2_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vsub_vx_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m1_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vsub_vx_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m2_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vsub_vx_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m4_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vsub_vx_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m8_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vsub_vx_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m1_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vsub_vx_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m2_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vsub_vx_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m4_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vsub_vx_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m8_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf8_t test___riscv_vsub_vx_u8mf8_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf8_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vsub_vx_u8mf4_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf4_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vsub_vx_u8mf2_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf2_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vsub_vx_u8m1_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m1_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vsub_vx_u8m2_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m2_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vsub_vx_u8m4_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m4_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vsub_vx_u8m8_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m8_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vsub_vx_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16mf4_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vsub_vx_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16mf2_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vsub_vx_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m1_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vsub_vx_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m2_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vsub_vx_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m4_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vsub_vx_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m8_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vsub_vx_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32mf2_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vsub_vx_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m1_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vsub_vx_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m2_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vsub_vx_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m4_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vsub_vx_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m8_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vsub_vx_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m1_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vsub_vx_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m2_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vsub_vx_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m4_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vsub_vx_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m8_tum(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tumu_rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tumu_rv32-1.c
new file mode 100644
index 00000000000..5b4000e60c5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tumu_rv32-1.c
@@ -0,0 +1,289 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsub_vx_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf8_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vsub_vx_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vsub_vx_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vsub_vx_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m1_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vsub_vx_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vsub_vx_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vsub_vx_i8m8_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m8_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vsub_vx_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16mf4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vsub_vx_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16mf2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vsub_vx_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m1_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vsub_vx_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vsub_vx_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vsub_vx_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m8_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vsub_vx_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32mf2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vsub_vx_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m1_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vsub_vx_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vsub_vx_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vsub_vx_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m8_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vsub_vx_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m1_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vsub_vx_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vsub_vx_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vsub_vx_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m8_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vsub_vx_u8mf8_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf8_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vsub_vx_u8mf4_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vsub_vx_u8mf2_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vsub_vx_u8m1_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m1_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vsub_vx_u8m2_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vsub_vx_u8m4_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vsub_vx_u8m8_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m8_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vsub_vx_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16mf4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vsub_vx_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16mf2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vsub_vx_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m1_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vsub_vx_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vsub_vx_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vsub_vx_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m8_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vsub_vx_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32mf2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vsub_vx_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m1_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vsub_vx_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vsub_vx_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vsub_vx_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m8_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vsub_vx_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m1_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vsub_vx_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vsub_vx_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vsub_vx_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m8_tumu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tumu_rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tumu_rv32-2.c
new file mode 100644
index 00000000000..b2560e2d99a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tumu_rv32-2.c
@@ -0,0 +1,289 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsub_vx_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf8_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vsub_vx_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vsub_vx_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vsub_vx_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m1_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vsub_vx_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vsub_vx_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vsub_vx_i8m8_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m8_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vsub_vx_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16mf4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vsub_vx_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16mf2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vsub_vx_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m1_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vsub_vx_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vsub_vx_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vsub_vx_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m8_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vsub_vx_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32mf2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vsub_vx_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m1_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vsub_vx_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vsub_vx_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vsub_vx_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m8_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vsub_vx_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m1_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vsub_vx_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vsub_vx_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vsub_vx_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m8_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf8_t test___riscv_vsub_vx_u8mf8_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf8_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vsub_vx_u8mf4_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vsub_vx_u8mf2_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vsub_vx_u8m1_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m1_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vsub_vx_u8m2_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vsub_vx_u8m4_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vsub_vx_u8m8_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m8_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vsub_vx_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16mf4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vsub_vx_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16mf2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vsub_vx_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m1_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vsub_vx_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vsub_vx_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vsub_vx_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m8_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vsub_vx_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32mf2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vsub_vx_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m1_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vsub_vx_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vsub_vx_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vsub_vx_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m8_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vsub_vx_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m1_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vsub_vx_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vsub_vx_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vsub_vx_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m8_tumu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tumu_rv32-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tumu_rv32-3.c
new file mode 100644
index 00000000000..c0a945738b0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tumu_rv32-3.c
@@ -0,0 +1,289 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsub_vx_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf8_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vsub_vx_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vsub_vx_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vsub_vx_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m1_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vsub_vx_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vsub_vx_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vsub_vx_i8m8_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m8_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vsub_vx_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16mf4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vsub_vx_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16mf2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vsub_vx_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m1_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vsub_vx_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vsub_vx_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vsub_vx_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m8_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vsub_vx_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32mf2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vsub_vx_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m1_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vsub_vx_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vsub_vx_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vsub_vx_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m8_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vsub_vx_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m1_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vsub_vx_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vsub_vx_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vsub_vx_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m8_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf8_t test___riscv_vsub_vx_u8mf8_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf8_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vsub_vx_u8mf4_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vsub_vx_u8mf2_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vsub_vx_u8m1_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m1_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vsub_vx_u8m2_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vsub_vx_u8m4_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vsub_vx_u8m8_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m8_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vsub_vx_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16mf4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vsub_vx_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16mf2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vsub_vx_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m1_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vsub_vx_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vsub_vx_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vsub_vx_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m8_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vsub_vx_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32mf2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vsub_vx_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m1_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vsub_vx_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vsub_vx_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vsub_vx_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m8_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vsub_vx_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m1_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vsub_vx_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vsub_vx_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vsub_vx_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m8_tumu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 8 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tumu_rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tumu_rv64-1.c
new file mode 100644
index 00000000000..74a51cabe8d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tumu_rv64-1.c
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsub_vx_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf8_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vsub_vx_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vsub_vx_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vsub_vx_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m1_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vsub_vx_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vsub_vx_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vsub_vx_i8m8_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m8_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vsub_vx_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16mf4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vsub_vx_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16mf2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vsub_vx_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m1_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vsub_vx_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vsub_vx_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vsub_vx_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m8_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vsub_vx_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32mf2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vsub_vx_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m1_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vsub_vx_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vsub_vx_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vsub_vx_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m8_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vsub_vx_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m1_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vsub_vx_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vsub_vx_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vsub_vx_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m8_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vsub_vx_u8mf8_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf8_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vsub_vx_u8mf4_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vsub_vx_u8mf2_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vsub_vx_u8m1_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m1_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vsub_vx_u8m2_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vsub_vx_u8m4_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vsub_vx_u8m8_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m8_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vsub_vx_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16mf4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vsub_vx_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16mf2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vsub_vx_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m1_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vsub_vx_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vsub_vx_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vsub_vx_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m8_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vsub_vx_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32mf2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vsub_vx_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m1_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vsub_vx_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vsub_vx_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vsub_vx_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m8_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vsub_vx_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m1_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vsub_vx_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vsub_vx_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vsub_vx_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m8_tumu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tumu_rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tumu_rv64-2.c
new file mode 100644
index 00000000000..f25ddbcf46a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tumu_rv64-2.c
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsub_vx_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf8_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vsub_vx_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vsub_vx_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vsub_vx_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m1_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vsub_vx_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vsub_vx_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vsub_vx_i8m8_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m8_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vsub_vx_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16mf4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vsub_vx_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16mf2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vsub_vx_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m1_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vsub_vx_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vsub_vx_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vsub_vx_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m8_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vsub_vx_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32mf2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vsub_vx_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m1_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vsub_vx_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vsub_vx_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vsub_vx_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m8_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vsub_vx_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m1_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vsub_vx_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vsub_vx_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vsub_vx_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m8_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf8_t test___riscv_vsub_vx_u8mf8_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf8_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vsub_vx_u8mf4_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vsub_vx_u8mf2_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vsub_vx_u8m1_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m1_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vsub_vx_u8m2_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vsub_vx_u8m4_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vsub_vx_u8m8_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m8_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vsub_vx_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16mf4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vsub_vx_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16mf2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vsub_vx_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m1_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vsub_vx_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vsub_vx_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vsub_vx_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m8_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vsub_vx_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32mf2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vsub_vx_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m1_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vsub_vx_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vsub_vx_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vsub_vx_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m8_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vsub_vx_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m1_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vsub_vx_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vsub_vx_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vsub_vx_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m8_tumu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tumu_rv64-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tumu_rv64-3.c
new file mode 100644
index 00000000000..fb875a58dec
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsub_vx_tumu_rv64-3.c
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsub_vx_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf8_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vsub_vx_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vsub_vx_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8mf2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vsub_vx_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m1_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vsub_vx_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vsub_vx_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vsub_vx_i8m8_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i8m8_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vsub_vx_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16mf4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vsub_vx_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16mf2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vsub_vx_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m1_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vsub_vx_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vsub_vx_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vsub_vx_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i16m8_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vsub_vx_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32mf2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vsub_vx_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m1_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vsub_vx_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vsub_vx_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vsub_vx_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i32m8_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vsub_vx_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m1_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vsub_vx_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vsub_vx_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vsub_vx_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_i64m8_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf8_t test___riscv_vsub_vx_u8mf8_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf8_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vsub_vx_u8mf4_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vsub_vx_u8mf2_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8mf2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vsub_vx_u8m1_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m1_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vsub_vx_u8m2_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vsub_vx_u8m4_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vsub_vx_u8m8_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u8m8_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vsub_vx_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16mf4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vsub_vx_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16mf2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vsub_vx_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m1_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vsub_vx_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vsub_vx_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vsub_vx_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u16m8_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vsub_vx_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32mf2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vsub_vx_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m1_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vsub_vx_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vsub_vx_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vsub_vx_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u32m8_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vsub_vx_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m1_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vsub_vx_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vsub_vx_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vsub_vx_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_vx_u64m8_tumu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 2 } } */
--
2.36.1
^ permalink raw reply [flat|nested] 2+ messages in thread
* [PATCH] RISC-V: Add vsub.vx C++ API tests
@ 2023-02-03 7:42 juzhe.zhong
0 siblings, 0 replies; 2+ messages in thread
From: juzhe.zhong @ 2023-02-03 7:42 UTC (permalink / raw)
To: gcc-patches; +Cc: kito.cheng, Ju-Zhe Zhong
From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/vsub_vx_mu_rv32-1.C: New test.
* g++.target/riscv/rvv/base/vsub_vx_mu_rv32-2.C: New test.
* g++.target/riscv/rvv/base/vsub_vx_mu_rv32-3.C: New test.
* g++.target/riscv/rvv/base/vsub_vx_mu_rv64-1.C: New test.
* g++.target/riscv/rvv/base/vsub_vx_mu_rv64-2.C: New test.
* g++.target/riscv/rvv/base/vsub_vx_mu_rv64-3.C: New test.
* g++.target/riscv/rvv/base/vsub_vx_rv32-1.C: New test.
* g++.target/riscv/rvv/base/vsub_vx_rv32-2.C: New test.
* g++.target/riscv/rvv/base/vsub_vx_rv32-3.C: New test.
* g++.target/riscv/rvv/base/vsub_vx_rv64-1.C: New test.
* g++.target/riscv/rvv/base/vsub_vx_rv64-2.C: New test.
* g++.target/riscv/rvv/base/vsub_vx_rv64-3.C: New test.
* g++.target/riscv/rvv/base/vsub_vx_tu_rv32-1.C: New test.
* g++.target/riscv/rvv/base/vsub_vx_tu_rv32-2.C: New test.
* g++.target/riscv/rvv/base/vsub_vx_tu_rv32-3.C: New test.
* g++.target/riscv/rvv/base/vsub_vx_tu_rv64-1.C: New test.
* g++.target/riscv/rvv/base/vsub_vx_tu_rv64-2.C: New test.
* g++.target/riscv/rvv/base/vsub_vx_tu_rv64-3.C: New test.
* g++.target/riscv/rvv/base/vsub_vx_tum_rv32-1.C: New test.
* g++.target/riscv/rvv/base/vsub_vx_tum_rv32-2.C: New test.
* g++.target/riscv/rvv/base/vsub_vx_tum_rv32-3.C: New test.
* g++.target/riscv/rvv/base/vsub_vx_tum_rv64-1.C: New test.
* g++.target/riscv/rvv/base/vsub_vx_tum_rv64-2.C: New test.
* g++.target/riscv/rvv/base/vsub_vx_tum_rv64-3.C: New test.
* g++.target/riscv/rvv/base/vsub_vx_tumu_rv32-1.C: New test.
* g++.target/riscv/rvv/base/vsub_vx_tumu_rv32-2.C: New test.
* g++.target/riscv/rvv/base/vsub_vx_tumu_rv32-3.C: New test.
* g++.target/riscv/rvv/base/vsub_vx_tumu_rv64-1.C: New test.
* g++.target/riscv/rvv/base/vsub_vx_tumu_rv64-2.C: New test.
* g++.target/riscv/rvv/base/vsub_vx_tumu_rv64-3.C: New test.
---
.../riscv/rvv/base/vsub_vx_mu_rv32-1.C | 289 +++++++++
.../riscv/rvv/base/vsub_vx_mu_rv32-2.C | 289 +++++++++
.../riscv/rvv/base/vsub_vx_mu_rv32-3.C | 289 +++++++++
.../riscv/rvv/base/vsub_vx_mu_rv64-1.C | 292 +++++++++
.../riscv/rvv/base/vsub_vx_mu_rv64-2.C | 292 +++++++++
.../riscv/rvv/base/vsub_vx_mu_rv64-3.C | 292 +++++++++
.../riscv/rvv/base/vsub_vx_rv32-1.C | 572 +++++++++++++++++
.../riscv/rvv/base/vsub_vx_rv32-2.C | 572 +++++++++++++++++
.../riscv/rvv/base/vsub_vx_rv32-3.C | 572 +++++++++++++++++
.../riscv/rvv/base/vsub_vx_rv64-1.C | 578 ++++++++++++++++++
.../riscv/rvv/base/vsub_vx_rv64-2.C | 578 ++++++++++++++++++
.../riscv/rvv/base/vsub_vx_rv64-3.C | 578 ++++++++++++++++++
.../riscv/rvv/base/vsub_vx_tu_rv32-1.C | 289 +++++++++
.../riscv/rvv/base/vsub_vx_tu_rv32-2.C | 289 +++++++++
.../riscv/rvv/base/vsub_vx_tu_rv32-3.C | 289 +++++++++
.../riscv/rvv/base/vsub_vx_tu_rv64-1.C | 292 +++++++++
.../riscv/rvv/base/vsub_vx_tu_rv64-2.C | 292 +++++++++
.../riscv/rvv/base/vsub_vx_tu_rv64-3.C | 292 +++++++++
.../riscv/rvv/base/vsub_vx_tum_rv32-1.C | 289 +++++++++
.../riscv/rvv/base/vsub_vx_tum_rv32-2.C | 289 +++++++++
.../riscv/rvv/base/vsub_vx_tum_rv32-3.C | 289 +++++++++
.../riscv/rvv/base/vsub_vx_tum_rv64-1.C | 292 +++++++++
.../riscv/rvv/base/vsub_vx_tum_rv64-2.C | 292 +++++++++
.../riscv/rvv/base/vsub_vx_tum_rv64-3.C | 292 +++++++++
.../riscv/rvv/base/vsub_vx_tumu_rv32-1.C | 289 +++++++++
.../riscv/rvv/base/vsub_vx_tumu_rv32-2.C | 289 +++++++++
.../riscv/rvv/base/vsub_vx_tumu_rv32-3.C | 289 +++++++++
.../riscv/rvv/base/vsub_vx_tumu_rv64-1.C | 292 +++++++++
.../riscv/rvv/base/vsub_vx_tumu_rv64-2.C | 292 +++++++++
.../riscv/rvv/base/vsub_vx_tumu_rv64-3.C | 292 +++++++++
30 files changed, 10422 insertions(+)
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_mu_rv32-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_mu_rv32-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_mu_rv32-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_mu_rv64-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_mu_rv64-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_mu_rv64-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_rv32-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_rv32-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_rv32-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_rv64-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_rv64-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_rv64-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tu_rv32-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tu_rv32-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tu_rv32-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tu_rv64-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tu_rv64-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tu_rv64-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tum_rv32-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tum_rv32-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tum_rv32-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tum_rv64-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tum_rv64-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tum_rv64-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tumu_rv32-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tumu_rv32-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tumu_rv32-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tumu_rv64-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tumu_rv64-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tumu_rv64-3.C
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_mu_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_mu_rv32-1.C
new file mode 100644
index 00000000000..6e8f536247b
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_mu_rv32-1.C
@@ -0,0 +1,289 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsub_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vsub_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vsub_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vsub_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vsub_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vsub_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vsub_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vsub_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vsub_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vsub_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vsub_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vsub_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vsub_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vsub_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vsub_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vsub_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vsub_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vsub_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vsub_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vsub_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vsub_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vsub_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vsub_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vsub_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vsub_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vsub_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vsub_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vsub_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vsub_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vsub_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vsub_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vsub_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vsub_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vsub_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vsub_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vsub_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vsub_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vsub_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vsub_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vsub_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vsub_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vsub_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vsub_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vsub_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_mu_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_mu_rv32-2.C
new file mode 100644
index 00000000000..ba395cacce4
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_mu_rv32-2.C
@@ -0,0 +1,289 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsub_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vsub_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vsub_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vsub_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vsub_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vsub_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vsub_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vsub_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vsub_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vsub_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vsub_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vsub_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vsub_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vsub_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vsub_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vsub_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vsub_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vsub_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vsub_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vsub_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vsub_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vsub_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf8_t test___riscv_vsub_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vsub_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vsub_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vsub_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vsub_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vsub_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vsub_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vsub_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vsub_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vsub_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vsub_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vsub_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vsub_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vsub_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vsub_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vsub_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vsub_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vsub_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vsub_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vsub_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vsub_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vsub_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_mu_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_mu_rv32-3.C
new file mode 100644
index 00000000000..7afe9ded282
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_mu_rv32-3.C
@@ -0,0 +1,289 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsub_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vsub_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vsub_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vsub_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vsub_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vsub_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vsub_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vsub_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vsub_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vsub_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vsub_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vsub_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vsub_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vsub_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vsub_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vsub_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vsub_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vsub_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vsub_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vsub_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vsub_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vsub_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf8_t test___riscv_vsub_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vsub_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vsub_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vsub_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vsub_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vsub_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vsub_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vsub_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vsub_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vsub_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vsub_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vsub_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vsub_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vsub_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vsub_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vsub_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vsub_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vsub_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vsub_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vsub_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vsub_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vsub_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_mu_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_mu_rv64-1.C
new file mode 100644
index 00000000000..562d9d70832
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_mu_rv64-1.C
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsub_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vsub_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vsub_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vsub_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vsub_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vsub_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vsub_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vsub_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vsub_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vsub_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vsub_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vsub_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vsub_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vsub_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vsub_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vsub_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vsub_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vsub_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vsub_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vsub_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vsub_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vsub_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vsub_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vsub_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vsub_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vsub_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vsub_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vsub_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vsub_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vsub_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vsub_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vsub_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vsub_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vsub_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vsub_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vsub_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vsub_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vsub_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vsub_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vsub_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vsub_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vsub_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vsub_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vsub_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_mu_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_mu_rv64-2.C
new file mode 100644
index 00000000000..dc6b08caad6
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_mu_rv64-2.C
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsub_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vsub_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vsub_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vsub_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vsub_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vsub_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vsub_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vsub_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vsub_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vsub_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vsub_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vsub_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vsub_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vsub_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vsub_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vsub_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vsub_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vsub_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vsub_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vsub_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vsub_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vsub_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf8_t test___riscv_vsub_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vsub_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vsub_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vsub_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vsub_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vsub_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vsub_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vsub_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vsub_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vsub_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vsub_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vsub_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vsub_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vsub_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vsub_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vsub_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vsub_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vsub_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vsub_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vsub_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vsub_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vsub_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_mu_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_mu_rv64-3.C
new file mode 100644
index 00000000000..6d90eafcf8c
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_mu_rv64-3.C
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsub_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vsub_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vsub_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vsub_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vsub_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vsub_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vsub_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vsub_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vsub_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vsub_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vsub_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vsub_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vsub_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vsub_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vsub_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vsub_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vsub_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vsub_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vsub_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vsub_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vsub_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vsub_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf8_t test___riscv_vsub_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vsub_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vsub_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vsub_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vsub_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vsub_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vsub_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vsub_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vsub_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vsub_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vsub_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vsub_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vsub_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vsub_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vsub_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vsub_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vsub_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vsub_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vsub_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vsub_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vsub_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vsub_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_mu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_rv32-1.C
new file mode 100644
index 00000000000..71c4f43a981
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_rv32-1.C
@@ -0,0 +1,572 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsub(vint8mf8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vsub(vint8mf4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vsub(vint8mf2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vsub(vint8m1_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vsub(vint8m2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vsub(vint8m4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vsub(vint8m8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vsub(vint16mf4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vsub(vint16mf2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vsub(vint16m1_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vsub(vint16m2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vsub(vint16m4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vsub(vint16m8_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vsub(vint32mf2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vsub(vint32m1_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vsub(vint32m2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vsub(vint32m4_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vsub(vint32m8_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vsub(vint64m1_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vsub(vint64m2_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vsub(vint64m4_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vsub(vint64m8_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vsub(vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vsub(vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vsub(vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vsub(vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vsub(vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vsub(vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vsub(vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vsub(vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vsub(vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vsub(vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vsub(vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vsub(vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vsub(vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vsub(vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vsub(vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vsub(vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vsub(vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vsub(vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vsub(vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vsub(vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vsub(vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vsub(vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vint8mf8_t test___riscv_vsub(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vsub(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vsub(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vsub(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vsub(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vsub(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vsub(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vsub(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vsub(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vsub(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vsub(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vsub(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vsub(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vsub(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vsub(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vsub(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vsub(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vsub(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vsub(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vsub(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vsub(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vsub(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vsub(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vsub(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vsub(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vsub(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vsub(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vsub(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vsub(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vsub(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vsub(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vsub(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vsub(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vsub(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vsub(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vsub(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vsub(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vsub(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vsub(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vsub(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vsub(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vsub(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vsub(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vsub(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_rv32-2.C
new file mode 100644
index 00000000000..dd7074590d2
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_rv32-2.C
@@ -0,0 +1,572 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsub(vint8mf8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vsub(vint8mf4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vsub(vint8mf2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vsub(vint8m1_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vsub(vint8m2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vsub(vint8m4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vsub(vint8m8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vsub(vint16mf4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vsub(vint16mf2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vsub(vint16m1_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vsub(vint16m2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vsub(vint16m4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vsub(vint16m8_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vsub(vint32mf2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vsub(vint32m1_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vsub(vint32m2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vsub(vint32m4_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vsub(vint32m8_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vsub(vint64m1_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vsub(vint64m2_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vsub(vint64m4_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vsub(vint64m8_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vuint8mf8_t test___riscv_vsub(vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vsub(vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vsub(vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vsub(vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vsub(vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vsub(vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vsub(vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vsub(vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vsub(vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vsub(vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vsub(vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vsub(vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vsub(vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vsub(vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vsub(vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vsub(vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vsub(vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vsub(vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vsub(vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vsub(vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vsub(vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vsub(vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vint8mf8_t test___riscv_vsub(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vsub(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vsub(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vsub(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vsub(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vsub(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vsub(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vsub(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vsub(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vsub(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vsub(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vsub(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vsub(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vsub(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vsub(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vsub(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vsub(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vsub(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vsub(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vsub(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vsub(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vsub(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vuint8mf8_t test___riscv_vsub(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vsub(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vsub(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vsub(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vsub(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vsub(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vsub(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vsub(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vsub(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vsub(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vsub(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vsub(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vsub(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vsub(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vsub(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vsub(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vsub(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vsub(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vsub(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vsub(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vsub(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vsub(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_rv32-3.C
new file mode 100644
index 00000000000..e5e0982c4a7
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_rv32-3.C
@@ -0,0 +1,572 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsub(vint8mf8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vsub(vint8mf4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vsub(vint8mf2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vsub(vint8m1_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vsub(vint8m2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vsub(vint8m4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vsub(vint8m8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vsub(vint16mf4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vsub(vint16mf2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vsub(vint16m1_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vsub(vint16m2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vsub(vint16m4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vsub(vint16m8_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vsub(vint32mf2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vsub(vint32m1_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vsub(vint32m2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vsub(vint32m4_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vsub(vint32m8_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vsub(vint64m1_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vsub(vint64m2_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vsub(vint64m4_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vsub(vint64m8_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vuint8mf8_t test___riscv_vsub(vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vsub(vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vsub(vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vsub(vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vsub(vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vsub(vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vsub(vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vsub(vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vsub(vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vsub(vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vsub(vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vsub(vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vsub(vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vsub(vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vsub(vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vsub(vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vsub(vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vsub(vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vsub(vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vsub(vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vsub(vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vsub(vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vint8mf8_t test___riscv_vsub(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vsub(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vsub(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vsub(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vsub(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vsub(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vsub(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vsub(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vsub(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vsub(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vsub(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vsub(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vsub(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vsub(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vsub(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vsub(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vsub(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vsub(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vsub(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vsub(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vsub(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vsub(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vuint8mf8_t test___riscv_vsub(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vsub(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vsub(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vsub(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vsub(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vsub(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vsub(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vsub(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vsub(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vsub(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vsub(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vsub(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vsub(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vsub(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vsub(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vsub(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vsub(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vsub(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vsub(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vsub(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vsub(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vsub(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_rv64-1.C
new file mode 100644
index 00000000000..f602a79ed44
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_rv64-1.C
@@ -0,0 +1,578 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsub(vint8mf8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vsub(vint8mf4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vsub(vint8mf2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vsub(vint8m1_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vsub(vint8m2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vsub(vint8m4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vsub(vint8m8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vsub(vint16mf4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vsub(vint16mf2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vsub(vint16m1_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vsub(vint16m2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vsub(vint16m4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vsub(vint16m8_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vsub(vint32mf2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vsub(vint32m1_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vsub(vint32m2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vsub(vint32m4_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vsub(vint32m8_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vsub(vint64m1_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vsub(vint64m2_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vsub(vint64m4_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vsub(vint64m8_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vsub(vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vsub(vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vsub(vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vsub(vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vsub(vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vsub(vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vsub(vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vsub(vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vsub(vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vsub(vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vsub(vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vsub(vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vsub(vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vsub(vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vsub(vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vsub(vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vsub(vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vsub(vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vsub(vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vsub(vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vsub(vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vsub(vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,vl);
+}
+
+
+vint8mf8_t test___riscv_vsub(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vsub(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vsub(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vsub(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vsub(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vsub(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vsub(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vsub(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vsub(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vsub(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vsub(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vsub(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vsub(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vsub(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vsub(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vsub(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vsub(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vsub(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vsub(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vsub(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vsub(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vsub(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vsub(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vsub(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vsub(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vsub(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vsub(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vsub(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vsub(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vsub(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vsub(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vsub(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vsub(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vsub(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vsub(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vsub(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vsub(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vsub(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vsub(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vsub(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vsub(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vsub(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vsub(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vsub(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_rv64-2.C
new file mode 100644
index 00000000000..bfd2d6924a7
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_rv64-2.C
@@ -0,0 +1,578 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsub(vint8mf8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vsub(vint8mf4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vsub(vint8mf2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vsub(vint8m1_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vsub(vint8m2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vsub(vint8m4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vsub(vint8m8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vsub(vint16mf4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vsub(vint16mf2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vsub(vint16m1_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vsub(vint16m2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vsub(vint16m4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vsub(vint16m8_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vsub(vint32mf2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vsub(vint32m1_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vsub(vint32m2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vsub(vint32m4_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vsub(vint32m8_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vsub(vint64m1_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vsub(vint64m2_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vsub(vint64m4_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vsub(vint64m8_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vuint8mf8_t test___riscv_vsub(vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vsub(vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vsub(vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vsub(vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vsub(vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vsub(vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vsub(vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vsub(vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vsub(vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vsub(vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vsub(vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vsub(vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vsub(vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vsub(vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vsub(vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vsub(vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vsub(vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vsub(vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vsub(vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vsub(vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vsub(vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vsub(vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,31);
+}
+
+
+vint8mf8_t test___riscv_vsub(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vsub(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vsub(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vsub(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vsub(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vsub(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vsub(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vsub(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vsub(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vsub(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vsub(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vsub(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vsub(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vsub(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vsub(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vsub(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vsub(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vsub(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vsub(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vsub(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vsub(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vsub(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vuint8mf8_t test___riscv_vsub(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vsub(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vsub(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vsub(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vsub(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vsub(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vsub(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vsub(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vsub(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vsub(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vsub(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vsub(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vsub(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vsub(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vsub(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vsub(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vsub(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vsub(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vsub(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vsub(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vsub(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vsub(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_rv64-3.C
new file mode 100644
index 00000000000..391c1eae3d5
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_rv64-3.C
@@ -0,0 +1,578 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsub(vint8mf8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vsub(vint8mf4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vsub(vint8mf2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vsub(vint8m1_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vsub(vint8m2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vsub(vint8m4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vsub(vint8m8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vsub(vint16mf4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vsub(vint16mf2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vsub(vint16m1_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vsub(vint16m2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vsub(vint16m4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vsub(vint16m8_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vsub(vint32mf2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vsub(vint32m1_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vsub(vint32m2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vsub(vint32m4_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vsub(vint32m8_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vsub(vint64m1_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vsub(vint64m2_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vsub(vint64m4_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vsub(vint64m8_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vuint8mf8_t test___riscv_vsub(vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vsub(vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vsub(vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vsub(vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vsub(vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vsub(vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vsub(vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vsub(vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vsub(vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vsub(vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vsub(vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vsub(vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vsub(vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vsub(vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vsub(vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vsub(vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vsub(vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vsub(vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vsub(vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vsub(vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vsub(vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vsub(vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub(op1,op2,32);
+}
+
+
+vint8mf8_t test___riscv_vsub(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vsub(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vsub(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vsub(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vsub(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vsub(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vsub(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vsub(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vsub(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vsub(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vsub(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vsub(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vsub(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vsub(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vsub(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vsub(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vsub(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vsub(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vsub(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vsub(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vsub(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vsub(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vuint8mf8_t test___riscv_vsub(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vsub(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vsub(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vsub(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vsub(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vsub(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vsub(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vsub(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vsub(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vsub(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vsub(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vsub(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vsub(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vsub(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vsub(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vsub(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vsub(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vsub(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vsub(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vsub(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vsub(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vsub(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub(mask,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tu_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tu_rv32-1.C
new file mode 100644
index 00000000000..be890dfe844
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tu_rv32-1.C
@@ -0,0 +1,289 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsub_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vsub_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vsub_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vsub_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vsub_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vsub_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vsub_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vsub_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vsub_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vsub_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vsub_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vsub_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vsub_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vsub_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vsub_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vsub_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vsub_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vsub_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vsub_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vsub_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vsub_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vsub_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vsub_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vsub_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vsub_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vsub_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vsub_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vsub_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vsub_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vsub_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vsub_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vsub_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vsub_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vsub_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vsub_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vsub_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vsub_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vsub_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vsub_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vsub_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vsub_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vsub_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vsub_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vsub_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tu_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tu_rv32-2.C
new file mode 100644
index 00000000000..590e02e326c
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tu_rv32-2.C
@@ -0,0 +1,289 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsub_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vsub_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vsub_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vsub_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vsub_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vsub_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vsub_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vsub_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vsub_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vsub_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vsub_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vsub_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vsub_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vsub_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vsub_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vsub_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vsub_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vsub_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vsub_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vsub_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vsub_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vsub_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vuint8mf8_t test___riscv_vsub_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vsub_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vsub_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vsub_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vsub_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vsub_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vsub_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vsub_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vsub_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vsub_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vsub_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vsub_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vsub_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vsub_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vsub_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vsub_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vsub_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vsub_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vsub_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vsub_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vsub_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vsub_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tu_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tu_rv32-3.C
new file mode 100644
index 00000000000..ef82b81ba0f
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tu_rv32-3.C
@@ -0,0 +1,289 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsub_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vsub_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vsub_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vsub_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vsub_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vsub_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vsub_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vsub_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vsub_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vsub_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vsub_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vsub_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vsub_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vsub_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vsub_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vsub_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vsub_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vsub_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vsub_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vsub_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vsub_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vsub_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vuint8mf8_t test___riscv_vsub_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vsub_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vsub_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vsub_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vsub_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vsub_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vsub_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vsub_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vsub_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vsub_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vsub_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vsub_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vsub_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vsub_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vsub_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vsub_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vsub_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vsub_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vsub_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vsub_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vsub_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vsub_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tu_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tu_rv64-1.C
new file mode 100644
index 00000000000..c6105afc9d6
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tu_rv64-1.C
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsub_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vsub_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vsub_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vsub_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vsub_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vsub_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vsub_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vsub_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vsub_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vsub_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vsub_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vsub_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vsub_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vsub_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vsub_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vsub_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vsub_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vsub_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vsub_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vsub_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vsub_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vsub_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vsub_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vsub_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vsub_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vsub_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vsub_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vsub_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vsub_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vsub_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vsub_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vsub_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vsub_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vsub_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vsub_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vsub_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vsub_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vsub_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vsub_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vsub_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vsub_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vsub_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vsub_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vsub_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tu_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tu_rv64-2.C
new file mode 100644
index 00000000000..cb37b528de9
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tu_rv64-2.C
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsub_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vsub_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vsub_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vsub_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vsub_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vsub_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vsub_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vsub_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vsub_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vsub_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vsub_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vsub_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vsub_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vsub_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vsub_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vsub_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vsub_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vsub_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vsub_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vsub_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vsub_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vsub_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vuint8mf8_t test___riscv_vsub_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vsub_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vsub_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vsub_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vsub_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vsub_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vsub_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vsub_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vsub_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vsub_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vsub_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vsub_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vsub_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vsub_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vsub_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vsub_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vsub_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vsub_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vsub_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vsub_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vsub_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vsub_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tu_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tu_rv64-3.C
new file mode 100644
index 00000000000..23927091edb
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tu_rv64-3.C
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsub_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vsub_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vsub_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vsub_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vsub_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vsub_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vsub_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vsub_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vsub_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vsub_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vsub_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vsub_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vsub_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vsub_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vsub_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vsub_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vsub_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vsub_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vsub_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vsub_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vsub_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vsub_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vuint8mf8_t test___riscv_vsub_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vsub_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vsub_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vsub_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vsub_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vsub_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vsub_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vsub_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vsub_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vsub_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vsub_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vsub_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vsub_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vsub_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vsub_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vsub_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vsub_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vsub_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vsub_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vsub_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vsub_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vsub_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_tu(merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tum_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tum_rv32-1.C
new file mode 100644
index 00000000000..9863520e23c
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tum_rv32-1.C
@@ -0,0 +1,289 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsub_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vsub_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vsub_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vsub_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vsub_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vsub_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vsub_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vsub_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vsub_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vsub_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vsub_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vsub_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vsub_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vsub_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vsub_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vsub_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vsub_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vsub_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vsub_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vsub_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vsub_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vsub_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vsub_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vsub_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vsub_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vsub_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vsub_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vsub_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vsub_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vsub_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vsub_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vsub_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vsub_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vsub_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vsub_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vsub_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vsub_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vsub_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vsub_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vsub_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vsub_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vsub_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vsub_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vsub_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tum_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tum_rv32-2.C
new file mode 100644
index 00000000000..45797e4e46f
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tum_rv32-2.C
@@ -0,0 +1,289 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsub_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vsub_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vsub_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vsub_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vsub_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vsub_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vsub_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vsub_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vsub_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vsub_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vsub_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vsub_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vsub_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vsub_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vsub_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vsub_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vsub_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vsub_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vsub_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vsub_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vsub_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vsub_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf8_t test___riscv_vsub_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vsub_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vsub_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vsub_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vsub_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vsub_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vsub_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vsub_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vsub_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vsub_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vsub_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vsub_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vsub_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vsub_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vsub_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vsub_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vsub_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vsub_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vsub_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vsub_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vsub_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vsub_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tum_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tum_rv32-3.C
new file mode 100644
index 00000000000..873d672b213
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tum_rv32-3.C
@@ -0,0 +1,289 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsub_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vsub_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vsub_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vsub_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vsub_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vsub_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vsub_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vsub_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vsub_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vsub_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vsub_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vsub_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vsub_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vsub_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vsub_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vsub_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vsub_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vsub_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vsub_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vsub_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vsub_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vsub_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf8_t test___riscv_vsub_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vsub_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vsub_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vsub_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vsub_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vsub_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vsub_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vsub_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vsub_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vsub_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vsub_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vsub_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vsub_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vsub_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vsub_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vsub_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vsub_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vsub_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vsub_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vsub_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vsub_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vsub_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tum_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tum_rv64-1.C
new file mode 100644
index 00000000000..1f736a0515c
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tum_rv64-1.C
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsub_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vsub_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vsub_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vsub_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vsub_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vsub_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vsub_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vsub_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vsub_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vsub_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vsub_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vsub_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vsub_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vsub_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vsub_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vsub_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vsub_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vsub_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vsub_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vsub_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vsub_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vsub_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vsub_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vsub_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vsub_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vsub_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vsub_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vsub_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vsub_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vsub_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vsub_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vsub_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vsub_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vsub_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vsub_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vsub_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vsub_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vsub_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vsub_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vsub_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vsub_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vsub_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vsub_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vsub_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tum_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tum_rv64-2.C
new file mode 100644
index 00000000000..965a40b659d
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tum_rv64-2.C
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsub_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vsub_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vsub_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vsub_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vsub_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vsub_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vsub_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vsub_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vsub_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vsub_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vsub_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vsub_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vsub_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vsub_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vsub_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vsub_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vsub_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vsub_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vsub_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vsub_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vsub_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vsub_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf8_t test___riscv_vsub_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vsub_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vsub_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vsub_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vsub_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vsub_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vsub_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vsub_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vsub_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vsub_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vsub_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vsub_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vsub_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vsub_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vsub_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vsub_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vsub_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vsub_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vsub_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vsub_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vsub_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vsub_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tum_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tum_rv64-3.C
new file mode 100644
index 00000000000..53e99f5e766
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tum_rv64-3.C
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsub_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vsub_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vsub_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vsub_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vsub_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vsub_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vsub_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vsub_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vsub_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vsub_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vsub_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vsub_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vsub_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vsub_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vsub_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vsub_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vsub_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vsub_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vsub_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vsub_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vsub_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vsub_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf8_t test___riscv_vsub_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vsub_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vsub_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vsub_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vsub_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vsub_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vsub_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vsub_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vsub_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vsub_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vsub_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vsub_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vsub_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vsub_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vsub_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vsub_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vsub_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vsub_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vsub_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vsub_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vsub_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vsub_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_tum(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tumu_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tumu_rv32-1.C
new file mode 100644
index 00000000000..44c1d048c33
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tumu_rv32-1.C
@@ -0,0 +1,289 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsub_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vsub_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vsub_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vsub_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vsub_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vsub_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vsub_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vsub_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vsub_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vsub_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vsub_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vsub_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vsub_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vsub_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vsub_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vsub_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vsub_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vsub_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vsub_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vsub_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vsub_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vsub_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vsub_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vsub_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vsub_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vsub_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vsub_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vsub_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vsub_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vsub_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vsub_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vsub_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vsub_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vsub_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vsub_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vsub_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vsub_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vsub_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vsub_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vsub_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vsub_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vsub_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vsub_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vsub_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tumu_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tumu_rv32-2.C
new file mode 100644
index 00000000000..fa4a97f70ec
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tumu_rv32-2.C
@@ -0,0 +1,289 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsub_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vsub_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vsub_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vsub_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vsub_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vsub_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vsub_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vsub_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vsub_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vsub_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vsub_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vsub_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vsub_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vsub_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vsub_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vsub_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vsub_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vsub_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vsub_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vsub_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vsub_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vsub_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf8_t test___riscv_vsub_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vsub_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vsub_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vsub_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vsub_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vsub_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vsub_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vsub_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vsub_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vsub_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vsub_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vsub_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vsub_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vsub_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vsub_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vsub_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vsub_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vsub_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vsub_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vsub_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vsub_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vsub_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tumu_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tumu_rv32-3.C
new file mode 100644
index 00000000000..e23fb659827
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tumu_rv32-3.C
@@ -0,0 +1,289 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsub_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vsub_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vsub_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vsub_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vsub_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vsub_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vsub_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vsub_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vsub_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vsub_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vsub_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vsub_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vsub_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vsub_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vsub_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vsub_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vsub_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vsub_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vsub_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vsub_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vsub_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vsub_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf8_t test___riscv_vsub_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vsub_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vsub_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vsub_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vsub_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vsub_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vsub_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vsub_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vsub_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vsub_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vsub_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vsub_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vsub_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vsub_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vsub_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vsub_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vsub_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vsub_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vsub_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vsub_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vsub_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vsub_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsub\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 8 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tumu_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tumu_rv64-1.C
new file mode 100644
index 00000000000..6f90d3595b2
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tumu_rv64-1.C
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsub_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vsub_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vsub_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vsub_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vsub_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vsub_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vsub_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vsub_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vsub_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vsub_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vsub_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vsub_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vsub_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vsub_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vsub_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vsub_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vsub_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vsub_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vsub_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vsub_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vsub_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vsub_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vsub_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vsub_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vsub_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vsub_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vsub_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vsub_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vsub_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vsub_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vsub_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vsub_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vsub_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vsub_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vsub_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vsub_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vsub_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vsub_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vsub_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vsub_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vsub_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vsub_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vsub_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vsub_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tumu_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tumu_rv64-2.C
new file mode 100644
index 00000000000..cc5b52b32db
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tumu_rv64-2.C
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsub_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vsub_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vsub_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vsub_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vsub_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vsub_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vsub_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vsub_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vsub_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vsub_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vsub_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vsub_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vsub_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vsub_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vsub_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vsub_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vsub_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vsub_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vsub_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vsub_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vsub_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vsub_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf8_t test___riscv_vsub_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vsub_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vsub_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vsub_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vsub_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vsub_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vsub_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vsub_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vsub_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vsub_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vsub_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vsub_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vsub_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vsub_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vsub_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vsub_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vsub_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vsub_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vsub_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vsub_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vsub_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vsub_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tumu_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tumu_rv64-3.C
new file mode 100644
index 00000000000..899316f4ef8
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_tumu_rv64-3.C
@@ -0,0 +1,292 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vsub_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vsub_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vsub_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vsub_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vsub_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vsub_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vsub_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vsub_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vsub_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vsub_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vsub_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vsub_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vsub_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vsub_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vsub_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vsub_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vsub_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vsub_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vsub_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vsub_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vsub_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vsub_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf8_t test___riscv_vsub_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vsub_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vsub_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vsub_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vsub_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vsub_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vsub_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vsub_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vsub_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vsub_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vsub_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vsub_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vsub_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vsub_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vsub_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vsub_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vsub_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vsub_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vsub_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vsub_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vsub_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vsub_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vsub_tumu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vsub\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 2 } } */
--
2.36.1
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