* [PATCH] RISC-V: Add vremu.vx C API tests
@ 2023-02-03 7:10 juzhe.zhong
0 siblings, 0 replies; 2+ messages in thread
From: juzhe.zhong @ 2023-02-03 7:10 UTC (permalink / raw)
To: gcc-patches; +Cc: kito.cheng, Ju-Zhe Zhong
From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vremu_vx_m_rv32-1.c: New test.
* gcc.target/riscv/rvv/base/vremu_vx_m_rv32-2.c: New test.
* gcc.target/riscv/rvv/base/vremu_vx_m_rv32-3.c: New test.
* gcc.target/riscv/rvv/base/vremu_vx_m_rv64-1.c: New test.
* gcc.target/riscv/rvv/base/vremu_vx_m_rv64-2.c: New test.
* gcc.target/riscv/rvv/base/vremu_vx_m_rv64-3.c: New test.
* gcc.target/riscv/rvv/base/vremu_vx_mu_rv32-1.c: New test.
* gcc.target/riscv/rvv/base/vremu_vx_mu_rv32-2.c: New test.
* gcc.target/riscv/rvv/base/vremu_vx_mu_rv32-3.c: New test.
* gcc.target/riscv/rvv/base/vremu_vx_mu_rv64-1.c: New test.
* gcc.target/riscv/rvv/base/vremu_vx_mu_rv64-2.c: New test.
* gcc.target/riscv/rvv/base/vremu_vx_mu_rv64-3.c: New test.
* gcc.target/riscv/rvv/base/vremu_vx_rv32-1.c: New test.
* gcc.target/riscv/rvv/base/vremu_vx_rv32-2.c: New test.
* gcc.target/riscv/rvv/base/vremu_vx_rv32-3.c: New test.
* gcc.target/riscv/rvv/base/vremu_vx_rv64-1.c: New test.
* gcc.target/riscv/rvv/base/vremu_vx_rv64-2.c: New test.
* gcc.target/riscv/rvv/base/vremu_vx_rv64-3.c: New test.
* gcc.target/riscv/rvv/base/vremu_vx_tu_rv32-1.c: New test.
* gcc.target/riscv/rvv/base/vremu_vx_tu_rv32-2.c: New test.
* gcc.target/riscv/rvv/base/vremu_vx_tu_rv32-3.c: New test.
* gcc.target/riscv/rvv/base/vremu_vx_tu_rv64-1.c: New test.
* gcc.target/riscv/rvv/base/vremu_vx_tu_rv64-2.c: New test.
* gcc.target/riscv/rvv/base/vremu_vx_tu_rv64-3.c: New test.
* gcc.target/riscv/rvv/base/vremu_vx_tum_rv32-1.c: New test.
* gcc.target/riscv/rvv/base/vremu_vx_tum_rv32-2.c: New test.
* gcc.target/riscv/rvv/base/vremu_vx_tum_rv32-3.c: New test.
* gcc.target/riscv/rvv/base/vremu_vx_tum_rv64-1.c: New test.
* gcc.target/riscv/rvv/base/vremu_vx_tum_rv64-2.c: New test.
* gcc.target/riscv/rvv/base/vremu_vx_tum_rv64-3.c: New test.
* gcc.target/riscv/rvv/base/vremu_vx_tumu_rv32-1.c: New test.
* gcc.target/riscv/rvv/base/vremu_vx_tumu_rv32-2.c: New test.
* gcc.target/riscv/rvv/base/vremu_vx_tumu_rv32-3.c: New test.
* gcc.target/riscv/rvv/base/vremu_vx_tumu_rv64-1.c: New test.
* gcc.target/riscv/rvv/base/vremu_vx_tumu_rv64-2.c: New test.
* gcc.target/riscv/rvv/base/vremu_vx_tumu_rv64-3.c: New test.
---
.../riscv/rvv/base/vremu_vx_m_rv32-1.c | 157 +++++++++++++++++
.../riscv/rvv/base/vremu_vx_m_rv32-2.c | 157 +++++++++++++++++
.../riscv/rvv/base/vremu_vx_m_rv32-3.c | 157 +++++++++++++++++
.../riscv/rvv/base/vremu_vx_m_rv64-1.c | 160 ++++++++++++++++++
.../riscv/rvv/base/vremu_vx_m_rv64-2.c | 160 ++++++++++++++++++
.../riscv/rvv/base/vremu_vx_m_rv64-3.c | 160 ++++++++++++++++++
.../riscv/rvv/base/vremu_vx_mu_rv32-1.c | 157 +++++++++++++++++
.../riscv/rvv/base/vremu_vx_mu_rv32-2.c | 157 +++++++++++++++++
.../riscv/rvv/base/vremu_vx_mu_rv32-3.c | 157 +++++++++++++++++
.../riscv/rvv/base/vremu_vx_mu_rv64-1.c | 160 ++++++++++++++++++
.../riscv/rvv/base/vremu_vx_mu_rv64-2.c | 160 ++++++++++++++++++
.../riscv/rvv/base/vremu_vx_mu_rv64-3.c | 160 ++++++++++++++++++
.../riscv/rvv/base/vremu_vx_rv32-1.c | 157 +++++++++++++++++
.../riscv/rvv/base/vremu_vx_rv32-2.c | 157 +++++++++++++++++
.../riscv/rvv/base/vremu_vx_rv32-3.c | 157 +++++++++++++++++
.../riscv/rvv/base/vremu_vx_rv64-1.c | 160 ++++++++++++++++++
.../riscv/rvv/base/vremu_vx_rv64-2.c | 160 ++++++++++++++++++
.../riscv/rvv/base/vremu_vx_rv64-3.c | 160 ++++++++++++++++++
.../riscv/rvv/base/vremu_vx_tu_rv32-1.c | 157 +++++++++++++++++
.../riscv/rvv/base/vremu_vx_tu_rv32-2.c | 157 +++++++++++++++++
.../riscv/rvv/base/vremu_vx_tu_rv32-3.c | 157 +++++++++++++++++
.../riscv/rvv/base/vremu_vx_tu_rv64-1.c | 160 ++++++++++++++++++
.../riscv/rvv/base/vremu_vx_tu_rv64-2.c | 160 ++++++++++++++++++
.../riscv/rvv/base/vremu_vx_tu_rv64-3.c | 160 ++++++++++++++++++
.../riscv/rvv/base/vremu_vx_tum_rv32-1.c | 157 +++++++++++++++++
.../riscv/rvv/base/vremu_vx_tum_rv32-2.c | 157 +++++++++++++++++
.../riscv/rvv/base/vremu_vx_tum_rv32-3.c | 157 +++++++++++++++++
.../riscv/rvv/base/vremu_vx_tum_rv64-1.c | 160 ++++++++++++++++++
.../riscv/rvv/base/vremu_vx_tum_rv64-2.c | 160 ++++++++++++++++++
.../riscv/rvv/base/vremu_vx_tum_rv64-3.c | 160 ++++++++++++++++++
.../riscv/rvv/base/vremu_vx_tumu_rv32-1.c | 157 +++++++++++++++++
.../riscv/rvv/base/vremu_vx_tumu_rv32-2.c | 157 +++++++++++++++++
.../riscv/rvv/base/vremu_vx_tumu_rv32-3.c | 157 +++++++++++++++++
.../riscv/rvv/base/vremu_vx_tumu_rv64-1.c | 160 ++++++++++++++++++
.../riscv/rvv/base/vremu_vx_tumu_rv64-2.c | 160 ++++++++++++++++++
.../riscv/rvv/base/vremu_vx_tumu_rv64-3.c | 160 ++++++++++++++++++
36 files changed, 5706 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_m_rv32-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_m_rv32-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_m_rv32-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_m_rv64-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_m_rv64-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_m_rv64-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_mu_rv32-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_mu_rv32-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_mu_rv32-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_mu_rv64-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_mu_rv64-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_mu_rv64-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_rv32-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_rv32-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_rv32-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_rv64-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_rv64-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_rv64-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tu_rv32-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tu_rv32-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tu_rv32-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tu_rv64-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tu_rv64-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tu_rv64-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tum_rv32-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tum_rv32-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tum_rv32-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tum_rv64-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tum_rv64-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tum_rv64-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tumu_rv32-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tumu_rv32-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tumu_rv32-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tumu_rv64-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tumu_rv64-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tumu_rv64-3.c
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_m_rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_m_rv32-1.c
new file mode 100644
index 00000000000..a74cf559db8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_m_rv32-1.c
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vremu_vx_u8mf8_m(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf8_m(mask,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vremu_vx_u8mf4_m(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf4_m(mask,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vremu_vx_u8mf2_m(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf2_m(mask,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vremu_vx_u8m1_m(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m1_m(mask,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vremu_vx_u8m2_m(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m2_m(mask,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vremu_vx_u8m4_m(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m4_m(mask,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vremu_vx_u8m8_m(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m8_m(mask,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vremu_vx_u16mf4_m(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16mf4_m(mask,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vremu_vx_u16mf2_m(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16mf2_m(mask,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vremu_vx_u16m1_m(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m1_m(mask,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vremu_vx_u16m2_m(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m2_m(mask,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vremu_vx_u16m4_m(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m4_m(mask,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vremu_vx_u16m8_m(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m8_m(mask,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vremu_vx_u32mf2_m(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32mf2_m(mask,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vremu_vx_u32m1_m(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m1_m(mask,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vremu_vx_u32m2_m(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m2_m(mask,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vremu_vx_u32m4_m(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m4_m(mask,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vremu_vx_u32m8_m(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m8_m(mask,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vremu_vx_u64m1_m(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m1_m(mask,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vremu_vx_u64m2_m(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m2_m(mask,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vremu_vx_u64m4_m(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m4_m(mask,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vremu_vx_u64m8_m(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m8_m(mask,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vremu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_m_rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_m_rv32-2.c
new file mode 100644
index 00000000000..dda33411ab9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_m_rv32-2.c
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vremu_vx_u8mf8_m(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf8_m(mask,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vremu_vx_u8mf4_m(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf4_m(mask,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vremu_vx_u8mf2_m(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf2_m(mask,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vremu_vx_u8m1_m(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m1_m(mask,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vremu_vx_u8m2_m(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m2_m(mask,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vremu_vx_u8m4_m(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m4_m(mask,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vremu_vx_u8m8_m(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m8_m(mask,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vremu_vx_u16mf4_m(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16mf4_m(mask,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vremu_vx_u16mf2_m(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16mf2_m(mask,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vremu_vx_u16m1_m(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m1_m(mask,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vremu_vx_u16m2_m(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m2_m(mask,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vremu_vx_u16m4_m(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m4_m(mask,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vremu_vx_u16m8_m(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m8_m(mask,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vremu_vx_u32mf2_m(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32mf2_m(mask,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vremu_vx_u32m1_m(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m1_m(mask,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vremu_vx_u32m2_m(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m2_m(mask,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vremu_vx_u32m4_m(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m4_m(mask,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vremu_vx_u32m8_m(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m8_m(mask,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vremu_vx_u64m1_m(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m1_m(mask,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vremu_vx_u64m2_m(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m2_m(mask,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vremu_vx_u64m4_m(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m4_m(mask,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vremu_vx_u64m8_m(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m8_m(mask,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vremu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_m_rv32-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_m_rv32-3.c
new file mode 100644
index 00000000000..21b6e41f41e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_m_rv32-3.c
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vremu_vx_u8mf8_m(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf8_m(mask,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vremu_vx_u8mf4_m(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf4_m(mask,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vremu_vx_u8mf2_m(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf2_m(mask,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vremu_vx_u8m1_m(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m1_m(mask,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vremu_vx_u8m2_m(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m2_m(mask,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vremu_vx_u8m4_m(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m4_m(mask,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vremu_vx_u8m8_m(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m8_m(mask,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vremu_vx_u16mf4_m(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16mf4_m(mask,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vremu_vx_u16mf2_m(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16mf2_m(mask,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vremu_vx_u16m1_m(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m1_m(mask,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vremu_vx_u16m2_m(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m2_m(mask,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vremu_vx_u16m4_m(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m4_m(mask,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vremu_vx_u16m8_m(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m8_m(mask,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vremu_vx_u32mf2_m(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32mf2_m(mask,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vremu_vx_u32m1_m(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m1_m(mask,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vremu_vx_u32m2_m(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m2_m(mask,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vremu_vx_u32m4_m(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m4_m(mask,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vremu_vx_u32m8_m(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m8_m(mask,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vremu_vx_u64m1_m(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m1_m(mask,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vremu_vx_u64m2_m(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m2_m(mask,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vremu_vx_u64m4_m(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m4_m(mask,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vremu_vx_u64m8_m(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m8_m(mask,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vremu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_m_rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_m_rv64-1.c
new file mode 100644
index 00000000000..330ddafde33
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_m_rv64-1.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vremu_vx_u8mf8_m(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf8_m(mask,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vremu_vx_u8mf4_m(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf4_m(mask,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vremu_vx_u8mf2_m(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf2_m(mask,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vremu_vx_u8m1_m(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m1_m(mask,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vremu_vx_u8m2_m(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m2_m(mask,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vremu_vx_u8m4_m(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m4_m(mask,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vremu_vx_u8m8_m(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m8_m(mask,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vremu_vx_u16mf4_m(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16mf4_m(mask,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vremu_vx_u16mf2_m(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16mf2_m(mask,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vremu_vx_u16m1_m(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m1_m(mask,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vremu_vx_u16m2_m(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m2_m(mask,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vremu_vx_u16m4_m(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m4_m(mask,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vremu_vx_u16m8_m(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m8_m(mask,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vremu_vx_u32mf2_m(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32mf2_m(mask,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vremu_vx_u32m1_m(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m1_m(mask,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vremu_vx_u32m2_m(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m2_m(mask,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vremu_vx_u32m4_m(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m4_m(mask,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vremu_vx_u32m8_m(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m8_m(mask,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vremu_vx_u64m1_m(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m1_m(mask,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vremu_vx_u64m2_m(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m2_m(mask,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vremu_vx_u64m4_m(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m4_m(mask,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vremu_vx_u64m8_m(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m8_m(mask,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_m_rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_m_rv64-2.c
new file mode 100644
index 00000000000..83a0516f5c4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_m_rv64-2.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vremu_vx_u8mf8_m(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf8_m(mask,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vremu_vx_u8mf4_m(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf4_m(mask,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vremu_vx_u8mf2_m(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf2_m(mask,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vremu_vx_u8m1_m(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m1_m(mask,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vremu_vx_u8m2_m(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m2_m(mask,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vremu_vx_u8m4_m(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m4_m(mask,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vremu_vx_u8m8_m(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m8_m(mask,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vremu_vx_u16mf4_m(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16mf4_m(mask,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vremu_vx_u16mf2_m(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16mf2_m(mask,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vremu_vx_u16m1_m(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m1_m(mask,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vremu_vx_u16m2_m(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m2_m(mask,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vremu_vx_u16m4_m(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m4_m(mask,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vremu_vx_u16m8_m(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m8_m(mask,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vremu_vx_u32mf2_m(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32mf2_m(mask,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vremu_vx_u32m1_m(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m1_m(mask,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vremu_vx_u32m2_m(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m2_m(mask,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vremu_vx_u32m4_m(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m4_m(mask,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vremu_vx_u32m8_m(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m8_m(mask,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vremu_vx_u64m1_m(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m1_m(mask,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vremu_vx_u64m2_m(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m2_m(mask,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vremu_vx_u64m4_m(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m4_m(mask,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vremu_vx_u64m8_m(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m8_m(mask,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_m_rv64-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_m_rv64-3.c
new file mode 100644
index 00000000000..d789728a94d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_m_rv64-3.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vremu_vx_u8mf8_m(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf8_m(mask,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vremu_vx_u8mf4_m(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf4_m(mask,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vremu_vx_u8mf2_m(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf2_m(mask,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vremu_vx_u8m1_m(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m1_m(mask,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vremu_vx_u8m2_m(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m2_m(mask,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vremu_vx_u8m4_m(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m4_m(mask,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vremu_vx_u8m8_m(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m8_m(mask,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vremu_vx_u16mf4_m(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16mf4_m(mask,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vremu_vx_u16mf2_m(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16mf2_m(mask,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vremu_vx_u16m1_m(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m1_m(mask,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vremu_vx_u16m2_m(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m2_m(mask,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vremu_vx_u16m4_m(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m4_m(mask,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vremu_vx_u16m8_m(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m8_m(mask,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vremu_vx_u32mf2_m(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32mf2_m(mask,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vremu_vx_u32m1_m(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m1_m(mask,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vremu_vx_u32m2_m(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m2_m(mask,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vremu_vx_u32m4_m(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m4_m(mask,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vremu_vx_u32m8_m(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m8_m(mask,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vremu_vx_u64m1_m(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m1_m(mask,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vremu_vx_u64m2_m(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m2_m(mask,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vremu_vx_u64m4_m(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m4_m(mask,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vremu_vx_u64m8_m(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m8_m(mask,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_mu_rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_mu_rv32-1.c
new file mode 100644
index 00000000000..968116f904b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_mu_rv32-1.c
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vremu_vx_u8mf8_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vremu_vx_u8mf4_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vremu_vx_u8mf2_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vremu_vx_u8m1_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m1_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vremu_vx_u8m2_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vremu_vx_u8m4_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vremu_vx_u8m8_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vremu_vx_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16mf4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vremu_vx_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16mf2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vremu_vx_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m1_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vremu_vx_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vremu_vx_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vremu_vx_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vremu_vx_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32mf2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vremu_vx_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m1_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vremu_vx_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vremu_vx_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vremu_vx_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vremu_vx_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m1_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vremu_vx_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vremu_vx_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vremu_vx_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m8_mu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vremu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_mu_rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_mu_rv32-2.c
new file mode 100644
index 00000000000..d2b6c890c52
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_mu_rv32-2.c
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vremu_vx_u8mf8_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf8_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vremu_vx_u8mf4_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf4_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vremu_vx_u8mf2_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf2_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vremu_vx_u8m1_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m1_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vremu_vx_u8m2_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m2_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vremu_vx_u8m4_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m4_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vremu_vx_u8m8_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m8_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vremu_vx_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16mf4_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vremu_vx_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16mf2_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vremu_vx_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m1_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vremu_vx_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m2_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vremu_vx_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m4_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vremu_vx_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m8_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vremu_vx_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32mf2_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vremu_vx_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m1_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vremu_vx_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m2_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vremu_vx_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m4_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vremu_vx_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m8_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vremu_vx_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m1_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vremu_vx_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m2_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vremu_vx_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m4_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vremu_vx_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m8_mu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vremu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_mu_rv32-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_mu_rv32-3.c
new file mode 100644
index 00000000000..75f41825e0d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_mu_rv32-3.c
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vremu_vx_u8mf8_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf8_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vremu_vx_u8mf4_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf4_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vremu_vx_u8mf2_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf2_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vremu_vx_u8m1_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m1_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vremu_vx_u8m2_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m2_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vremu_vx_u8m4_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m4_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vremu_vx_u8m8_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m8_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vremu_vx_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16mf4_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vremu_vx_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16mf2_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vremu_vx_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m1_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vremu_vx_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m2_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vremu_vx_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m4_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vremu_vx_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m8_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vremu_vx_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32mf2_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vremu_vx_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m1_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vremu_vx_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m2_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vremu_vx_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m4_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vremu_vx_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m8_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vremu_vx_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m1_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vremu_vx_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m2_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vremu_vx_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m4_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vremu_vx_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m8_mu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vremu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_mu_rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_mu_rv64-1.c
new file mode 100644
index 00000000000..5dcdd7d85f8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_mu_rv64-1.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vremu_vx_u8mf8_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vremu_vx_u8mf4_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vremu_vx_u8mf2_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vremu_vx_u8m1_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m1_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vremu_vx_u8m2_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vremu_vx_u8m4_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vremu_vx_u8m8_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vremu_vx_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16mf4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vremu_vx_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16mf2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vremu_vx_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m1_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vremu_vx_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vremu_vx_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vremu_vx_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vremu_vx_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32mf2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vremu_vx_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m1_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vremu_vx_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vremu_vx_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vremu_vx_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vremu_vx_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m1_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vremu_vx_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vremu_vx_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vremu_vx_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m8_mu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_mu_rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_mu_rv64-2.c
new file mode 100644
index 00000000000..972429e14a3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_mu_rv64-2.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vremu_vx_u8mf8_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf8_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vremu_vx_u8mf4_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf4_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vremu_vx_u8mf2_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf2_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vremu_vx_u8m1_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m1_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vremu_vx_u8m2_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m2_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vremu_vx_u8m4_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m4_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vremu_vx_u8m8_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m8_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vremu_vx_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16mf4_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vremu_vx_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16mf2_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vremu_vx_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m1_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vremu_vx_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m2_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vremu_vx_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m4_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vremu_vx_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m8_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vremu_vx_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32mf2_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vremu_vx_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m1_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vremu_vx_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m2_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vremu_vx_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m4_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vremu_vx_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m8_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vremu_vx_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m1_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vremu_vx_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m2_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vremu_vx_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m4_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vremu_vx_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m8_mu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_mu_rv64-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_mu_rv64-3.c
new file mode 100644
index 00000000000..f163289ecc0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_mu_rv64-3.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vremu_vx_u8mf8_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf8_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vremu_vx_u8mf4_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf4_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vremu_vx_u8mf2_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf2_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vremu_vx_u8m1_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m1_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vremu_vx_u8m2_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m2_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vremu_vx_u8m4_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m4_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vremu_vx_u8m8_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m8_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vremu_vx_u16mf4_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16mf4_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vremu_vx_u16mf2_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16mf2_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vremu_vx_u16m1_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m1_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vremu_vx_u16m2_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m2_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vremu_vx_u16m4_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m4_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vremu_vx_u16m8_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m8_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vremu_vx_u32mf2_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32mf2_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vremu_vx_u32m1_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m1_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vremu_vx_u32m2_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m2_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vremu_vx_u32m4_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m4_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vremu_vx_u32m8_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m8_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vremu_vx_u64m1_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m1_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vremu_vx_u64m2_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m2_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vremu_vx_u64m4_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m4_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vremu_vx_u64m8_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m8_mu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_rv32-1.c
new file mode 100644
index 00000000000..40f0c3788f2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_rv32-1.c
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vremu_vx_u8mf8(vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf8(op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vremu_vx_u8mf4(vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf4(op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vremu_vx_u8mf2(vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf2(op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vremu_vx_u8m1(vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m1(op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vremu_vx_u8m2(vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m2(op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vremu_vx_u8m4(vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m4(op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vremu_vx_u8m8(vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m8(op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vremu_vx_u16mf4(vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16mf4(op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vremu_vx_u16mf2(vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16mf2(op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vremu_vx_u16m1(vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m1(op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vremu_vx_u16m2(vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m2(op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vremu_vx_u16m4(vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m4(op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vremu_vx_u16m8(vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m8(op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vremu_vx_u32mf2(vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32mf2(op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vremu_vx_u32m1(vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m1(op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vremu_vx_u32m2(vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m2(op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vremu_vx_u32m4(vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m4(op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vremu_vx_u32m8(vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m8(op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vremu_vx_u64m1(vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m1(op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vremu_vx_u64m2(vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m2(op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vremu_vx_u64m4(vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m4(op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vremu_vx_u64m8(vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m8(op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vremu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_rv32-2.c
new file mode 100644
index 00000000000..6c8ab1ec93f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_rv32-2.c
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vremu_vx_u8mf8(vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf8(op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vremu_vx_u8mf4(vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf4(op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vremu_vx_u8mf2(vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf2(op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vremu_vx_u8m1(vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m1(op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vremu_vx_u8m2(vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m2(op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vremu_vx_u8m4(vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m4(op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vremu_vx_u8m8(vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m8(op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vremu_vx_u16mf4(vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16mf4(op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vremu_vx_u16mf2(vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16mf2(op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vremu_vx_u16m1(vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m1(op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vremu_vx_u16m2(vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m2(op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vremu_vx_u16m4(vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m4(op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vremu_vx_u16m8(vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m8(op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vremu_vx_u32mf2(vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32mf2(op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vremu_vx_u32m1(vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m1(op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vremu_vx_u32m2(vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m2(op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vremu_vx_u32m4(vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m4(op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vremu_vx_u32m8(vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m8(op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vremu_vx_u64m1(vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m1(op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vremu_vx_u64m2(vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m2(op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vremu_vx_u64m4(vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m4(op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vremu_vx_u64m8(vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m8(op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vremu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_rv32-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_rv32-3.c
new file mode 100644
index 00000000000..6b8ed956d55
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_rv32-3.c
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vremu_vx_u8mf8(vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf8(op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vremu_vx_u8mf4(vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf4(op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vremu_vx_u8mf2(vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf2(op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vremu_vx_u8m1(vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m1(op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vremu_vx_u8m2(vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m2(op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vremu_vx_u8m4(vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m4(op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vremu_vx_u8m8(vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m8(op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vremu_vx_u16mf4(vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16mf4(op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vremu_vx_u16mf2(vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16mf2(op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vremu_vx_u16m1(vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m1(op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vremu_vx_u16m2(vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m2(op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vremu_vx_u16m4(vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m4(op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vremu_vx_u16m8(vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m8(op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vremu_vx_u32mf2(vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32mf2(op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vremu_vx_u32m1(vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m1(op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vremu_vx_u32m2(vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m2(op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vremu_vx_u32m4(vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m4(op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vremu_vx_u32m8(vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m8(op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vremu_vx_u64m1(vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m1(op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vremu_vx_u64m2(vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m2(op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vremu_vx_u64m4(vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m4(op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vremu_vx_u64m8(vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m8(op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vremu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_rv64-1.c
new file mode 100644
index 00000000000..2d3fa952e41
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_rv64-1.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vremu_vx_u8mf8(vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf8(op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vremu_vx_u8mf4(vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf4(op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vremu_vx_u8mf2(vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf2(op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vremu_vx_u8m1(vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m1(op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vremu_vx_u8m2(vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m2(op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vremu_vx_u8m4(vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m4(op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vremu_vx_u8m8(vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m8(op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vremu_vx_u16mf4(vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16mf4(op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vremu_vx_u16mf2(vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16mf2(op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vremu_vx_u16m1(vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m1(op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vremu_vx_u16m2(vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m2(op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vremu_vx_u16m4(vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m4(op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vremu_vx_u16m8(vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m8(op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vremu_vx_u32mf2(vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32mf2(op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vremu_vx_u32m1(vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m1(op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vremu_vx_u32m2(vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m2(op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vremu_vx_u32m4(vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m4(op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vremu_vx_u32m8(vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m8(op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vremu_vx_u64m1(vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m1(op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vremu_vx_u64m2(vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m2(op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vremu_vx_u64m4(vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m4(op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vremu_vx_u64m8(vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m8(op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_rv64-2.c
new file mode 100644
index 00000000000..c78854d6b4c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_rv64-2.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vremu_vx_u8mf8(vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf8(op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vremu_vx_u8mf4(vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf4(op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vremu_vx_u8mf2(vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf2(op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vremu_vx_u8m1(vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m1(op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vremu_vx_u8m2(vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m2(op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vremu_vx_u8m4(vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m4(op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vremu_vx_u8m8(vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m8(op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vremu_vx_u16mf4(vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16mf4(op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vremu_vx_u16mf2(vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16mf2(op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vremu_vx_u16m1(vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m1(op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vremu_vx_u16m2(vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m2(op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vremu_vx_u16m4(vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m4(op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vremu_vx_u16m8(vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m8(op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vremu_vx_u32mf2(vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32mf2(op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vremu_vx_u32m1(vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m1(op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vremu_vx_u32m2(vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m2(op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vremu_vx_u32m4(vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m4(op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vremu_vx_u32m8(vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m8(op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vremu_vx_u64m1(vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m1(op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vremu_vx_u64m2(vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m2(op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vremu_vx_u64m4(vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m4(op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vremu_vx_u64m8(vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m8(op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_rv64-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_rv64-3.c
new file mode 100644
index 00000000000..8a14a0719ab
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_rv64-3.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vremu_vx_u8mf8(vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf8(op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vremu_vx_u8mf4(vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf4(op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vremu_vx_u8mf2(vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf2(op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vremu_vx_u8m1(vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m1(op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vremu_vx_u8m2(vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m2(op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vremu_vx_u8m4(vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m4(op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vremu_vx_u8m8(vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m8(op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vremu_vx_u16mf4(vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16mf4(op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vremu_vx_u16mf2(vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16mf2(op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vremu_vx_u16m1(vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m1(op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vremu_vx_u16m2(vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m2(op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vremu_vx_u16m4(vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m4(op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vremu_vx_u16m8(vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m8(op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vremu_vx_u32mf2(vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32mf2(op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vremu_vx_u32m1(vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m1(op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vremu_vx_u32m2(vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m2(op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vremu_vx_u32m4(vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m4(op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vremu_vx_u32m8(vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m8(op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vremu_vx_u64m1(vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m1(op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vremu_vx_u64m2(vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m2(op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vremu_vx_u64m4(vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m4(op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vremu_vx_u64m8(vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m8(op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tu_rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tu_rv32-1.c
new file mode 100644
index 00000000000..ea49e42f59f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tu_rv32-1.c
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vremu_vx_u8mf8_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf8_tu(merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vremu_vx_u8mf4_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf4_tu(merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vremu_vx_u8mf2_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf2_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vremu_vx_u8m1_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m1_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vremu_vx_u8m2_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m2_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vremu_vx_u8m4_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m4_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vremu_vx_u8m8_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m8_tu(merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vremu_vx_u16mf4_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16mf4_tu(merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vremu_vx_u16mf2_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16mf2_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vremu_vx_u16m1_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m1_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vremu_vx_u16m2_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m2_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vremu_vx_u16m4_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m4_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vremu_vx_u16m8_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m8_tu(merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vremu_vx_u32mf2_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32mf2_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vremu_vx_u32m1_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m1_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vremu_vx_u32m2_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m2_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vremu_vx_u32m4_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m4_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vremu_vx_u32m8_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m8_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vremu_vx_u64m1_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m1_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vremu_vx_u64m2_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m2_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vremu_vx_u64m4_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m4_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vremu_vx_u64m8_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m8_tu(merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vremu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tu_rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tu_rv32-2.c
new file mode 100644
index 00000000000..6801534f96c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tu_rv32-2.c
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vremu_vx_u8mf8_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf8_tu(merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vremu_vx_u8mf4_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf4_tu(merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vremu_vx_u8mf2_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf2_tu(merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vremu_vx_u8m1_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m1_tu(merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vremu_vx_u8m2_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m2_tu(merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vremu_vx_u8m4_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m4_tu(merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vremu_vx_u8m8_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m8_tu(merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vremu_vx_u16mf4_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16mf4_tu(merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vremu_vx_u16mf2_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16mf2_tu(merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vremu_vx_u16m1_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m1_tu(merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vremu_vx_u16m2_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m2_tu(merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vremu_vx_u16m4_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m4_tu(merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vremu_vx_u16m8_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m8_tu(merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vremu_vx_u32mf2_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32mf2_tu(merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vremu_vx_u32m1_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m1_tu(merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vremu_vx_u32m2_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m2_tu(merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vremu_vx_u32m4_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m4_tu(merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vremu_vx_u32m8_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m8_tu(merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vremu_vx_u64m1_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m1_tu(merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vremu_vx_u64m2_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m2_tu(merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vremu_vx_u64m4_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m4_tu(merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vremu_vx_u64m8_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m8_tu(merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vremu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tu_rv32-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tu_rv32-3.c
new file mode 100644
index 00000000000..470bc7c144d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tu_rv32-3.c
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vremu_vx_u8mf8_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf8_tu(merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vremu_vx_u8mf4_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf4_tu(merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vremu_vx_u8mf2_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf2_tu(merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vremu_vx_u8m1_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m1_tu(merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vremu_vx_u8m2_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m2_tu(merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vremu_vx_u8m4_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m4_tu(merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vremu_vx_u8m8_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m8_tu(merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vremu_vx_u16mf4_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16mf4_tu(merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vremu_vx_u16mf2_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16mf2_tu(merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vremu_vx_u16m1_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m1_tu(merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vremu_vx_u16m2_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m2_tu(merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vremu_vx_u16m4_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m4_tu(merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vremu_vx_u16m8_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m8_tu(merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vremu_vx_u32mf2_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32mf2_tu(merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vremu_vx_u32m1_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m1_tu(merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vremu_vx_u32m2_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m2_tu(merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vremu_vx_u32m4_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m4_tu(merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vremu_vx_u32m8_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m8_tu(merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vremu_vx_u64m1_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m1_tu(merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vremu_vx_u64m2_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m2_tu(merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vremu_vx_u64m4_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m4_tu(merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vremu_vx_u64m8_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m8_tu(merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vremu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tu_rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tu_rv64-1.c
new file mode 100644
index 00000000000..118b35587a7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tu_rv64-1.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vremu_vx_u8mf8_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf8_tu(merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vremu_vx_u8mf4_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf4_tu(merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vremu_vx_u8mf2_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf2_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vremu_vx_u8m1_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m1_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vremu_vx_u8m2_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m2_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vremu_vx_u8m4_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m4_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vremu_vx_u8m8_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m8_tu(merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vremu_vx_u16mf4_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16mf4_tu(merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vremu_vx_u16mf2_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16mf2_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vremu_vx_u16m1_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m1_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vremu_vx_u16m2_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m2_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vremu_vx_u16m4_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m4_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vremu_vx_u16m8_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m8_tu(merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vremu_vx_u32mf2_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32mf2_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vremu_vx_u32m1_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m1_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vremu_vx_u32m2_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m2_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vremu_vx_u32m4_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m4_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vremu_vx_u32m8_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m8_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vremu_vx_u64m1_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m1_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vremu_vx_u64m2_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m2_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vremu_vx_u64m4_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m4_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vremu_vx_u64m8_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m8_tu(merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tu_rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tu_rv64-2.c
new file mode 100644
index 00000000000..af419dbe5e4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tu_rv64-2.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vremu_vx_u8mf8_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf8_tu(merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vremu_vx_u8mf4_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf4_tu(merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vremu_vx_u8mf2_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf2_tu(merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vremu_vx_u8m1_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m1_tu(merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vremu_vx_u8m2_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m2_tu(merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vremu_vx_u8m4_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m4_tu(merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vremu_vx_u8m8_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m8_tu(merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vremu_vx_u16mf4_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16mf4_tu(merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vremu_vx_u16mf2_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16mf2_tu(merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vremu_vx_u16m1_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m1_tu(merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vremu_vx_u16m2_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m2_tu(merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vremu_vx_u16m4_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m4_tu(merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vremu_vx_u16m8_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m8_tu(merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vremu_vx_u32mf2_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32mf2_tu(merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vremu_vx_u32m1_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m1_tu(merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vremu_vx_u32m2_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m2_tu(merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vremu_vx_u32m4_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m4_tu(merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vremu_vx_u32m8_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m8_tu(merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vremu_vx_u64m1_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m1_tu(merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vremu_vx_u64m2_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m2_tu(merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vremu_vx_u64m4_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m4_tu(merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vremu_vx_u64m8_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m8_tu(merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tu_rv64-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tu_rv64-3.c
new file mode 100644
index 00000000000..70d00d47251
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tu_rv64-3.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vremu_vx_u8mf8_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf8_tu(merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vremu_vx_u8mf4_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf4_tu(merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vremu_vx_u8mf2_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf2_tu(merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vremu_vx_u8m1_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m1_tu(merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vremu_vx_u8m2_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m2_tu(merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vremu_vx_u8m4_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m4_tu(merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vremu_vx_u8m8_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m8_tu(merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vremu_vx_u16mf4_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16mf4_tu(merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vremu_vx_u16mf2_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16mf2_tu(merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vremu_vx_u16m1_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m1_tu(merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vremu_vx_u16m2_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m2_tu(merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vremu_vx_u16m4_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m4_tu(merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vremu_vx_u16m8_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m8_tu(merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vremu_vx_u32mf2_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32mf2_tu(merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vremu_vx_u32m1_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m1_tu(merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vremu_vx_u32m2_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m2_tu(merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vremu_vx_u32m4_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m4_tu(merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vremu_vx_u32m8_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m8_tu(merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vremu_vx_u64m1_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m1_tu(merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vremu_vx_u64m2_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m2_tu(merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vremu_vx_u64m4_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m4_tu(merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vremu_vx_u64m8_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m8_tu(merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tum_rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tum_rv32-1.c
new file mode 100644
index 00000000000..37fb718c422
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tum_rv32-1.c
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vremu_vx_u8mf8_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf8_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vremu_vx_u8mf4_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vremu_vx_u8mf2_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vremu_vx_u8m1_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m1_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vremu_vx_u8m2_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vremu_vx_u8m4_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vremu_vx_u8m8_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m8_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vremu_vx_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16mf4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vremu_vx_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16mf2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vremu_vx_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m1_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vremu_vx_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vremu_vx_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vremu_vx_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m8_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vremu_vx_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32mf2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vremu_vx_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m1_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vremu_vx_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vremu_vx_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vremu_vx_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m8_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vremu_vx_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m1_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vremu_vx_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vremu_vx_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vremu_vx_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m8_tum(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vremu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tum_rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tum_rv32-2.c
new file mode 100644
index 00000000000..54b51b1b9b6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tum_rv32-2.c
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vremu_vx_u8mf8_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf8_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vremu_vx_u8mf4_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf4_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vremu_vx_u8mf2_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf2_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vremu_vx_u8m1_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m1_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vremu_vx_u8m2_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m2_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vremu_vx_u8m4_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m4_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vremu_vx_u8m8_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m8_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vremu_vx_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16mf4_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vremu_vx_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16mf2_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vremu_vx_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m1_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vremu_vx_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m2_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vremu_vx_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m4_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vremu_vx_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m8_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vremu_vx_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32mf2_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vremu_vx_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m1_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vremu_vx_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m2_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vremu_vx_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m4_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vremu_vx_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m8_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vremu_vx_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m1_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vremu_vx_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m2_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vremu_vx_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m4_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vremu_vx_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m8_tum(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vremu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tum_rv32-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tum_rv32-3.c
new file mode 100644
index 00000000000..fd9f578d936
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tum_rv32-3.c
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vremu_vx_u8mf8_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf8_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vremu_vx_u8mf4_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf4_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vremu_vx_u8mf2_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf2_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vremu_vx_u8m1_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m1_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vremu_vx_u8m2_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m2_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vremu_vx_u8m4_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m4_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vremu_vx_u8m8_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m8_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vremu_vx_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16mf4_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vremu_vx_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16mf2_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vremu_vx_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m1_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vremu_vx_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m2_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vremu_vx_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m4_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vremu_vx_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m8_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vremu_vx_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32mf2_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vremu_vx_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m1_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vremu_vx_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m2_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vremu_vx_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m4_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vremu_vx_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m8_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vremu_vx_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m1_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vremu_vx_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m2_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vremu_vx_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m4_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vremu_vx_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m8_tum(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vremu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tum_rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tum_rv64-1.c
new file mode 100644
index 00000000000..52399069c6d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tum_rv64-1.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vremu_vx_u8mf8_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf8_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vremu_vx_u8mf4_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vremu_vx_u8mf2_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vremu_vx_u8m1_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m1_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vremu_vx_u8m2_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vremu_vx_u8m4_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vremu_vx_u8m8_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m8_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vremu_vx_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16mf4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vremu_vx_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16mf2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vremu_vx_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m1_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vremu_vx_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vremu_vx_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vremu_vx_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m8_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vremu_vx_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32mf2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vremu_vx_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m1_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vremu_vx_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vremu_vx_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vremu_vx_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m8_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vremu_vx_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m1_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vremu_vx_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vremu_vx_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vremu_vx_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m8_tum(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tum_rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tum_rv64-2.c
new file mode 100644
index 00000000000..d007fa15a53
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tum_rv64-2.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vremu_vx_u8mf8_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf8_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vremu_vx_u8mf4_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf4_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vremu_vx_u8mf2_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf2_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vremu_vx_u8m1_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m1_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vremu_vx_u8m2_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m2_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vremu_vx_u8m4_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m4_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vremu_vx_u8m8_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m8_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vremu_vx_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16mf4_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vremu_vx_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16mf2_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vremu_vx_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m1_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vremu_vx_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m2_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vremu_vx_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m4_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vremu_vx_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m8_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vremu_vx_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32mf2_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vremu_vx_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m1_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vremu_vx_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m2_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vremu_vx_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m4_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vremu_vx_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m8_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vremu_vx_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m1_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vremu_vx_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m2_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vremu_vx_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m4_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vremu_vx_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m8_tum(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tum_rv64-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tum_rv64-3.c
new file mode 100644
index 00000000000..07badeb5af9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tum_rv64-3.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vremu_vx_u8mf8_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf8_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vremu_vx_u8mf4_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf4_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vremu_vx_u8mf2_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf2_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vremu_vx_u8m1_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m1_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vremu_vx_u8m2_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m2_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vremu_vx_u8m4_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m4_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vremu_vx_u8m8_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m8_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vremu_vx_u16mf4_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16mf4_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vremu_vx_u16mf2_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16mf2_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vremu_vx_u16m1_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m1_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vremu_vx_u16m2_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m2_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vremu_vx_u16m4_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m4_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vremu_vx_u16m8_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m8_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vremu_vx_u32mf2_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32mf2_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vremu_vx_u32m1_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m1_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vremu_vx_u32m2_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m2_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vremu_vx_u32m4_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m4_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vremu_vx_u32m8_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m8_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vremu_vx_u64m1_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m1_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vremu_vx_u64m2_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m2_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vremu_vx_u64m4_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m4_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vremu_vx_u64m8_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m8_tum(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tumu_rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tumu_rv32-1.c
new file mode 100644
index 00000000000..6644149e522
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tumu_rv32-1.c
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vremu_vx_u8mf8_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf8_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vremu_vx_u8mf4_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vremu_vx_u8mf2_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vremu_vx_u8m1_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m1_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vremu_vx_u8m2_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vremu_vx_u8m4_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vremu_vx_u8m8_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m8_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vremu_vx_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16mf4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vremu_vx_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16mf2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vremu_vx_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m1_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vremu_vx_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vremu_vx_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vremu_vx_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m8_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vremu_vx_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32mf2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vremu_vx_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m1_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vremu_vx_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vremu_vx_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vremu_vx_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m8_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vremu_vx_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m1_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vremu_vx_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vremu_vx_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vremu_vx_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m8_tumu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vremu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tumu_rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tumu_rv32-2.c
new file mode 100644
index 00000000000..1bbc24bb642
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tumu_rv32-2.c
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vremu_vx_u8mf8_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf8_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vremu_vx_u8mf4_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vremu_vx_u8mf2_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vremu_vx_u8m1_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m1_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vremu_vx_u8m2_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vremu_vx_u8m4_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vremu_vx_u8m8_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m8_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vremu_vx_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16mf4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vremu_vx_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16mf2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vremu_vx_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m1_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vremu_vx_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vremu_vx_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vremu_vx_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m8_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vremu_vx_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32mf2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vremu_vx_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m1_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vremu_vx_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vremu_vx_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vremu_vx_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m8_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vremu_vx_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m1_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vremu_vx_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vremu_vx_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vremu_vx_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m8_tumu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vremu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tumu_rv32-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tumu_rv32-3.c
new file mode 100644
index 00000000000..c233f9bb06b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tumu_rv32-3.c
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vremu_vx_u8mf8_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf8_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vremu_vx_u8mf4_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vremu_vx_u8mf2_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vremu_vx_u8m1_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m1_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vremu_vx_u8m2_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vremu_vx_u8m4_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vremu_vx_u8m8_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m8_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vremu_vx_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16mf4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vremu_vx_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16mf2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vremu_vx_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m1_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vremu_vx_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vremu_vx_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vremu_vx_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m8_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vremu_vx_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32mf2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vremu_vx_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m1_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vremu_vx_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vremu_vx_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vremu_vx_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m8_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vremu_vx_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m1_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vremu_vx_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vremu_vx_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vremu_vx_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m8_tumu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vremu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tumu_rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tumu_rv64-1.c
new file mode 100644
index 00000000000..c7ac67723b5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tumu_rv64-1.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vremu_vx_u8mf8_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf8_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vremu_vx_u8mf4_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vremu_vx_u8mf2_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vremu_vx_u8m1_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m1_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vremu_vx_u8m2_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vremu_vx_u8m4_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vremu_vx_u8m8_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m8_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vremu_vx_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16mf4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vremu_vx_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16mf2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vremu_vx_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m1_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vremu_vx_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vremu_vx_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vremu_vx_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m8_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vremu_vx_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32mf2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vremu_vx_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m1_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vremu_vx_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vremu_vx_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vremu_vx_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m8_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vremu_vx_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m1_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vremu_vx_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vremu_vx_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vremu_vx_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m8_tumu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tumu_rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tumu_rv64-2.c
new file mode 100644
index 00000000000..fc5ea94295f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tumu_rv64-2.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vremu_vx_u8mf8_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf8_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vremu_vx_u8mf4_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vremu_vx_u8mf2_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vremu_vx_u8m1_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m1_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vremu_vx_u8m2_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vremu_vx_u8m4_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vremu_vx_u8m8_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m8_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vremu_vx_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16mf4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vremu_vx_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16mf2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vremu_vx_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m1_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vremu_vx_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vremu_vx_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vremu_vx_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m8_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vremu_vx_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32mf2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vremu_vx_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m1_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vremu_vx_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vremu_vx_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vremu_vx_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m8_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vremu_vx_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m1_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vremu_vx_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vremu_vx_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vremu_vx_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m8_tumu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tumu_rv64-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tumu_rv64-3.c
new file mode 100644
index 00000000000..3fb36252034
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vremu_vx_tumu_rv64-3.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vremu_vx_u8mf8_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf8_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vremu_vx_u8mf4_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vremu_vx_u8mf2_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8mf2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vremu_vx_u8m1_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m1_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vremu_vx_u8m2_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vremu_vx_u8m4_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vremu_vx_u8m8_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u8m8_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vremu_vx_u16mf4_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16mf4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vremu_vx_u16mf2_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16mf2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vremu_vx_u16m1_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m1_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vremu_vx_u16m2_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vremu_vx_u16m4_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vremu_vx_u16m8_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u16m8_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vremu_vx_u32mf2_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32mf2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vremu_vx_u32m1_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m1_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vremu_vx_u32m2_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vremu_vx_u32m4_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vremu_vx_u32m8_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u32m8_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vremu_vx_u64m1_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m1_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vremu_vx_u64m2_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vremu_vx_u64m4_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vremu_vx_u64m8_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_vx_u64m8_tumu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
--
2.36.1
^ permalink raw reply [flat|nested] 2+ messages in thread
* [PATCH] RISC-V: Add vremu.vx C++ API tests.
@ 2023-02-03 7:49 juzhe.zhong
0 siblings, 0 replies; 2+ messages in thread
From: juzhe.zhong @ 2023-02-03 7:49 UTC (permalink / raw)
To: gcc-patches; +Cc: kito.cheng, Ju-Zhe Zhong
From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/vremu_vx_mu_rv32-1.C: New test.
* g++.target/riscv/rvv/base/vremu_vx_mu_rv32-2.C: New test.
* g++.target/riscv/rvv/base/vremu_vx_mu_rv32-3.C: New test.
* g++.target/riscv/rvv/base/vremu_vx_mu_rv64-1.C: New test.
* g++.target/riscv/rvv/base/vremu_vx_mu_rv64-2.C: New test.
* g++.target/riscv/rvv/base/vremu_vx_mu_rv64-3.C: New test.
* g++.target/riscv/rvv/base/vremu_vx_rv32-1.C: New test.
* g++.target/riscv/rvv/base/vremu_vx_rv32-2.C: New test.
* g++.target/riscv/rvv/base/vremu_vx_rv32-3.C: New test.
* g++.target/riscv/rvv/base/vremu_vx_rv64-1.C: New test.
* g++.target/riscv/rvv/base/vremu_vx_rv64-2.C: New test.
* g++.target/riscv/rvv/base/vremu_vx_rv64-3.C: New test.
* g++.target/riscv/rvv/base/vremu_vx_tu_rv32-1.C: New test.
* g++.target/riscv/rvv/base/vremu_vx_tu_rv32-2.C: New test.
* g++.target/riscv/rvv/base/vremu_vx_tu_rv32-3.C: New test.
* g++.target/riscv/rvv/base/vremu_vx_tu_rv64-1.C: New test.
* g++.target/riscv/rvv/base/vremu_vx_tu_rv64-2.C: New test.
* g++.target/riscv/rvv/base/vremu_vx_tu_rv64-3.C: New test.
* g++.target/riscv/rvv/base/vremu_vx_tum_rv32-1.C: New test.
* g++.target/riscv/rvv/base/vremu_vx_tum_rv32-2.C: New test.
* g++.target/riscv/rvv/base/vremu_vx_tum_rv32-3.C: New test.
* g++.target/riscv/rvv/base/vremu_vx_tum_rv64-1.C: New test.
* g++.target/riscv/rvv/base/vremu_vx_tum_rv64-2.C: New test.
* g++.target/riscv/rvv/base/vremu_vx_tum_rv64-3.C: New test.
* g++.target/riscv/rvv/base/vremu_vx_tumu_rv32-1.C: New test.
* g++.target/riscv/rvv/base/vremu_vx_tumu_rv32-2.C: New test.
* g++.target/riscv/rvv/base/vremu_vx_tumu_rv32-3.C: New test.
* g++.target/riscv/rvv/base/vremu_vx_tumu_rv64-1.C: New test.
* g++.target/riscv/rvv/base/vremu_vx_tumu_rv64-2.C: New test.
* g++.target/riscv/rvv/base/vremu_vx_tumu_rv64-3.C: New test.
---
.../riscv/rvv/base/vremu_vx_mu_rv32-1.C | 157 +++++++++
.../riscv/rvv/base/vremu_vx_mu_rv32-2.C | 157 +++++++++
.../riscv/rvv/base/vremu_vx_mu_rv32-3.C | 157 +++++++++
.../riscv/rvv/base/vremu_vx_mu_rv64-1.C | 160 +++++++++
.../riscv/rvv/base/vremu_vx_mu_rv64-2.C | 160 +++++++++
.../riscv/rvv/base/vremu_vx_mu_rv64-3.C | 160 +++++++++
.../riscv/rvv/base/vremu_vx_rv32-1.C | 308 +++++++++++++++++
.../riscv/rvv/base/vremu_vx_rv32-2.C | 308 +++++++++++++++++
.../riscv/rvv/base/vremu_vx_rv32-3.C | 308 +++++++++++++++++
.../riscv/rvv/base/vremu_vx_rv64-1.C | 314 ++++++++++++++++++
.../riscv/rvv/base/vremu_vx_rv64-2.C | 314 ++++++++++++++++++
.../riscv/rvv/base/vremu_vx_rv64-3.C | 314 ++++++++++++++++++
.../riscv/rvv/base/vremu_vx_tu_rv32-1.C | 157 +++++++++
.../riscv/rvv/base/vremu_vx_tu_rv32-2.C | 157 +++++++++
.../riscv/rvv/base/vremu_vx_tu_rv32-3.C | 157 +++++++++
.../riscv/rvv/base/vremu_vx_tu_rv64-1.C | 160 +++++++++
.../riscv/rvv/base/vremu_vx_tu_rv64-2.C | 160 +++++++++
.../riscv/rvv/base/vremu_vx_tu_rv64-3.C | 160 +++++++++
.../riscv/rvv/base/vremu_vx_tum_rv32-1.C | 157 +++++++++
.../riscv/rvv/base/vremu_vx_tum_rv32-2.C | 157 +++++++++
.../riscv/rvv/base/vremu_vx_tum_rv32-3.C | 157 +++++++++
.../riscv/rvv/base/vremu_vx_tum_rv64-1.C | 160 +++++++++
.../riscv/rvv/base/vremu_vx_tum_rv64-2.C | 160 +++++++++
.../riscv/rvv/base/vremu_vx_tum_rv64-3.C | 160 +++++++++
.../riscv/rvv/base/vremu_vx_tumu_rv32-1.C | 157 +++++++++
.../riscv/rvv/base/vremu_vx_tumu_rv32-2.C | 157 +++++++++
.../riscv/rvv/base/vremu_vx_tumu_rv32-3.C | 157 +++++++++
.../riscv/rvv/base/vremu_vx_tumu_rv64-1.C | 160 +++++++++
.../riscv/rvv/base/vremu_vx_tumu_rv64-2.C | 160 +++++++++
.../riscv/rvv/base/vremu_vx_tumu_rv64-3.C | 160 +++++++++
30 files changed, 5670 insertions(+)
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_mu_rv32-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_mu_rv32-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_mu_rv32-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_mu_rv64-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_mu_rv64-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_mu_rv64-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_rv32-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_rv32-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_rv32-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_rv64-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_rv64-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_rv64-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tu_rv32-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tu_rv32-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tu_rv32-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tu_rv64-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tu_rv64-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tu_rv64-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tum_rv32-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tum_rv32-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tum_rv32-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tum_rv64-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tum_rv64-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tum_rv64-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tumu_rv32-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tumu_rv32-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tumu_rv32-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tumu_rv64-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tumu_rv64-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tumu_rv64-3.C
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_mu_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_mu_rv32-1.C
new file mode 100644
index 00000000000..e65db195a8b
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_mu_rv32-1.C
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vremu_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vremu_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vremu_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vremu_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vremu_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vremu_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vremu_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vremu_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vremu_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vremu_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vremu_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vremu_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vremu_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vremu_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vremu_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vremu_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vremu_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vremu_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vremu_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vremu_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vremu_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vremu_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vremu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_mu_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_mu_rv32-2.C
new file mode 100644
index 00000000000..8b35dcff6a5
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_mu_rv32-2.C
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vremu_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vremu_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vremu_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vremu_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vremu_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vremu_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vremu_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vremu_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vremu_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vremu_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vremu_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vremu_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vremu_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vremu_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vremu_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vremu_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vremu_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vremu_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vremu_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vremu_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vremu_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vremu_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vremu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_mu_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_mu_rv32-3.C
new file mode 100644
index 00000000000..15984b4eb9f
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_mu_rv32-3.C
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vremu_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vremu_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vremu_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vremu_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vremu_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vremu_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vremu_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vremu_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vremu_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vremu_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vremu_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vremu_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vremu_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vremu_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vremu_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vremu_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vremu_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vremu_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vremu_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vremu_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vremu_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vremu_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vremu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_mu_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_mu_rv64-1.C
new file mode 100644
index 00000000000..8b89e7ddb4d
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_mu_rv64-1.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vremu_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vremu_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vremu_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vremu_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vremu_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vremu_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vremu_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vremu_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vremu_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vremu_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vremu_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vremu_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vremu_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vremu_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vremu_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vremu_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vremu_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vremu_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vremu_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vremu_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vremu_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vremu_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_mu_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_mu_rv64-2.C
new file mode 100644
index 00000000000..e14485b4bf4
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_mu_rv64-2.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vremu_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vremu_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vremu_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vremu_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vremu_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vremu_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vremu_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vremu_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vremu_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vremu_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vremu_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vremu_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vremu_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vremu_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vremu_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vremu_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vremu_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vremu_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vremu_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vremu_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vremu_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vremu_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_mu_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_mu_rv64-3.C
new file mode 100644
index 00000000000..c73ebb1d043
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_mu_rv64-3.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vremu_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vremu_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vremu_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vremu_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vremu_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vremu_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vremu_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vremu_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vremu_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vremu_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vremu_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vremu_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vremu_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vremu_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vremu_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vremu_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vremu_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vremu_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vremu_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vremu_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vremu_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vremu_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_mu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_rv32-1.C
new file mode 100644
index 00000000000..a5ff66e5602
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_rv32-1.C
@@ -0,0 +1,308 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vremu(vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vremu(vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vremu(vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vremu(vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vremu(vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vremu(vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vremu(vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vremu(vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vremu(vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vremu(vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vremu(vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vremu(vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vremu(vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vremu(vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vremu(vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vremu(vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vremu(vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vremu(vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vremu(vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vremu(vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vremu(vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vremu(vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vremu(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vremu(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vremu(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vremu(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vremu(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vremu(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vremu(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vremu(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vremu(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vremu(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vremu(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vremu(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vremu(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vremu(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vremu(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vremu(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vremu(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vremu(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vremu(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vremu(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vremu(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vremu(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vremu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vremu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_rv32-2.C
new file mode 100644
index 00000000000..1b763a5013f
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_rv32-2.C
@@ -0,0 +1,308 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vremu(vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vremu(vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vremu(vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vremu(vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vremu(vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vremu(vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vremu(vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vremu(vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vremu(vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vremu(vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vremu(vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vremu(vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vremu(vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vremu(vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vremu(vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vremu(vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vremu(vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vremu(vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vremu(vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vremu(vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vremu(vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vremu(vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,31);
+}
+
+
+vuint8mf8_t test___riscv_vremu(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vremu(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vremu(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vremu(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vremu(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vremu(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vremu(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vremu(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vremu(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vremu(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vremu(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vremu(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vremu(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vremu(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vremu(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vremu(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vremu(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vremu(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vremu(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vremu(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vremu(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vremu(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vremu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vremu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_rv32-3.C
new file mode 100644
index 00000000000..2daf0555e83
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_rv32-3.C
@@ -0,0 +1,308 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vremu(vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vremu(vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vremu(vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vremu(vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vremu(vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vremu(vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vremu(vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vremu(vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vremu(vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vremu(vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vremu(vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vremu(vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vremu(vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vremu(vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vremu(vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vremu(vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vremu(vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vremu(vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vremu(vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vremu(vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vremu(vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vremu(vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,32);
+}
+
+
+vuint8mf8_t test___riscv_vremu(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vremu(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vremu(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vremu(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vremu(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vremu(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vremu(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vremu(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vremu(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vremu(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vremu(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vremu(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vremu(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vremu(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vremu(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vremu(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vremu(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vremu(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vremu(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vremu(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vremu(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vremu(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vremu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vremu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_rv64-1.C
new file mode 100644
index 00000000000..eaeee48f8af
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_rv64-1.C
@@ -0,0 +1,314 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vremu(vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vremu(vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vremu(vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vremu(vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vremu(vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vremu(vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vremu(vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vremu(vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vremu(vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vremu(vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vremu(vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vremu(vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vremu(vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vremu(vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vremu(vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vremu(vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vremu(vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vremu(vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vremu(vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vremu(vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vremu(vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vremu(vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,vl);
+}
+
+
+vuint8mf8_t test___riscv_vremu(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vremu(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vremu(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vremu(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vremu(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vremu(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vremu(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vremu(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vremu(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vremu(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vremu(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vremu(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vremu(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vremu(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vremu(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vremu(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vremu(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vremu(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vremu(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vremu(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vremu(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vremu(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_rv64-2.C
new file mode 100644
index 00000000000..3bebf2d698e
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_rv64-2.C
@@ -0,0 +1,314 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vremu(vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vremu(vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vremu(vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vremu(vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vremu(vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vremu(vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vremu(vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vremu(vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vremu(vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vremu(vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vremu(vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vremu(vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vremu(vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vremu(vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vremu(vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vremu(vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vremu(vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vremu(vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vremu(vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vremu(vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vremu(vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vremu(vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,31);
+}
+
+
+vuint8mf8_t test___riscv_vremu(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vremu(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vremu(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vremu(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vremu(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vremu(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vremu(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vremu(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vremu(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vremu(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vremu(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vremu(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vremu(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vremu(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vremu(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vremu(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vremu(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vremu(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vremu(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vremu(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vremu(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vremu(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_rv64-3.C
new file mode 100644
index 00000000000..1053ec4ea79
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_rv64-3.C
@@ -0,0 +1,314 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vremu(vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vremu(vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vremu(vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vremu(vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vremu(vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vremu(vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vremu(vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vremu(vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vremu(vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vremu(vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vremu(vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vremu(vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vremu(vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vremu(vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vremu(vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vremu(vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vremu(vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vremu(vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vremu(vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vremu(vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vremu(vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vremu(vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu(op1,op2,32);
+}
+
+
+vuint8mf8_t test___riscv_vremu(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vremu(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vremu(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vremu(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vremu(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vremu(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vremu(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vremu(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vremu(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vremu(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vremu(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vremu(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vremu(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vremu(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vremu(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vremu(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vremu(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vremu(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vremu(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vremu(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vremu(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vremu(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu(mask,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tu_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tu_rv32-1.C
new file mode 100644
index 00000000000..d5771602ce6
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tu_rv32-1.C
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vremu_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vremu_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vremu_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vremu_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vremu_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vremu_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vremu_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vremu_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vremu_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vremu_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vremu_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vremu_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vremu_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vremu_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vremu_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vremu_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vremu_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vremu_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vremu_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vremu_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vremu_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vremu_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vremu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tu_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tu_rv32-2.C
new file mode 100644
index 00000000000..aea51610658
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tu_rv32-2.C
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vremu_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vremu_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vremu_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vremu_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vremu_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vremu_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vremu_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vremu_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vremu_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vremu_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vremu_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vremu_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vremu_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vremu_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vremu_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vremu_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vremu_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vremu_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vremu_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vremu_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vremu_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vremu_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vremu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tu_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tu_rv32-3.C
new file mode 100644
index 00000000000..db0c21600e5
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tu_rv32-3.C
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vremu_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vremu_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vremu_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vremu_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vremu_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vremu_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vremu_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vremu_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vremu_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vremu_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vremu_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vremu_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vremu_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vremu_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vremu_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vremu_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vremu_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vremu_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vremu_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vremu_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vremu_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vremu_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vremu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tu_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tu_rv64-1.C
new file mode 100644
index 00000000000..d27019c12a0
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tu_rv64-1.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vremu_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vremu_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vremu_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vremu_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vremu_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vremu_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vremu_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vremu_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vremu_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vremu_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vremu_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vremu_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vremu_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vremu_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vremu_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vremu_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vremu_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vremu_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vremu_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vremu_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vremu_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vremu_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tu_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tu_rv64-2.C
new file mode 100644
index 00000000000..c2817107704
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tu_rv64-2.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vremu_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vremu_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vremu_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vremu_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vremu_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vremu_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vremu_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vremu_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vremu_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vremu_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vremu_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vremu_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vremu_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vremu_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vremu_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vremu_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vremu_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vremu_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vremu_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vremu_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vremu_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vremu_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tu_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tu_rv64-3.C
new file mode 100644
index 00000000000..f12754c8ccc
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tu_rv64-3.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vremu_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vremu_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vremu_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vremu_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vremu_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vremu_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vremu_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vremu_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vremu_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vremu_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vremu_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vremu_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vremu_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vremu_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vremu_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vremu_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vremu_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vremu_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vremu_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vremu_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vremu_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vremu_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_tu(merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tum_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tum_rv32-1.C
new file mode 100644
index 00000000000..8264f1b0e00
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tum_rv32-1.C
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vremu_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vremu_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vremu_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vremu_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vremu_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vremu_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vremu_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vremu_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vremu_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vremu_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vremu_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vremu_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vremu_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vremu_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vremu_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vremu_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vremu_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vremu_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vremu_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vremu_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vremu_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vremu_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vremu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tum_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tum_rv32-2.C
new file mode 100644
index 00000000000..aa361d27d1d
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tum_rv32-2.C
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vremu_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vremu_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vremu_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vremu_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vremu_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vremu_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vremu_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vremu_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vremu_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vremu_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vremu_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vremu_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vremu_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vremu_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vremu_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vremu_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vremu_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vremu_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vremu_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vremu_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vremu_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vremu_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vremu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tum_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tum_rv32-3.C
new file mode 100644
index 00000000000..9f77d03c7d1
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tum_rv32-3.C
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vremu_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vremu_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vremu_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vremu_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vremu_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vremu_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vremu_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vremu_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vremu_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vremu_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vremu_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vremu_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vremu_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vremu_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vremu_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vremu_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vremu_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vremu_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vremu_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vremu_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vremu_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vremu_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vremu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tum_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tum_rv64-1.C
new file mode 100644
index 00000000000..0b8ebe68aec
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tum_rv64-1.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vremu_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vremu_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vremu_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vremu_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vremu_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vremu_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vremu_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vremu_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vremu_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vremu_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vremu_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vremu_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vremu_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vremu_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vremu_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vremu_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vremu_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vremu_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vremu_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vremu_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vremu_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vremu_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tum_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tum_rv64-2.C
new file mode 100644
index 00000000000..3b72749c8a0
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tum_rv64-2.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vremu_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vremu_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vremu_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vremu_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vremu_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vremu_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vremu_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vremu_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vremu_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vremu_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vremu_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vremu_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vremu_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vremu_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vremu_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vremu_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vremu_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vremu_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vremu_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vremu_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vremu_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vremu_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tum_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tum_rv64-3.C
new file mode 100644
index 00000000000..3dfc134a21a
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tum_rv64-3.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vremu_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vremu_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vremu_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vremu_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vremu_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vremu_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vremu_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vremu_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vremu_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vremu_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vremu_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vremu_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vremu_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vremu_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vremu_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vremu_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vremu_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vremu_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vremu_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vremu_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vremu_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vremu_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_tum(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tumu_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tumu_rv32-1.C
new file mode 100644
index 00000000000..8dd61fd28b9
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tumu_rv32-1.C
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vremu_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vremu_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vremu_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vremu_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vremu_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vremu_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vremu_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vremu_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vremu_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vremu_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vremu_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vremu_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vremu_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vremu_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vremu_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vremu_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vremu_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vremu_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vremu_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vremu_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vremu_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vremu_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vremu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tumu_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tumu_rv32-2.C
new file mode 100644
index 00000000000..1df4f594f65
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tumu_rv32-2.C
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vremu_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vremu_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vremu_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vremu_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vremu_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vremu_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vremu_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vremu_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vremu_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vremu_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vremu_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vremu_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vremu_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vremu_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vremu_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vremu_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vremu_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vremu_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vremu_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vremu_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vremu_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vremu_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vremu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tumu_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tumu_rv32-3.C
new file mode 100644
index 00000000000..068514b6ca4
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tumu_rv32-3.C
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vremu_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vremu_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vremu_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vremu_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vremu_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vremu_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vremu_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vremu_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vremu_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vremu_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vremu_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vremu_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vremu_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vremu_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vremu_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vremu_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vremu_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vremu_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vremu_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vremu_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vremu_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vremu_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vremu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tumu_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tumu_rv64-1.C
new file mode 100644
index 00000000000..80d673f7a90
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tumu_rv64-1.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vremu_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf4_t test___riscv_vremu_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8mf2_t test___riscv_vremu_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m1_t test___riscv_vremu_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m2_t test___riscv_vremu_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m4_t test___riscv_vremu_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint8m8_t test___riscv_vremu_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf4_t test___riscv_vremu_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16mf2_t test___riscv_vremu_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m1_t test___riscv_vremu_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m2_t test___riscv_vremu_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m4_t test___riscv_vremu_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint16m8_t test___riscv_vremu_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32mf2_t test___riscv_vremu_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m1_t test___riscv_vremu_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m2_t test___riscv_vremu_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m4_t test___riscv_vremu_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint32m8_t test___riscv_vremu_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m1_t test___riscv_vremu_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m2_t test___riscv_vremu_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m4_t test___riscv_vremu_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vuint64m8_t test___riscv_vremu_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tumu_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tumu_rv64-2.C
new file mode 100644
index 00000000000..63838fc379f
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tumu_rv64-2.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vremu_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf4_t test___riscv_vremu_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8mf2_t test___riscv_vremu_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m1_t test___riscv_vremu_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m2_t test___riscv_vremu_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m4_t test___riscv_vremu_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint8m8_t test___riscv_vremu_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf4_t test___riscv_vremu_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16mf2_t test___riscv_vremu_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m1_t test___riscv_vremu_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m2_t test___riscv_vremu_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m4_t test___riscv_vremu_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint16m8_t test___riscv_vremu_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32mf2_t test___riscv_vremu_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m1_t test___riscv_vremu_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m2_t test___riscv_vremu_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m4_t test___riscv_vremu_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint32m8_t test___riscv_vremu_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m1_t test___riscv_vremu_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m2_t test___riscv_vremu_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m4_t test___riscv_vremu_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,31);
+}
+
+
+vuint64m8_t test___riscv_vremu_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tumu_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tumu_rv64-3.C
new file mode 100644
index 00000000000..8ab9c00a10c
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_tumu_rv64-3.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vuint8mf8_t test___riscv_vremu_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf4_t test___riscv_vremu_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8mf2_t test___riscv_vremu_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m1_t test___riscv_vremu_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m2_t test___riscv_vremu_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m4_t test___riscv_vremu_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint8m8_t test___riscv_vremu_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf4_t test___riscv_vremu_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16mf2_t test___riscv_vremu_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m1_t test___riscv_vremu_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m2_t test___riscv_vremu_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m4_t test___riscv_vremu_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint16m8_t test___riscv_vremu_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32mf2_t test___riscv_vremu_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m1_t test___riscv_vremu_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m2_t test___riscv_vremu_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m4_t test___riscv_vremu_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint32m8_t test___riscv_vremu_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m1_t test___riscv_vremu_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m2_t test___riscv_vremu_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m4_t test___riscv_vremu_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,32);
+}
+
+
+vuint64m8_t test___riscv_vremu_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl)
+{
+ return __riscv_vremu_tumu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vremu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
--
2.36.1
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2023-02-03 7:10 [PATCH] RISC-V: Add vremu.vx C API tests juzhe.zhong
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