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* [PATCH] RISC-V: Add vmax.vx C API tests
@ 2023-02-03  7:23 juzhe.zhong
  0 siblings, 0 replies; 2+ messages in thread
From: juzhe.zhong @ 2023-02-03  7:23 UTC (permalink / raw)
  To: gcc-patches; +Cc: kito.cheng, Ju-Zhe Zhong

From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/rvv/base/vmax_vx_m_rv32-1.c: New test.
        * gcc.target/riscv/rvv/base/vmax_vx_m_rv32-2.c: New test.
        * gcc.target/riscv/rvv/base/vmax_vx_m_rv32-3.c: New test.
        * gcc.target/riscv/rvv/base/vmax_vx_m_rv64-1.c: New test.
        * gcc.target/riscv/rvv/base/vmax_vx_m_rv64-2.c: New test.
        * gcc.target/riscv/rvv/base/vmax_vx_m_rv64-3.c: New test.
        * gcc.target/riscv/rvv/base/vmax_vx_mu_rv32-1.c: New test.
        * gcc.target/riscv/rvv/base/vmax_vx_mu_rv32-2.c: New test.
        * gcc.target/riscv/rvv/base/vmax_vx_mu_rv32-3.c: New test.
        * gcc.target/riscv/rvv/base/vmax_vx_mu_rv64-1.c: New test.
        * gcc.target/riscv/rvv/base/vmax_vx_mu_rv64-2.c: New test.
        * gcc.target/riscv/rvv/base/vmax_vx_mu_rv64-3.c: New test.
        * gcc.target/riscv/rvv/base/vmax_vx_rv32-1.c: New test.
        * gcc.target/riscv/rvv/base/vmax_vx_rv32-2.c: New test.
        * gcc.target/riscv/rvv/base/vmax_vx_rv32-3.c: New test.
        * gcc.target/riscv/rvv/base/vmax_vx_rv64-1.c: New test.
        * gcc.target/riscv/rvv/base/vmax_vx_rv64-2.c: New test.
        * gcc.target/riscv/rvv/base/vmax_vx_rv64-3.c: New test.
        * gcc.target/riscv/rvv/base/vmax_vx_tu_rv32-1.c: New test.
        * gcc.target/riscv/rvv/base/vmax_vx_tu_rv32-2.c: New test.
        * gcc.target/riscv/rvv/base/vmax_vx_tu_rv32-3.c: New test.
        * gcc.target/riscv/rvv/base/vmax_vx_tu_rv64-1.c: New test.
        * gcc.target/riscv/rvv/base/vmax_vx_tu_rv64-2.c: New test.
        * gcc.target/riscv/rvv/base/vmax_vx_tu_rv64-3.c: New test.
        * gcc.target/riscv/rvv/base/vmax_vx_tum_rv32-1.c: New test.
        * gcc.target/riscv/rvv/base/vmax_vx_tum_rv32-2.c: New test.
        * gcc.target/riscv/rvv/base/vmax_vx_tum_rv32-3.c: New test.
        * gcc.target/riscv/rvv/base/vmax_vx_tum_rv64-1.c: New test.
        * gcc.target/riscv/rvv/base/vmax_vx_tum_rv64-2.c: New test.
        * gcc.target/riscv/rvv/base/vmax_vx_tum_rv64-3.c: New test.
        * gcc.target/riscv/rvv/base/vmax_vx_tumu_rv32-1.c: New test.
        * gcc.target/riscv/rvv/base/vmax_vx_tumu_rv32-2.c: New test.
        * gcc.target/riscv/rvv/base/vmax_vx_tumu_rv32-3.c: New test.
        * gcc.target/riscv/rvv/base/vmax_vx_tumu_rv64-1.c: New test.
        * gcc.target/riscv/rvv/base/vmax_vx_tumu_rv64-2.c: New test.
        * gcc.target/riscv/rvv/base/vmax_vx_tumu_rv64-3.c: New test.

---
 .../riscv/rvv/base/vmax_vx_m_rv32-1.c         | 157 +++++++++++++++++
 .../riscv/rvv/base/vmax_vx_m_rv32-2.c         | 157 +++++++++++++++++
 .../riscv/rvv/base/vmax_vx_m_rv32-3.c         | 157 +++++++++++++++++
 .../riscv/rvv/base/vmax_vx_m_rv64-1.c         | 160 ++++++++++++++++++
 .../riscv/rvv/base/vmax_vx_m_rv64-2.c         | 160 ++++++++++++++++++
 .../riscv/rvv/base/vmax_vx_m_rv64-3.c         | 160 ++++++++++++++++++
 .../riscv/rvv/base/vmax_vx_mu_rv32-1.c        | 157 +++++++++++++++++
 .../riscv/rvv/base/vmax_vx_mu_rv32-2.c        | 157 +++++++++++++++++
 .../riscv/rvv/base/vmax_vx_mu_rv32-3.c        | 157 +++++++++++++++++
 .../riscv/rvv/base/vmax_vx_mu_rv64-1.c        | 160 ++++++++++++++++++
 .../riscv/rvv/base/vmax_vx_mu_rv64-2.c        | 160 ++++++++++++++++++
 .../riscv/rvv/base/vmax_vx_mu_rv64-3.c        | 160 ++++++++++++++++++
 .../riscv/rvv/base/vmax_vx_rv32-1.c           | 157 +++++++++++++++++
 .../riscv/rvv/base/vmax_vx_rv32-2.c           | 157 +++++++++++++++++
 .../riscv/rvv/base/vmax_vx_rv32-3.c           | 157 +++++++++++++++++
 .../riscv/rvv/base/vmax_vx_rv64-1.c           | 160 ++++++++++++++++++
 .../riscv/rvv/base/vmax_vx_rv64-2.c           | 160 ++++++++++++++++++
 .../riscv/rvv/base/vmax_vx_rv64-3.c           | 160 ++++++++++++++++++
 .../riscv/rvv/base/vmax_vx_tu_rv32-1.c        | 157 +++++++++++++++++
 .../riscv/rvv/base/vmax_vx_tu_rv32-2.c        | 157 +++++++++++++++++
 .../riscv/rvv/base/vmax_vx_tu_rv32-3.c        | 157 +++++++++++++++++
 .../riscv/rvv/base/vmax_vx_tu_rv64-1.c        | 160 ++++++++++++++++++
 .../riscv/rvv/base/vmax_vx_tu_rv64-2.c        | 160 ++++++++++++++++++
 .../riscv/rvv/base/vmax_vx_tu_rv64-3.c        | 160 ++++++++++++++++++
 .../riscv/rvv/base/vmax_vx_tum_rv32-1.c       | 157 +++++++++++++++++
 .../riscv/rvv/base/vmax_vx_tum_rv32-2.c       | 157 +++++++++++++++++
 .../riscv/rvv/base/vmax_vx_tum_rv32-3.c       | 157 +++++++++++++++++
 .../riscv/rvv/base/vmax_vx_tum_rv64-1.c       | 160 ++++++++++++++++++
 .../riscv/rvv/base/vmax_vx_tum_rv64-2.c       | 160 ++++++++++++++++++
 .../riscv/rvv/base/vmax_vx_tum_rv64-3.c       | 160 ++++++++++++++++++
 .../riscv/rvv/base/vmax_vx_tumu_rv32-1.c      | 157 +++++++++++++++++
 .../riscv/rvv/base/vmax_vx_tumu_rv32-2.c      | 157 +++++++++++++++++
 .../riscv/rvv/base/vmax_vx_tumu_rv32-3.c      | 157 +++++++++++++++++
 .../riscv/rvv/base/vmax_vx_tumu_rv64-1.c      | 160 ++++++++++++++++++
 .../riscv/rvv/base/vmax_vx_tumu_rv64-2.c      | 160 ++++++++++++++++++
 .../riscv/rvv/base/vmax_vx_tumu_rv64-3.c      | 160 ++++++++++++++++++
 36 files changed, 5706 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_m_rv32-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_m_rv32-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_m_rv32-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_m_rv64-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_m_rv64-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_m_rv64-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_mu_rv32-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_mu_rv32-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_mu_rv32-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_mu_rv64-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_mu_rv64-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_mu_rv64-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_rv32-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_rv32-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_rv32-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_rv64-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_rv64-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_rv64-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tu_rv32-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tu_rv32-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tu_rv32-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tu_rv64-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tu_rv64-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tu_rv64-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tum_rv32-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tum_rv32-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tum_rv32-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tum_rv64-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tum_rv64-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tum_rv64-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tumu_rv32-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tumu_rv32-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tumu_rv32-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tumu_rv64-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tumu_rv64-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tumu_rv64-3.c

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_m_rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_m_rv32-1.c
new file mode 100644
index 00000000000..9f04970f312
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_m_rv32-1.c
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmax_vx_i8mf8_m(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf8_m(mask,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vmax_vx_i8mf4_m(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf4_m(mask,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vmax_vx_i8mf2_m(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf2_m(mask,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vmax_vx_i8m1_m(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m1_m(mask,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vmax_vx_i8m2_m(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m2_m(mask,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vmax_vx_i8m4_m(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m4_m(mask,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vmax_vx_i8m8_m(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m8_m(mask,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vmax_vx_i16mf4_m(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16mf4_m(mask,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vmax_vx_i16mf2_m(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16mf2_m(mask,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vmax_vx_i16m1_m(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m1_m(mask,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vmax_vx_i16m2_m(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m2_m(mask,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vmax_vx_i16m4_m(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m4_m(mask,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vmax_vx_i16m8_m(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m8_m(mask,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vmax_vx_i32mf2_m(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32mf2_m(mask,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vmax_vx_i32m1_m(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m1_m(mask,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vmax_vx_i32m2_m(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m2_m(mask,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vmax_vx_i32m4_m(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m4_m(mask,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vmax_vx_i32m8_m(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m8_m(mask,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vmax_vx_i64m1_m(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m1_m(mask,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vmax_vx_i64m2_m(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m2_m(mask,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vmax_vx_i64m4_m(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m4_m(mask,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vmax_vx_i64m8_m(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m8_m(mask,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_m_rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_m_rv32-2.c
new file mode 100644
index 00000000000..a46364a4b4d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_m_rv32-2.c
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmax_vx_i8mf8_m(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf8_m(mask,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vmax_vx_i8mf4_m(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf4_m(mask,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vmax_vx_i8mf2_m(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf2_m(mask,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vmax_vx_i8m1_m(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m1_m(mask,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vmax_vx_i8m2_m(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m2_m(mask,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vmax_vx_i8m4_m(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m4_m(mask,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vmax_vx_i8m8_m(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m8_m(mask,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vmax_vx_i16mf4_m(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16mf4_m(mask,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vmax_vx_i16mf2_m(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16mf2_m(mask,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vmax_vx_i16m1_m(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m1_m(mask,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vmax_vx_i16m2_m(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m2_m(mask,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vmax_vx_i16m4_m(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m4_m(mask,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vmax_vx_i16m8_m(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m8_m(mask,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vmax_vx_i32mf2_m(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32mf2_m(mask,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vmax_vx_i32m1_m(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m1_m(mask,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vmax_vx_i32m2_m(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m2_m(mask,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vmax_vx_i32m4_m(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m4_m(mask,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vmax_vx_i32m8_m(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m8_m(mask,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vmax_vx_i64m1_m(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m1_m(mask,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vmax_vx_i64m2_m(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m2_m(mask,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vmax_vx_i64m4_m(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m4_m(mask,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vmax_vx_i64m8_m(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m8_m(mask,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_m_rv32-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_m_rv32-3.c
new file mode 100644
index 00000000000..82462075339
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_m_rv32-3.c
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmax_vx_i8mf8_m(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf8_m(mask,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vmax_vx_i8mf4_m(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf4_m(mask,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vmax_vx_i8mf2_m(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf2_m(mask,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vmax_vx_i8m1_m(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m1_m(mask,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vmax_vx_i8m2_m(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m2_m(mask,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vmax_vx_i8m4_m(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m4_m(mask,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vmax_vx_i8m8_m(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m8_m(mask,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vmax_vx_i16mf4_m(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16mf4_m(mask,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vmax_vx_i16mf2_m(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16mf2_m(mask,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vmax_vx_i16m1_m(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m1_m(mask,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vmax_vx_i16m2_m(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m2_m(mask,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vmax_vx_i16m4_m(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m4_m(mask,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vmax_vx_i16m8_m(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m8_m(mask,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vmax_vx_i32mf2_m(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32mf2_m(mask,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vmax_vx_i32m1_m(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m1_m(mask,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vmax_vx_i32m2_m(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m2_m(mask,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vmax_vx_i32m4_m(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m4_m(mask,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vmax_vx_i32m8_m(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m8_m(mask,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vmax_vx_i64m1_m(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m1_m(mask,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vmax_vx_i64m2_m(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m2_m(mask,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vmax_vx_i64m4_m(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m4_m(mask,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vmax_vx_i64m8_m(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m8_m(mask,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_m_rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_m_rv64-1.c
new file mode 100644
index 00000000000..7175a626153
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_m_rv64-1.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmax_vx_i8mf8_m(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf8_m(mask,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vmax_vx_i8mf4_m(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf4_m(mask,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vmax_vx_i8mf2_m(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf2_m(mask,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vmax_vx_i8m1_m(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m1_m(mask,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vmax_vx_i8m2_m(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m2_m(mask,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vmax_vx_i8m4_m(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m4_m(mask,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vmax_vx_i8m8_m(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m8_m(mask,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vmax_vx_i16mf4_m(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16mf4_m(mask,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vmax_vx_i16mf2_m(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16mf2_m(mask,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vmax_vx_i16m1_m(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m1_m(mask,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vmax_vx_i16m2_m(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m2_m(mask,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vmax_vx_i16m4_m(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m4_m(mask,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vmax_vx_i16m8_m(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m8_m(mask,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vmax_vx_i32mf2_m(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32mf2_m(mask,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vmax_vx_i32m1_m(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m1_m(mask,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vmax_vx_i32m2_m(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m2_m(mask,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vmax_vx_i32m4_m(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m4_m(mask,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vmax_vx_i32m8_m(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m8_m(mask,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vmax_vx_i64m1_m(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m1_m(mask,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vmax_vx_i64m2_m(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m2_m(mask,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vmax_vx_i64m4_m(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m4_m(mask,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vmax_vx_i64m8_m(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m8_m(mask,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_m_rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_m_rv64-2.c
new file mode 100644
index 00000000000..263c74d2ac8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_m_rv64-2.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmax_vx_i8mf8_m(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf8_m(mask,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vmax_vx_i8mf4_m(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf4_m(mask,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vmax_vx_i8mf2_m(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf2_m(mask,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vmax_vx_i8m1_m(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m1_m(mask,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vmax_vx_i8m2_m(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m2_m(mask,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vmax_vx_i8m4_m(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m4_m(mask,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vmax_vx_i8m8_m(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m8_m(mask,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vmax_vx_i16mf4_m(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16mf4_m(mask,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vmax_vx_i16mf2_m(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16mf2_m(mask,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vmax_vx_i16m1_m(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m1_m(mask,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vmax_vx_i16m2_m(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m2_m(mask,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vmax_vx_i16m4_m(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m4_m(mask,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vmax_vx_i16m8_m(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m8_m(mask,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vmax_vx_i32mf2_m(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32mf2_m(mask,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vmax_vx_i32m1_m(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m1_m(mask,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vmax_vx_i32m2_m(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m2_m(mask,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vmax_vx_i32m4_m(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m4_m(mask,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vmax_vx_i32m8_m(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m8_m(mask,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vmax_vx_i64m1_m(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m1_m(mask,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vmax_vx_i64m2_m(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m2_m(mask,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vmax_vx_i64m4_m(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m4_m(mask,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vmax_vx_i64m8_m(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m8_m(mask,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_m_rv64-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_m_rv64-3.c
new file mode 100644
index 00000000000..e070165552c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_m_rv64-3.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmax_vx_i8mf8_m(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf8_m(mask,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vmax_vx_i8mf4_m(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf4_m(mask,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vmax_vx_i8mf2_m(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf2_m(mask,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vmax_vx_i8m1_m(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m1_m(mask,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vmax_vx_i8m2_m(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m2_m(mask,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vmax_vx_i8m4_m(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m4_m(mask,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vmax_vx_i8m8_m(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m8_m(mask,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vmax_vx_i16mf4_m(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16mf4_m(mask,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vmax_vx_i16mf2_m(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16mf2_m(mask,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vmax_vx_i16m1_m(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m1_m(mask,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vmax_vx_i16m2_m(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m2_m(mask,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vmax_vx_i16m4_m(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m4_m(mask,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vmax_vx_i16m8_m(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m8_m(mask,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vmax_vx_i32mf2_m(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32mf2_m(mask,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vmax_vx_i32m1_m(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m1_m(mask,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vmax_vx_i32m2_m(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m2_m(mask,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vmax_vx_i32m4_m(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m4_m(mask,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vmax_vx_i32m8_m(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m8_m(mask,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vmax_vx_i64m1_m(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m1_m(mask,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vmax_vx_i64m2_m(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m2_m(mask,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vmax_vx_i64m4_m(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m4_m(mask,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vmax_vx_i64m8_m(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m8_m(mask,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_mu_rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_mu_rv32-1.c
new file mode 100644
index 00000000000..82c9dada484
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_mu_rv32-1.c
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmax_vx_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vmax_vx_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vmax_vx_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vmax_vx_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m1_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vmax_vx_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vmax_vx_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vmax_vx_i8m8_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vmax_vx_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16mf4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vmax_vx_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16mf2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vmax_vx_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m1_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vmax_vx_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vmax_vx_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vmax_vx_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vmax_vx_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32mf2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vmax_vx_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m1_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vmax_vx_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vmax_vx_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vmax_vx_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vmax_vx_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m1_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vmax_vx_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vmax_vx_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vmax_vx_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m8_mu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_mu_rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_mu_rv32-2.c
new file mode 100644
index 00000000000..25abdbca0e1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_mu_rv32-2.c
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmax_vx_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf8_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vmax_vx_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf4_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vmax_vx_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf2_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vmax_vx_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m1_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vmax_vx_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m2_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vmax_vx_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m4_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vmax_vx_i8m8_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m8_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vmax_vx_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16mf4_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vmax_vx_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16mf2_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vmax_vx_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m1_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vmax_vx_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m2_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vmax_vx_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m4_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vmax_vx_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m8_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vmax_vx_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32mf2_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vmax_vx_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m1_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vmax_vx_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m2_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vmax_vx_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m4_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vmax_vx_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m8_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vmax_vx_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m1_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vmax_vx_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m2_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vmax_vx_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m4_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vmax_vx_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m8_mu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_mu_rv32-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_mu_rv32-3.c
new file mode 100644
index 00000000000..c3a3686e645
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_mu_rv32-3.c
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmax_vx_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf8_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vmax_vx_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf4_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vmax_vx_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf2_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vmax_vx_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m1_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vmax_vx_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m2_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vmax_vx_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m4_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vmax_vx_i8m8_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m8_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vmax_vx_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16mf4_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vmax_vx_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16mf2_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vmax_vx_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m1_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vmax_vx_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m2_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vmax_vx_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m4_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vmax_vx_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m8_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vmax_vx_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32mf2_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vmax_vx_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m1_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vmax_vx_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m2_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vmax_vx_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m4_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vmax_vx_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m8_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vmax_vx_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m1_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vmax_vx_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m2_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vmax_vx_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m4_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vmax_vx_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m8_mu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_mu_rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_mu_rv64-1.c
new file mode 100644
index 00000000000..2255e132628
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_mu_rv64-1.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmax_vx_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vmax_vx_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vmax_vx_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vmax_vx_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m1_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vmax_vx_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vmax_vx_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vmax_vx_i8m8_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vmax_vx_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16mf4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vmax_vx_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16mf2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vmax_vx_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m1_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vmax_vx_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vmax_vx_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vmax_vx_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vmax_vx_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32mf2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vmax_vx_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m1_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vmax_vx_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vmax_vx_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vmax_vx_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vmax_vx_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m1_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vmax_vx_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vmax_vx_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vmax_vx_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m8_mu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_mu_rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_mu_rv64-2.c
new file mode 100644
index 00000000000..d4de8d3a9b5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_mu_rv64-2.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmax_vx_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf8_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vmax_vx_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf4_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vmax_vx_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf2_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vmax_vx_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m1_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vmax_vx_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m2_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vmax_vx_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m4_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vmax_vx_i8m8_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m8_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vmax_vx_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16mf4_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vmax_vx_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16mf2_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vmax_vx_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m1_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vmax_vx_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m2_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vmax_vx_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m4_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vmax_vx_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m8_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vmax_vx_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32mf2_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vmax_vx_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m1_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vmax_vx_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m2_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vmax_vx_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m4_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vmax_vx_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m8_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vmax_vx_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m1_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vmax_vx_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m2_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vmax_vx_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m4_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vmax_vx_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m8_mu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_mu_rv64-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_mu_rv64-3.c
new file mode 100644
index 00000000000..c484b816de7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_mu_rv64-3.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmax_vx_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf8_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vmax_vx_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf4_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vmax_vx_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf2_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vmax_vx_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m1_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vmax_vx_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m2_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vmax_vx_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m4_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vmax_vx_i8m8_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m8_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vmax_vx_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16mf4_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vmax_vx_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16mf2_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vmax_vx_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m1_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vmax_vx_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m2_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vmax_vx_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m4_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vmax_vx_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m8_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vmax_vx_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32mf2_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vmax_vx_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m1_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vmax_vx_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m2_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vmax_vx_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m4_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vmax_vx_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m8_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vmax_vx_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m1_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vmax_vx_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m2_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vmax_vx_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m4_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vmax_vx_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m8_mu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_rv32-1.c
new file mode 100644
index 00000000000..b9894f05268
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_rv32-1.c
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmax_vx_i8mf8(vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf8(op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vmax_vx_i8mf4(vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf4(op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vmax_vx_i8mf2(vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf2(op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vmax_vx_i8m1(vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m1(op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vmax_vx_i8m2(vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m2(op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vmax_vx_i8m4(vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m4(op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vmax_vx_i8m8(vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m8(op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vmax_vx_i16mf4(vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16mf4(op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vmax_vx_i16mf2(vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16mf2(op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vmax_vx_i16m1(vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m1(op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vmax_vx_i16m2(vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m2(op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vmax_vx_i16m4(vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m4(op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vmax_vx_i16m8(vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m8(op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vmax_vx_i32mf2(vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32mf2(op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vmax_vx_i32m1(vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m1(op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vmax_vx_i32m2(vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m2(op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vmax_vx_i32m4(vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m4(op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vmax_vx_i32m8(vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m8(op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vmax_vx_i64m1(vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m1(op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vmax_vx_i64m2(vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m2(op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vmax_vx_i64m4(vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m4(op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vmax_vx_i64m8(vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m8(op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_rv32-2.c
new file mode 100644
index 00000000000..b53e033f83f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_rv32-2.c
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmax_vx_i8mf8(vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf8(op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vmax_vx_i8mf4(vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf4(op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vmax_vx_i8mf2(vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf2(op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vmax_vx_i8m1(vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m1(op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vmax_vx_i8m2(vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m2(op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vmax_vx_i8m4(vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m4(op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vmax_vx_i8m8(vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m8(op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vmax_vx_i16mf4(vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16mf4(op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vmax_vx_i16mf2(vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16mf2(op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vmax_vx_i16m1(vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m1(op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vmax_vx_i16m2(vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m2(op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vmax_vx_i16m4(vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m4(op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vmax_vx_i16m8(vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m8(op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vmax_vx_i32mf2(vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32mf2(op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vmax_vx_i32m1(vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m1(op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vmax_vx_i32m2(vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m2(op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vmax_vx_i32m4(vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m4(op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vmax_vx_i32m8(vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m8(op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vmax_vx_i64m1(vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m1(op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vmax_vx_i64m2(vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m2(op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vmax_vx_i64m4(vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m4(op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vmax_vx_i64m8(vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m8(op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_rv32-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_rv32-3.c
new file mode 100644
index 00000000000..769434cb83e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_rv32-3.c
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmax_vx_i8mf8(vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf8(op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vmax_vx_i8mf4(vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf4(op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vmax_vx_i8mf2(vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf2(op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vmax_vx_i8m1(vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m1(op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vmax_vx_i8m2(vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m2(op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vmax_vx_i8m4(vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m4(op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vmax_vx_i8m8(vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m8(op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vmax_vx_i16mf4(vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16mf4(op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vmax_vx_i16mf2(vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16mf2(op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vmax_vx_i16m1(vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m1(op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vmax_vx_i16m2(vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m2(op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vmax_vx_i16m4(vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m4(op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vmax_vx_i16m8(vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m8(op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vmax_vx_i32mf2(vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32mf2(op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vmax_vx_i32m1(vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m1(op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vmax_vx_i32m2(vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m2(op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vmax_vx_i32m4(vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m4(op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vmax_vx_i32m8(vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m8(op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vmax_vx_i64m1(vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m1(op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vmax_vx_i64m2(vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m2(op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vmax_vx_i64m4(vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m4(op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vmax_vx_i64m8(vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m8(op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_rv64-1.c
new file mode 100644
index 00000000000..608285e95c3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_rv64-1.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmax_vx_i8mf8(vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf8(op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vmax_vx_i8mf4(vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf4(op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vmax_vx_i8mf2(vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf2(op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vmax_vx_i8m1(vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m1(op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vmax_vx_i8m2(vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m2(op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vmax_vx_i8m4(vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m4(op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vmax_vx_i8m8(vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m8(op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vmax_vx_i16mf4(vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16mf4(op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vmax_vx_i16mf2(vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16mf2(op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vmax_vx_i16m1(vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m1(op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vmax_vx_i16m2(vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m2(op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vmax_vx_i16m4(vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m4(op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vmax_vx_i16m8(vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m8(op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vmax_vx_i32mf2(vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32mf2(op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vmax_vx_i32m1(vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m1(op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vmax_vx_i32m2(vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m2(op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vmax_vx_i32m4(vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m4(op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vmax_vx_i32m8(vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m8(op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vmax_vx_i64m1(vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m1(op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vmax_vx_i64m2(vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m2(op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vmax_vx_i64m4(vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m4(op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vmax_vx_i64m8(vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m8(op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_rv64-2.c
new file mode 100644
index 00000000000..3d0ad72ee3a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_rv64-2.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmax_vx_i8mf8(vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf8(op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vmax_vx_i8mf4(vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf4(op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vmax_vx_i8mf2(vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf2(op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vmax_vx_i8m1(vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m1(op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vmax_vx_i8m2(vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m2(op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vmax_vx_i8m4(vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m4(op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vmax_vx_i8m8(vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m8(op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vmax_vx_i16mf4(vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16mf4(op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vmax_vx_i16mf2(vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16mf2(op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vmax_vx_i16m1(vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m1(op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vmax_vx_i16m2(vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m2(op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vmax_vx_i16m4(vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m4(op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vmax_vx_i16m8(vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m8(op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vmax_vx_i32mf2(vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32mf2(op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vmax_vx_i32m1(vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m1(op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vmax_vx_i32m2(vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m2(op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vmax_vx_i32m4(vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m4(op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vmax_vx_i32m8(vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m8(op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vmax_vx_i64m1(vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m1(op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vmax_vx_i64m2(vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m2(op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vmax_vx_i64m4(vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m4(op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vmax_vx_i64m8(vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m8(op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_rv64-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_rv64-3.c
new file mode 100644
index 00000000000..02452507109
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_rv64-3.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmax_vx_i8mf8(vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf8(op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vmax_vx_i8mf4(vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf4(op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vmax_vx_i8mf2(vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf2(op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vmax_vx_i8m1(vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m1(op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vmax_vx_i8m2(vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m2(op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vmax_vx_i8m4(vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m4(op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vmax_vx_i8m8(vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m8(op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vmax_vx_i16mf4(vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16mf4(op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vmax_vx_i16mf2(vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16mf2(op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vmax_vx_i16m1(vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m1(op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vmax_vx_i16m2(vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m2(op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vmax_vx_i16m4(vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m4(op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vmax_vx_i16m8(vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m8(op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vmax_vx_i32mf2(vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32mf2(op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vmax_vx_i32m1(vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m1(op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vmax_vx_i32m2(vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m2(op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vmax_vx_i32m4(vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m4(op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vmax_vx_i32m8(vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m8(op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vmax_vx_i64m1(vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m1(op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vmax_vx_i64m2(vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m2(op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vmax_vx_i64m4(vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m4(op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vmax_vx_i64m8(vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m8(op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tu_rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tu_rv32-1.c
new file mode 100644
index 00000000000..f683c0861d7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tu_rv32-1.c
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmax_vx_i8mf8_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf8_tu(merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vmax_vx_i8mf4_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf4_tu(merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vmax_vx_i8mf2_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf2_tu(merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vmax_vx_i8m1_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m1_tu(merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vmax_vx_i8m2_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m2_tu(merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vmax_vx_i8m4_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m4_tu(merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vmax_vx_i8m8_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m8_tu(merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vmax_vx_i16mf4_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16mf4_tu(merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vmax_vx_i16mf2_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16mf2_tu(merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vmax_vx_i16m1_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m1_tu(merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vmax_vx_i16m2_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m2_tu(merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vmax_vx_i16m4_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m4_tu(merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vmax_vx_i16m8_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m8_tu(merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vmax_vx_i32mf2_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32mf2_tu(merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vmax_vx_i32m1_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m1_tu(merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vmax_vx_i32m2_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m2_tu(merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vmax_vx_i32m4_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m4_tu(merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vmax_vx_i32m8_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m8_tu(merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vmax_vx_i64m1_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m1_tu(merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vmax_vx_i64m2_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m2_tu(merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vmax_vx_i64m4_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m4_tu(merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vmax_vx_i64m8_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m8_tu(merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tu_rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tu_rv32-2.c
new file mode 100644
index 00000000000..92cbf0868c5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tu_rv32-2.c
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmax_vx_i8mf8_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf8_tu(merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vmax_vx_i8mf4_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf4_tu(merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vmax_vx_i8mf2_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf2_tu(merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vmax_vx_i8m1_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m1_tu(merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vmax_vx_i8m2_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m2_tu(merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vmax_vx_i8m4_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m4_tu(merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vmax_vx_i8m8_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m8_tu(merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vmax_vx_i16mf4_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16mf4_tu(merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vmax_vx_i16mf2_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16mf2_tu(merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vmax_vx_i16m1_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m1_tu(merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vmax_vx_i16m2_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m2_tu(merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vmax_vx_i16m4_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m4_tu(merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vmax_vx_i16m8_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m8_tu(merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vmax_vx_i32mf2_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32mf2_tu(merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vmax_vx_i32m1_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m1_tu(merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vmax_vx_i32m2_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m2_tu(merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vmax_vx_i32m4_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m4_tu(merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vmax_vx_i32m8_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m8_tu(merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vmax_vx_i64m1_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m1_tu(merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vmax_vx_i64m2_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m2_tu(merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vmax_vx_i64m4_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m4_tu(merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vmax_vx_i64m8_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m8_tu(merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tu_rv32-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tu_rv32-3.c
new file mode 100644
index 00000000000..5036c3a6b0b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tu_rv32-3.c
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmax_vx_i8mf8_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf8_tu(merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vmax_vx_i8mf4_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf4_tu(merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vmax_vx_i8mf2_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf2_tu(merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vmax_vx_i8m1_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m1_tu(merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vmax_vx_i8m2_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m2_tu(merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vmax_vx_i8m4_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m4_tu(merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vmax_vx_i8m8_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m8_tu(merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vmax_vx_i16mf4_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16mf4_tu(merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vmax_vx_i16mf2_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16mf2_tu(merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vmax_vx_i16m1_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m1_tu(merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vmax_vx_i16m2_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m2_tu(merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vmax_vx_i16m4_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m4_tu(merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vmax_vx_i16m8_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m8_tu(merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vmax_vx_i32mf2_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32mf2_tu(merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vmax_vx_i32m1_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m1_tu(merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vmax_vx_i32m2_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m2_tu(merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vmax_vx_i32m4_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m4_tu(merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vmax_vx_i32m8_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m8_tu(merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vmax_vx_i64m1_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m1_tu(merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vmax_vx_i64m2_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m2_tu(merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vmax_vx_i64m4_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m4_tu(merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vmax_vx_i64m8_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m8_tu(merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tu_rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tu_rv64-1.c
new file mode 100644
index 00000000000..e3f847f6772
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tu_rv64-1.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmax_vx_i8mf8_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf8_tu(merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vmax_vx_i8mf4_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf4_tu(merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vmax_vx_i8mf2_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf2_tu(merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vmax_vx_i8m1_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m1_tu(merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vmax_vx_i8m2_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m2_tu(merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vmax_vx_i8m4_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m4_tu(merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vmax_vx_i8m8_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m8_tu(merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vmax_vx_i16mf4_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16mf4_tu(merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vmax_vx_i16mf2_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16mf2_tu(merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vmax_vx_i16m1_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m1_tu(merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vmax_vx_i16m2_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m2_tu(merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vmax_vx_i16m4_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m4_tu(merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vmax_vx_i16m8_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m8_tu(merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vmax_vx_i32mf2_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32mf2_tu(merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vmax_vx_i32m1_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m1_tu(merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vmax_vx_i32m2_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m2_tu(merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vmax_vx_i32m4_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m4_tu(merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vmax_vx_i32m8_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m8_tu(merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vmax_vx_i64m1_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m1_tu(merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vmax_vx_i64m2_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m2_tu(merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vmax_vx_i64m4_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m4_tu(merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vmax_vx_i64m8_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m8_tu(merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tu_rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tu_rv64-2.c
new file mode 100644
index 00000000000..9400b22379f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tu_rv64-2.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmax_vx_i8mf8_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf8_tu(merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vmax_vx_i8mf4_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf4_tu(merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vmax_vx_i8mf2_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf2_tu(merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vmax_vx_i8m1_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m1_tu(merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vmax_vx_i8m2_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m2_tu(merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vmax_vx_i8m4_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m4_tu(merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vmax_vx_i8m8_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m8_tu(merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vmax_vx_i16mf4_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16mf4_tu(merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vmax_vx_i16mf2_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16mf2_tu(merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vmax_vx_i16m1_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m1_tu(merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vmax_vx_i16m2_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m2_tu(merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vmax_vx_i16m4_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m4_tu(merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vmax_vx_i16m8_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m8_tu(merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vmax_vx_i32mf2_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32mf2_tu(merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vmax_vx_i32m1_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m1_tu(merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vmax_vx_i32m2_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m2_tu(merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vmax_vx_i32m4_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m4_tu(merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vmax_vx_i32m8_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m8_tu(merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vmax_vx_i64m1_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m1_tu(merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vmax_vx_i64m2_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m2_tu(merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vmax_vx_i64m4_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m4_tu(merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vmax_vx_i64m8_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m8_tu(merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tu_rv64-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tu_rv64-3.c
new file mode 100644
index 00000000000..b9565944678
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tu_rv64-3.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmax_vx_i8mf8_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf8_tu(merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vmax_vx_i8mf4_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf4_tu(merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vmax_vx_i8mf2_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf2_tu(merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vmax_vx_i8m1_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m1_tu(merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vmax_vx_i8m2_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m2_tu(merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vmax_vx_i8m4_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m4_tu(merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vmax_vx_i8m8_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m8_tu(merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vmax_vx_i16mf4_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16mf4_tu(merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vmax_vx_i16mf2_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16mf2_tu(merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vmax_vx_i16m1_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m1_tu(merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vmax_vx_i16m2_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m2_tu(merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vmax_vx_i16m4_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m4_tu(merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vmax_vx_i16m8_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m8_tu(merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vmax_vx_i32mf2_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32mf2_tu(merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vmax_vx_i32m1_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m1_tu(merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vmax_vx_i32m2_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m2_tu(merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vmax_vx_i32m4_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m4_tu(merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vmax_vx_i32m8_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m8_tu(merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vmax_vx_i64m1_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m1_tu(merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vmax_vx_i64m2_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m2_tu(merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vmax_vx_i64m4_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m4_tu(merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vmax_vx_i64m8_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m8_tu(merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tum_rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tum_rv32-1.c
new file mode 100644
index 00000000000..8ff04c42edd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tum_rv32-1.c
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmax_vx_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf8_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vmax_vx_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vmax_vx_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vmax_vx_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m1_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vmax_vx_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vmax_vx_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vmax_vx_i8m8_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m8_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vmax_vx_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16mf4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vmax_vx_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16mf2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vmax_vx_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m1_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vmax_vx_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vmax_vx_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vmax_vx_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m8_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vmax_vx_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32mf2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vmax_vx_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m1_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vmax_vx_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vmax_vx_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vmax_vx_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m8_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vmax_vx_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m1_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vmax_vx_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vmax_vx_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vmax_vx_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m8_tum(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tum_rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tum_rv32-2.c
new file mode 100644
index 00000000000..81c6da1186f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tum_rv32-2.c
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmax_vx_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf8_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vmax_vx_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf4_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vmax_vx_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf2_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vmax_vx_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m1_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vmax_vx_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m2_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vmax_vx_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m4_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vmax_vx_i8m8_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m8_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vmax_vx_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16mf4_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vmax_vx_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16mf2_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vmax_vx_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m1_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vmax_vx_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m2_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vmax_vx_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m4_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vmax_vx_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m8_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vmax_vx_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32mf2_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vmax_vx_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m1_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vmax_vx_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m2_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vmax_vx_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m4_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vmax_vx_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m8_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vmax_vx_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m1_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vmax_vx_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m2_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vmax_vx_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m4_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vmax_vx_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m8_tum(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tum_rv32-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tum_rv32-3.c
new file mode 100644
index 00000000000..1a4d7b4f26b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tum_rv32-3.c
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmax_vx_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf8_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vmax_vx_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf4_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vmax_vx_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf2_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vmax_vx_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m1_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vmax_vx_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m2_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vmax_vx_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m4_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vmax_vx_i8m8_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m8_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vmax_vx_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16mf4_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vmax_vx_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16mf2_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vmax_vx_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m1_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vmax_vx_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m2_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vmax_vx_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m4_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vmax_vx_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m8_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vmax_vx_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32mf2_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vmax_vx_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m1_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vmax_vx_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m2_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vmax_vx_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m4_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vmax_vx_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m8_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vmax_vx_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m1_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vmax_vx_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m2_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vmax_vx_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m4_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vmax_vx_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m8_tum(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tum_rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tum_rv64-1.c
new file mode 100644
index 00000000000..b1aa2988d8c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tum_rv64-1.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmax_vx_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf8_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vmax_vx_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vmax_vx_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vmax_vx_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m1_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vmax_vx_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vmax_vx_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vmax_vx_i8m8_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m8_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vmax_vx_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16mf4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vmax_vx_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16mf2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vmax_vx_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m1_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vmax_vx_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vmax_vx_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vmax_vx_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m8_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vmax_vx_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32mf2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vmax_vx_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m1_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vmax_vx_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vmax_vx_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vmax_vx_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m8_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vmax_vx_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m1_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vmax_vx_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m2_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vmax_vx_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m4_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vmax_vx_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m8_tum(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tum_rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tum_rv64-2.c
new file mode 100644
index 00000000000..a29597dbc7f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tum_rv64-2.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmax_vx_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf8_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vmax_vx_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf4_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vmax_vx_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf2_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vmax_vx_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m1_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vmax_vx_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m2_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vmax_vx_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m4_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vmax_vx_i8m8_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m8_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vmax_vx_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16mf4_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vmax_vx_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16mf2_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vmax_vx_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m1_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vmax_vx_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m2_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vmax_vx_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m4_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vmax_vx_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m8_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vmax_vx_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32mf2_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vmax_vx_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m1_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vmax_vx_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m2_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vmax_vx_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m4_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vmax_vx_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m8_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vmax_vx_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m1_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vmax_vx_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m2_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vmax_vx_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m4_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vmax_vx_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m8_tum(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tum_rv64-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tum_rv64-3.c
new file mode 100644
index 00000000000..074d1dacf95
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tum_rv64-3.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmax_vx_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf8_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vmax_vx_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf4_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vmax_vx_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf2_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vmax_vx_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m1_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vmax_vx_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m2_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vmax_vx_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m4_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vmax_vx_i8m8_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m8_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vmax_vx_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16mf4_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vmax_vx_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16mf2_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vmax_vx_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m1_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vmax_vx_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m2_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vmax_vx_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m4_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vmax_vx_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m8_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vmax_vx_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32mf2_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vmax_vx_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m1_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vmax_vx_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m2_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vmax_vx_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m4_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vmax_vx_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m8_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vmax_vx_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m1_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vmax_vx_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m2_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vmax_vx_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m4_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vmax_vx_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m8_tum(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tumu_rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tumu_rv32-1.c
new file mode 100644
index 00000000000..d11339e0c29
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tumu_rv32-1.c
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmax_vx_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf8_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vmax_vx_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vmax_vx_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vmax_vx_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m1_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vmax_vx_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vmax_vx_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vmax_vx_i8m8_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m8_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vmax_vx_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16mf4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vmax_vx_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16mf2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vmax_vx_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m1_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vmax_vx_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vmax_vx_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vmax_vx_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m8_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vmax_vx_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32mf2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vmax_vx_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m1_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vmax_vx_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vmax_vx_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vmax_vx_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m8_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vmax_vx_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m1_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vmax_vx_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vmax_vx_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vmax_vx_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m8_tumu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tumu_rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tumu_rv32-2.c
new file mode 100644
index 00000000000..77e6a5293a3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tumu_rv32-2.c
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmax_vx_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf8_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vmax_vx_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vmax_vx_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vmax_vx_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m1_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vmax_vx_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vmax_vx_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vmax_vx_i8m8_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m8_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vmax_vx_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16mf4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vmax_vx_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16mf2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vmax_vx_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m1_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vmax_vx_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vmax_vx_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vmax_vx_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m8_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vmax_vx_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32mf2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vmax_vx_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m1_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vmax_vx_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vmax_vx_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vmax_vx_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m8_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vmax_vx_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m1_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vmax_vx_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vmax_vx_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vmax_vx_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m8_tumu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tumu_rv32-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tumu_rv32-3.c
new file mode 100644
index 00000000000..0ab53d3aea7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tumu_rv32-3.c
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmax_vx_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf8_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vmax_vx_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vmax_vx_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vmax_vx_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m1_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vmax_vx_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vmax_vx_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vmax_vx_i8m8_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m8_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vmax_vx_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16mf4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vmax_vx_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16mf2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vmax_vx_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m1_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vmax_vx_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vmax_vx_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vmax_vx_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m8_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vmax_vx_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32mf2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vmax_vx_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m1_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vmax_vx_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vmax_vx_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vmax_vx_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m8_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vmax_vx_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m1_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vmax_vx_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vmax_vx_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vmax_vx_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m8_tumu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 4 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tumu_rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tumu_rv64-1.c
new file mode 100644
index 00000000000..809b7fb6b28
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tumu_rv64-1.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmax_vx_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf8_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vmax_vx_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vmax_vx_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vmax_vx_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m1_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vmax_vx_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vmax_vx_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vmax_vx_i8m8_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m8_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vmax_vx_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16mf4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vmax_vx_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16mf2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vmax_vx_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m1_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vmax_vx_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vmax_vx_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vmax_vx_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m8_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vmax_vx_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32mf2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vmax_vx_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m1_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vmax_vx_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vmax_vx_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vmax_vx_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m8_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vmax_vx_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m1_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vmax_vx_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m2_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vmax_vx_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m4_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vmax_vx_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m8_tumu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tumu_rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tumu_rv64-2.c
new file mode 100644
index 00000000000..3793a66e7ab
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tumu_rv64-2.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmax_vx_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf8_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vmax_vx_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vmax_vx_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vmax_vx_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m1_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vmax_vx_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vmax_vx_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vmax_vx_i8m8_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m8_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vmax_vx_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16mf4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vmax_vx_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16mf2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vmax_vx_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m1_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vmax_vx_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vmax_vx_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vmax_vx_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m8_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vmax_vx_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32mf2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vmax_vx_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m1_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vmax_vx_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vmax_vx_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vmax_vx_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m8_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vmax_vx_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m1_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vmax_vx_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m2_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vmax_vx_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m4_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vmax_vx_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m8_tumu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tumu_rv64-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tumu_rv64-3.c
new file mode 100644
index 00000000000..98950f685a7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmax_vx_tumu_rv64-3.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmax_vx_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf8_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vmax_vx_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vmax_vx_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8mf2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vmax_vx_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m1_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vmax_vx_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vmax_vx_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vmax_vx_i8m8_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i8m8_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vmax_vx_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16mf4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vmax_vx_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16mf2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vmax_vx_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m1_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vmax_vx_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vmax_vx_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vmax_vx_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i16m8_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vmax_vx_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32mf2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vmax_vx_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m1_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vmax_vx_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vmax_vx_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vmax_vx_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i32m8_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vmax_vx_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m1_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vmax_vx_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m2_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vmax_vx_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m4_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vmax_vx_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_vx_i64m8_tumu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t} 1 } } */
-- 
2.36.1


^ permalink raw reply	[flat|nested] 2+ messages in thread

* [PATCH] RISC-V: Add vmax.vx C++ API tests.
@ 2023-02-03  8:09 juzhe.zhong
  0 siblings, 0 replies; 2+ messages in thread
From: juzhe.zhong @ 2023-02-03  8:09 UTC (permalink / raw)
  To: gcc-patches; +Cc: kito.cheng, Ju-Zhe Zhong

From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>

gcc/testsuite/ChangeLog:

        * g++.target/riscv/rvv/base/vmax_vx_mu_rv32-1.C: New test.
        * g++.target/riscv/rvv/base/vmax_vx_mu_rv32-2.C: New test.
        * g++.target/riscv/rvv/base/vmax_vx_mu_rv32-3.C: New test.
        * g++.target/riscv/rvv/base/vmax_vx_mu_rv64-1.C: New test.
        * g++.target/riscv/rvv/base/vmax_vx_mu_rv64-2.C: New test.
        * g++.target/riscv/rvv/base/vmax_vx_mu_rv64-3.C: New test.
        * g++.target/riscv/rvv/base/vmax_vx_rv32-1.C: New test.
        * g++.target/riscv/rvv/base/vmax_vx_rv32-2.C: New test.
        * g++.target/riscv/rvv/base/vmax_vx_rv32-3.C: New test.
        * g++.target/riscv/rvv/base/vmax_vx_rv64-1.C: New test.
        * g++.target/riscv/rvv/base/vmax_vx_rv64-2.C: New test.
        * g++.target/riscv/rvv/base/vmax_vx_rv64-3.C: New test.
        * g++.target/riscv/rvv/base/vmax_vx_tu_rv32-1.C: New test.
        * g++.target/riscv/rvv/base/vmax_vx_tu_rv32-2.C: New test.
        * g++.target/riscv/rvv/base/vmax_vx_tu_rv32-3.C: New test.
        * g++.target/riscv/rvv/base/vmax_vx_tu_rv64-1.C: New test.
        * g++.target/riscv/rvv/base/vmax_vx_tu_rv64-2.C: New test.
        * g++.target/riscv/rvv/base/vmax_vx_tu_rv64-3.C: New test.
        * g++.target/riscv/rvv/base/vmax_vx_tum_rv32-1.C: New test.
        * g++.target/riscv/rvv/base/vmax_vx_tum_rv32-2.C: New test.
        * g++.target/riscv/rvv/base/vmax_vx_tum_rv32-3.C: New test.
        * g++.target/riscv/rvv/base/vmax_vx_tum_rv64-1.C: New test.
        * g++.target/riscv/rvv/base/vmax_vx_tum_rv64-2.C: New test.
        * g++.target/riscv/rvv/base/vmax_vx_tum_rv64-3.C: New test.
        * g++.target/riscv/rvv/base/vmax_vx_tumu_rv32-1.C: New test.
        * g++.target/riscv/rvv/base/vmax_vx_tumu_rv32-2.C: New test.
        * g++.target/riscv/rvv/base/vmax_vx_tumu_rv32-3.C: New test.
        * g++.target/riscv/rvv/base/vmax_vx_tumu_rv64-1.C: New test.
        * g++.target/riscv/rvv/base/vmax_vx_tumu_rv64-2.C: New test.
        * g++.target/riscv/rvv/base/vmax_vx_tumu_rv64-3.C: New test.

---
 .../riscv/rvv/base/vmax_vx_mu_rv32-1.C        | 157 +++++++++
 .../riscv/rvv/base/vmax_vx_mu_rv32-2.C        | 157 +++++++++
 .../riscv/rvv/base/vmax_vx_mu_rv32-3.C        | 157 +++++++++
 .../riscv/rvv/base/vmax_vx_mu_rv64-1.C        | 160 +++++++++
 .../riscv/rvv/base/vmax_vx_mu_rv64-2.C        | 160 +++++++++
 .../riscv/rvv/base/vmax_vx_mu_rv64-3.C        | 160 +++++++++
 .../riscv/rvv/base/vmax_vx_rv32-1.C           | 308 +++++++++++++++++
 .../riscv/rvv/base/vmax_vx_rv32-2.C           | 308 +++++++++++++++++
 .../riscv/rvv/base/vmax_vx_rv32-3.C           | 308 +++++++++++++++++
 .../riscv/rvv/base/vmax_vx_rv64-1.C           | 314 ++++++++++++++++++
 .../riscv/rvv/base/vmax_vx_rv64-2.C           | 314 ++++++++++++++++++
 .../riscv/rvv/base/vmax_vx_rv64-3.C           | 314 ++++++++++++++++++
 .../riscv/rvv/base/vmax_vx_tu_rv32-1.C        | 157 +++++++++
 .../riscv/rvv/base/vmax_vx_tu_rv32-2.C        | 157 +++++++++
 .../riscv/rvv/base/vmax_vx_tu_rv32-3.C        | 157 +++++++++
 .../riscv/rvv/base/vmax_vx_tu_rv64-1.C        | 160 +++++++++
 .../riscv/rvv/base/vmax_vx_tu_rv64-2.C        | 160 +++++++++
 .../riscv/rvv/base/vmax_vx_tu_rv64-3.C        | 160 +++++++++
 .../riscv/rvv/base/vmax_vx_tum_rv32-1.C       | 157 +++++++++
 .../riscv/rvv/base/vmax_vx_tum_rv32-2.C       | 157 +++++++++
 .../riscv/rvv/base/vmax_vx_tum_rv32-3.C       | 157 +++++++++
 .../riscv/rvv/base/vmax_vx_tum_rv64-1.C       | 160 +++++++++
 .../riscv/rvv/base/vmax_vx_tum_rv64-2.C       | 160 +++++++++
 .../riscv/rvv/base/vmax_vx_tum_rv64-3.C       | 160 +++++++++
 .../riscv/rvv/base/vmax_vx_tumu_rv32-1.C      | 157 +++++++++
 .../riscv/rvv/base/vmax_vx_tumu_rv32-2.C      | 157 +++++++++
 .../riscv/rvv/base/vmax_vx_tumu_rv32-3.C      | 157 +++++++++
 .../riscv/rvv/base/vmax_vx_tumu_rv64-1.C      | 160 +++++++++
 .../riscv/rvv/base/vmax_vx_tumu_rv64-2.C      | 160 +++++++++
 .../riscv/rvv/base/vmax_vx_tumu_rv64-3.C      | 160 +++++++++
 30 files changed, 5670 insertions(+)
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_mu_rv32-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_mu_rv32-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_mu_rv32-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_mu_rv64-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_mu_rv64-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_mu_rv64-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_rv32-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_rv32-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_rv32-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_rv64-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_rv64-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_rv64-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tu_rv32-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tu_rv32-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tu_rv32-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tu_rv64-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tu_rv64-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tu_rv64-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tum_rv32-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tum_rv32-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tum_rv32-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tum_rv64-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tum_rv64-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tum_rv64-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tumu_rv32-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tumu_rv32-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tumu_rv32-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tumu_rv64-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tumu_rv64-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tumu_rv64-3.C

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_mu_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_mu_rv32-1.C
new file mode 100644
index 00000000000..684cb97c8ef
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_mu_rv32-1.C
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmax_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vmax_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vmax_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vmax_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vmax_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vmax_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vmax_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vmax_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vmax_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vmax_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vmax_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vmax_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vmax_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vmax_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vmax_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vmax_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vmax_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vmax_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vmax_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vmax_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vmax_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vmax_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_mu_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_mu_rv32-2.C
new file mode 100644
index 00000000000..55152a0109a
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_mu_rv32-2.C
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmax_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vmax_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vmax_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vmax_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vmax_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vmax_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vmax_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vmax_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vmax_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vmax_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vmax_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vmax_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vmax_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vmax_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vmax_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vmax_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vmax_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vmax_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vmax_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vmax_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vmax_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vmax_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_mu_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_mu_rv32-3.C
new file mode 100644
index 00000000000..2338af2d467
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_mu_rv32-3.C
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmax_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vmax_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vmax_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vmax_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vmax_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vmax_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vmax_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vmax_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vmax_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vmax_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vmax_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vmax_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vmax_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vmax_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vmax_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vmax_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vmax_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vmax_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vmax_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vmax_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vmax_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vmax_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_mu_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_mu_rv64-1.C
new file mode 100644
index 00000000000..faac69b195b
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_mu_rv64-1.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmax_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vmax_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vmax_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vmax_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vmax_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vmax_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vmax_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vmax_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vmax_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vmax_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vmax_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vmax_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vmax_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vmax_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vmax_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vmax_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vmax_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vmax_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vmax_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vmax_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vmax_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vmax_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_mu_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_mu_rv64-2.C
new file mode 100644
index 00000000000..fa23cf69a17
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_mu_rv64-2.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmax_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vmax_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vmax_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vmax_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vmax_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vmax_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vmax_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vmax_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vmax_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vmax_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vmax_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vmax_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vmax_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vmax_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vmax_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vmax_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vmax_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vmax_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vmax_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vmax_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vmax_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vmax_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_mu_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_mu_rv64-3.C
new file mode 100644
index 00000000000..a2adba3d90f
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_mu_rv64-3.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmax_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vmax_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vmax_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vmax_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vmax_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vmax_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vmax_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vmax_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vmax_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vmax_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vmax_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vmax_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vmax_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vmax_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vmax_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vmax_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vmax_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vmax_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vmax_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vmax_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vmax_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vmax_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_mu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_rv32-1.C
new file mode 100644
index 00000000000..93c8d324c8e
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_rv32-1.C
@@ -0,0 +1,308 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmax(vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vmax(vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vmax(vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vmax(vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vmax(vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vmax(vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vmax(vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vmax(vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vmax(vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vmax(vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vmax(vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vmax(vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vmax(vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vmax(vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vmax(vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vmax(vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vmax(vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vmax(vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vmax(vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vmax(vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vmax(vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vmax(vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,vl);
+}
+
+
+vint8mf8_t test___riscv_vmax(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vmax(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vmax(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vmax(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vmax(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vmax(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vmax(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vmax(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vmax(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vmax(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vmax(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vmax(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vmax(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vmax(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vmax(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vmax(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vmax(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vmax(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vmax(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vmax(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vmax(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vmax(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_rv32-2.C
new file mode 100644
index 00000000000..3b14b352e11
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_rv32-2.C
@@ -0,0 +1,308 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmax(vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vmax(vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vmax(vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vmax(vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vmax(vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vmax(vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vmax(vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vmax(vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vmax(vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vmax(vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vmax(vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vmax(vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vmax(vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vmax(vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vmax(vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vmax(vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vmax(vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vmax(vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vmax(vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vmax(vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vmax(vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vmax(vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,31);
+}
+
+
+vint8mf8_t test___riscv_vmax(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vmax(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vmax(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vmax(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vmax(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vmax(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vmax(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vmax(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vmax(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vmax(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vmax(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vmax(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vmax(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vmax(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vmax(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vmax(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vmax(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vmax(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vmax(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vmax(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vmax(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vmax(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_rv32-3.C
new file mode 100644
index 00000000000..88e0f47ef48
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_rv32-3.C
@@ -0,0 +1,308 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmax(vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vmax(vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vmax(vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vmax(vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vmax(vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vmax(vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vmax(vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vmax(vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vmax(vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vmax(vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vmax(vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vmax(vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vmax(vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vmax(vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vmax(vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vmax(vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vmax(vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vmax(vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vmax(vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vmax(vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vmax(vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vmax(vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,32);
+}
+
+
+vint8mf8_t test___riscv_vmax(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vmax(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vmax(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vmax(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vmax(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vmax(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vmax(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vmax(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vmax(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vmax(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vmax(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vmax(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vmax(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vmax(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vmax(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vmax(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vmax(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vmax(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vmax(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vmax(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vmax(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vmax(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_rv64-1.C
new file mode 100644
index 00000000000..10180eb2d39
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_rv64-1.C
@@ -0,0 +1,314 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmax(vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vmax(vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vmax(vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vmax(vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vmax(vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vmax(vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vmax(vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vmax(vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vmax(vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vmax(vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vmax(vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vmax(vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vmax(vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vmax(vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vmax(vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vmax(vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vmax(vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vmax(vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vmax(vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vmax(vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vmax(vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vmax(vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,vl);
+}
+
+
+vint8mf8_t test___riscv_vmax(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vmax(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vmax(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vmax(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vmax(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vmax(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vmax(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vmax(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vmax(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vmax(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vmax(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vmax(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vmax(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vmax(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vmax(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vmax(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vmax(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vmax(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vmax(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vmax(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vmax(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vmax(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_rv64-2.C
new file mode 100644
index 00000000000..d101b0c4f34
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_rv64-2.C
@@ -0,0 +1,314 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmax(vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vmax(vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vmax(vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vmax(vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vmax(vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vmax(vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vmax(vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vmax(vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vmax(vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vmax(vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vmax(vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vmax(vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vmax(vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vmax(vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vmax(vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vmax(vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vmax(vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vmax(vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vmax(vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vmax(vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vmax(vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vmax(vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,31);
+}
+
+
+vint8mf8_t test___riscv_vmax(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vmax(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vmax(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vmax(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vmax(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vmax(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vmax(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vmax(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vmax(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vmax(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vmax(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vmax(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vmax(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vmax(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vmax(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vmax(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vmax(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vmax(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vmax(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vmax(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vmax(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vmax(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_rv64-3.C
new file mode 100644
index 00000000000..d3f6451a7fc
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_rv64-3.C
@@ -0,0 +1,314 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmax(vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vmax(vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vmax(vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vmax(vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vmax(vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vmax(vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vmax(vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vmax(vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vmax(vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vmax(vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vmax(vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vmax(vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vmax(vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vmax(vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vmax(vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vmax(vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vmax(vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vmax(vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vmax(vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vmax(vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vmax(vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vmax(vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax(op1,op2,32);
+}
+
+
+vint8mf8_t test___riscv_vmax(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vmax(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vmax(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vmax(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vmax(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vmax(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vmax(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vmax(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vmax(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vmax(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vmax(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vmax(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vmax(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vmax(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vmax(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vmax(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vmax(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vmax(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vmax(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vmax(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vmax(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vmax(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax(mask,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tu_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tu_rv32-1.C
new file mode 100644
index 00000000000..0c404e52d22
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tu_rv32-1.C
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmax_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vmax_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vmax_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vmax_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vmax_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vmax_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vmax_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vmax_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vmax_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vmax_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vmax_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vmax_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vmax_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vmax_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vmax_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vmax_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vmax_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vmax_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vmax_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vmax_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vmax_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vmax_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tu_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tu_rv32-2.C
new file mode 100644
index 00000000000..8116bdeb1c9
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tu_rv32-2.C
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmax_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vmax_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vmax_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vmax_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vmax_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vmax_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vmax_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vmax_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vmax_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vmax_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vmax_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vmax_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vmax_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vmax_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vmax_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vmax_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vmax_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vmax_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vmax_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vmax_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vmax_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vmax_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tu_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tu_rv32-3.C
new file mode 100644
index 00000000000..a4d67e625fc
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tu_rv32-3.C
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmax_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vmax_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vmax_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vmax_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vmax_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vmax_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vmax_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vmax_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vmax_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vmax_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vmax_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vmax_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vmax_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vmax_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vmax_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vmax_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vmax_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vmax_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vmax_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vmax_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vmax_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vmax_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tu_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tu_rv64-1.C
new file mode 100644
index 00000000000..3b0606b0aa1
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tu_rv64-1.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmax_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vmax_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vmax_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vmax_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vmax_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vmax_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vmax_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vmax_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vmax_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vmax_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vmax_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vmax_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vmax_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vmax_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vmax_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vmax_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vmax_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vmax_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vmax_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vmax_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vmax_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vmax_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tu_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tu_rv64-2.C
new file mode 100644
index 00000000000..74078342193
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tu_rv64-2.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmax_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vmax_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vmax_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vmax_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vmax_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vmax_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vmax_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vmax_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vmax_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vmax_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vmax_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vmax_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vmax_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vmax_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vmax_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vmax_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vmax_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vmax_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vmax_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vmax_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vmax_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vmax_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tu_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tu_rv64-3.C
new file mode 100644
index 00000000000..d462491deeb
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tu_rv64-3.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmax_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vmax_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vmax_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vmax_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vmax_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vmax_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vmax_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vmax_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vmax_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vmax_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vmax_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vmax_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vmax_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vmax_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vmax_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vmax_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vmax_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vmax_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vmax_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vmax_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vmax_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vmax_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_tu(merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tum_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tum_rv32-1.C
new file mode 100644
index 00000000000..b1c55d9b694
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tum_rv32-1.C
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmax_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vmax_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vmax_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vmax_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vmax_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vmax_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vmax_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vmax_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vmax_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vmax_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vmax_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vmax_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vmax_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vmax_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vmax_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vmax_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vmax_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vmax_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vmax_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vmax_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vmax_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vmax_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tum_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tum_rv32-2.C
new file mode 100644
index 00000000000..99b78d9613d
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tum_rv32-2.C
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmax_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vmax_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vmax_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vmax_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vmax_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vmax_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vmax_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vmax_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vmax_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vmax_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vmax_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vmax_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vmax_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vmax_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vmax_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vmax_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vmax_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vmax_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vmax_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vmax_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vmax_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vmax_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tum_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tum_rv32-3.C
new file mode 100644
index 00000000000..9d697c2b1ec
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tum_rv32-3.C
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmax_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vmax_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vmax_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vmax_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vmax_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vmax_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vmax_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vmax_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vmax_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vmax_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vmax_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vmax_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vmax_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vmax_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vmax_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vmax_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vmax_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vmax_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vmax_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vmax_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vmax_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vmax_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tum_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tum_rv64-1.C
new file mode 100644
index 00000000000..829f50fbfa2
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tum_rv64-1.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmax_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vmax_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vmax_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vmax_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vmax_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vmax_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vmax_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vmax_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vmax_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vmax_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vmax_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vmax_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vmax_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vmax_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vmax_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vmax_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vmax_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vmax_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vmax_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vmax_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vmax_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vmax_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tum_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tum_rv64-2.C
new file mode 100644
index 00000000000..0089ffed593
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tum_rv64-2.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmax_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vmax_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vmax_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vmax_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vmax_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vmax_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vmax_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vmax_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vmax_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vmax_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vmax_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vmax_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vmax_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vmax_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vmax_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vmax_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vmax_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vmax_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vmax_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vmax_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vmax_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vmax_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tum_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tum_rv64-3.C
new file mode 100644
index 00000000000..4199f3bfeff
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tum_rv64-3.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmax_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vmax_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vmax_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vmax_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vmax_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vmax_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vmax_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vmax_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vmax_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vmax_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vmax_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vmax_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vmax_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vmax_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vmax_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vmax_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vmax_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vmax_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vmax_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vmax_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vmax_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vmax_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_tum(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tumu_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tumu_rv32-1.C
new file mode 100644
index 00000000000..42a644d15b4
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tumu_rv32-1.C
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmax_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vmax_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vmax_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vmax_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vmax_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vmax_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vmax_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vmax_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vmax_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vmax_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vmax_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vmax_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vmax_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vmax_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vmax_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vmax_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vmax_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vmax_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vmax_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vmax_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vmax_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vmax_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tumu_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tumu_rv32-2.C
new file mode 100644
index 00000000000..844d21a2be5
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tumu_rv32-2.C
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmax_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vmax_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vmax_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vmax_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vmax_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vmax_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vmax_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vmax_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vmax_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vmax_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vmax_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vmax_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vmax_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vmax_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vmax_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vmax_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vmax_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vmax_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vmax_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vmax_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vmax_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vmax_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tumu_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tumu_rv32-3.C
new file mode 100644
index 00000000000..270973cce2c
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tumu_rv32-3.C
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmax_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vmax_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vmax_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vmax_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vmax_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vmax_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vmax_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vmax_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vmax_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vmax_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vmax_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vmax_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vmax_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vmax_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vmax_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vmax_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vmax_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vmax_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vmax_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vmax_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vmax_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vmax_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vmax\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tumu_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tumu_rv64-1.C
new file mode 100644
index 00000000000..fa4e497550b
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tumu_rv64-1.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmax_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vmax_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vmax_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vmax_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vmax_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vmax_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vmax_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vmax_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vmax_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vmax_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vmax_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vmax_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vmax_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vmax_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vmax_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vmax_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vmax_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vmax_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vmax_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vmax_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vmax_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vmax_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tumu_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tumu_rv64-2.C
new file mode 100644
index 00000000000..6144308ab71
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tumu_rv64-2.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmax_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vmax_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vmax_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vmax_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vmax_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vmax_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vmax_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vmax_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vmax_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vmax_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vmax_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vmax_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vmax_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vmax_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vmax_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vmax_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vmax_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vmax_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vmax_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vmax_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vmax_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vmax_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tumu_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tumu_rv64-3.C
new file mode 100644
index 00000000000..413712172f8
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_tumu_rv64-3.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vmax_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vmax_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vmax_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vmax_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vmax_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vmax_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vmax_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vmax_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vmax_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vmax_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vmax_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vmax_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vmax_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vmax_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vmax_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vmax_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vmax_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vmax_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vmax_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vmax_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vmax_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vmax_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vmax_tumu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vmax\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
-- 
2.36.1


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2023-02-03  7:23 [PATCH] RISC-V: Add vmax.vx C API tests juzhe.zhong
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