* [PATCH v1] RISC-V: Change the generation mode of ADJUST_SP_RTX from gen_insn to gen_SET.
@ 2023-02-03 9:42 Jin Ma
2023-02-12 11:34 ` Kito Cheng
0 siblings, 1 reply; 2+ messages in thread
From: Jin Ma @ 2023-02-03 9:42 UTC (permalink / raw)
To: gcc-patches; +Cc: kito.cheng, kito.cheng, palmer, Jin Ma
The gen_insn method is used to generate ADJUST_SP_RTX here, which has certain
potential risks:
When the architecture adds pre-processing to `define_insn "adddi3"`, such as
`define_expend "adddi3"`, the gen_expand will be automatically called here,
causing the patern to emit directly, which will cause insn to enter REG_NOTE
for `DWARF` instead of patern.
The following error REG_NOTE occurred:
error: invalid rtl sharing found in the insn:
(insn 19 3 20 2 (parallel [
...
])
(expr_list:REG_CFA_ADJUST_CFA
(insn 18 0 0 (set (reg/f:DI 2 sp)
(plus:DI (reg/f:DI 2 sp)
(const_int -16 [0xfffffffffffffff0]))) -1
(nil))))
In fact, the correct one should be the following:
(insn 19 3 20 2 (parallel [
...
])
(expr_list:REG_CFA_ADJUST_CFA
(set (reg/f:DI 2 sp)
(plus:DI (reg/f:DI 2 sp)
(const_int -16 [0xfffffffffffffff0])))))
Following the treatment of arm or other architectures, it is more reasonable to
use gen_SET here.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_adjust_libcall_cfi_prologue): Change gen_add3_insn
to gen_rtx_SET.
(riscv_adjust_libcall_cfi_epilogue): Likewise.
---
gcc/config/riscv/riscv.cc | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 3b7804b7501..c9c6e53c6d0 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -5054,8 +5054,9 @@ riscv_adjust_libcall_cfi_prologue ()
}
/* Debug info for adjust sp. */
- adjust_sp_rtx = gen_add3_insn (stack_pointer_rtx,
- stack_pointer_rtx, GEN_INT (-saved_size));
+ adjust_sp_rtx =
+ gen_rtx_SET (stack_pointer_rtx,
+ gen_rtx_PLUS (GET_MODE(stack_pointer_rtx), stack_pointer_rtx, GEN_INT (-saved_size)));
dwarf = alloc_reg_note (REG_CFA_ADJUST_CFA, adjust_sp_rtx,
dwarf);
return dwarf;
@@ -5176,8 +5177,9 @@ riscv_adjust_libcall_cfi_epilogue ()
int saved_size = cfun->machine->frame.save_libcall_adjustment;
/* Debug info for adjust sp. */
- adjust_sp_rtx = gen_add3_insn (stack_pointer_rtx,
- stack_pointer_rtx, GEN_INT (saved_size));
+ adjust_sp_rtx =
+ gen_rtx_SET (stack_pointer_rtx,
+ gen_rtx_PLUS (GET_MODE(stack_pointer_rtx), stack_pointer_rtx, GEN_INT (saved_size)));
dwarf = alloc_reg_note (REG_CFA_ADJUST_CFA, adjust_sp_rtx,
dwarf);
--
2.17.1
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: [PATCH v1] RISC-V: Change the generation mode of ADJUST_SP_RTX from gen_insn to gen_SET.
2023-02-03 9:42 [PATCH v1] RISC-V: Change the generation mode of ADJUST_SP_RTX from gen_insn to gen_SET Jin Ma
@ 2023-02-12 11:34 ` Kito Cheng
0 siblings, 0 replies; 2+ messages in thread
From: Kito Cheng @ 2023-02-12 11:34 UTC (permalink / raw)
To: Jin Ma; +Cc: gcc-patches, kito.cheng, palmer
Committed, thanks :)
On Fri, Feb 3, 2023 at 5:45 PM Jin Ma via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> The gen_insn method is used to generate ADJUST_SP_RTX here, which has certain
> potential risks:
>
> When the architecture adds pre-processing to `define_insn "adddi3"`, such as
> `define_expend "adddi3"`, the gen_expand will be automatically called here,
> causing the patern to emit directly, which will cause insn to enter REG_NOTE
> for `DWARF` instead of patern.
>
> The following error REG_NOTE occurred:
> error: invalid rtl sharing found in the insn:
> (insn 19 3 20 2 (parallel [
> ...
> ])
> (expr_list:REG_CFA_ADJUST_CFA
> (insn 18 0 0 (set (reg/f:DI 2 sp)
> (plus:DI (reg/f:DI 2 sp)
> (const_int -16 [0xfffffffffffffff0]))) -1
> (nil))))
>
> In fact, the correct one should be the following:
> (insn 19 3 20 2 (parallel [
> ...
> ])
> (expr_list:REG_CFA_ADJUST_CFA
> (set (reg/f:DI 2 sp)
> (plus:DI (reg/f:DI 2 sp)
> (const_int -16 [0xfffffffffffffff0])))))
>
> Following the treatment of arm or other architectures, it is more reasonable to
> use gen_SET here.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.cc (riscv_adjust_libcall_cfi_prologue): Change gen_add3_insn
> to gen_rtx_SET.
> (riscv_adjust_libcall_cfi_epilogue): Likewise.
> ---
> gcc/config/riscv/riscv.cc | 10 ++++++----
> 1 file changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 3b7804b7501..c9c6e53c6d0 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -5054,8 +5054,9 @@ riscv_adjust_libcall_cfi_prologue ()
> }
>
> /* Debug info for adjust sp. */
> - adjust_sp_rtx = gen_add3_insn (stack_pointer_rtx,
> - stack_pointer_rtx, GEN_INT (-saved_size));
> + adjust_sp_rtx =
> + gen_rtx_SET (stack_pointer_rtx,
> + gen_rtx_PLUS (GET_MODE(stack_pointer_rtx), stack_pointer_rtx, GEN_INT (-saved_size)));
> dwarf = alloc_reg_note (REG_CFA_ADJUST_CFA, adjust_sp_rtx,
> dwarf);
> return dwarf;
> @@ -5176,8 +5177,9 @@ riscv_adjust_libcall_cfi_epilogue ()
> int saved_size = cfun->machine->frame.save_libcall_adjustment;
>
> /* Debug info for adjust sp. */
> - adjust_sp_rtx = gen_add3_insn (stack_pointer_rtx,
> - stack_pointer_rtx, GEN_INT (saved_size));
> + adjust_sp_rtx =
> + gen_rtx_SET (stack_pointer_rtx,
> + gen_rtx_PLUS (GET_MODE(stack_pointer_rtx), stack_pointer_rtx, GEN_INT (saved_size)));
> dwarf = alloc_reg_note (REG_CFA_ADJUST_CFA, adjust_sp_rtx,
> dwarf);
>
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 2+ messages in thread
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2023-02-03 9:42 [PATCH v1] RISC-V: Change the generation mode of ADJUST_SP_RTX from gen_insn to gen_SET Jin Ma
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