public inbox for gcc-patches@gcc.gnu.org
 help / color / mirror / Atom feed
* [PATCH] RISC-V: Add vnot.v C API tests
@ 2023-02-03 23:22 juzhe.zhong
  0 siblings, 0 replies; 2+ messages in thread
From: juzhe.zhong @ 2023-02-03 23:22 UTC (permalink / raw)
  To: gcc-patches; +Cc: kito.cheng, Ju-Zhe Zhong

From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/rvv/base/vnot_v-1.c: New test.
        * gcc.target/riscv/rvv/base/vnot_v-2.c: New test.
        * gcc.target/riscv/rvv/base/vnot_v-3.c: New test.
        * gcc.target/riscv/rvv/base/vnot_v_m-1.c: New test.
        * gcc.target/riscv/rvv/base/vnot_v_m-2.c: New test.
        * gcc.target/riscv/rvv/base/vnot_v_m-3.c: New test.
        * gcc.target/riscv/rvv/base/vnot_v_mu-1.c: New test.
        * gcc.target/riscv/rvv/base/vnot_v_mu-2.c: New test.
        * gcc.target/riscv/rvv/base/vnot_v_mu-3.c: New test.
        * gcc.target/riscv/rvv/base/vnot_v_tu-1.c: New test.
        * gcc.target/riscv/rvv/base/vnot_v_tu-2.c: New test.
        * gcc.target/riscv/rvv/base/vnot_v_tu-3.c: New test.
        * gcc.target/riscv/rvv/base/vnot_v_tum-1.c: New test.
        * gcc.target/riscv/rvv/base/vnot_v_tum-2.c: New test.
        * gcc.target/riscv/rvv/base/vnot_v_tum-3.c: New test.
        * gcc.target/riscv/rvv/base/vnot_v_tumu-1.c: New test.
        * gcc.target/riscv/rvv/base/vnot_v_tumu-2.c: New test.
        * gcc.target/riscv/rvv/base/vnot_v_tumu-3.c: New test.

---
 .../gcc.target/riscv/rvv/base/vnot_v-1.c      | 160 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vnot_v-2.c      | 160 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vnot_v-3.c      | 160 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vnot_v_m-1.c    | 160 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vnot_v_m-2.c    | 160 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vnot_v_m-3.c    | 160 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vnot_v_mu-1.c   | 160 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vnot_v_mu-2.c   | 160 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vnot_v_mu-3.c   | 160 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vnot_v_tu-1.c   | 160 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vnot_v_tu-2.c   | 160 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vnot_v_tu-3.c   | 160 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vnot_v_tum-1.c  | 160 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vnot_v_tum-2.c  | 160 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vnot_v_tum-3.c  | 160 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vnot_v_tumu-1.c | 160 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vnot_v_tumu-2.c | 160 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vnot_v_tumu-3.c | 160 ++++++++++++++++++
 18 files changed, 2880 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_m-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_m-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_m-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_mu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_mu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_mu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_tu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_tu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_tu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_tum-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_tum-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_tum-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_tumu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_tumu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_tumu-3.c

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v-1.c
new file mode 100644
index 00000000000..82bd70e5fda
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v-1.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnot_v_i8mf8(vint8mf8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8mf8(op1,vl);
+}
+
+
+vint8mf4_t test___riscv_vnot_v_i8mf4(vint8mf4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8mf4(op1,vl);
+}
+
+
+vint8mf2_t test___riscv_vnot_v_i8mf2(vint8mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8mf2(op1,vl);
+}
+
+
+vint8m1_t test___riscv_vnot_v_i8m1(vint8m1_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8m1(op1,vl);
+}
+
+
+vint8m2_t test___riscv_vnot_v_i8m2(vint8m2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8m2(op1,vl);
+}
+
+
+vint8m4_t test___riscv_vnot_v_i8m4(vint8m4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8m4(op1,vl);
+}
+
+
+vint8m8_t test___riscv_vnot_v_i8m8(vint8m8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8m8(op1,vl);
+}
+
+
+vint16mf4_t test___riscv_vnot_v_i16mf4(vint16mf4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16mf4(op1,vl);
+}
+
+
+vint16mf2_t test___riscv_vnot_v_i16mf2(vint16mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16mf2(op1,vl);
+}
+
+
+vint16m1_t test___riscv_vnot_v_i16m1(vint16m1_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16m1(op1,vl);
+}
+
+
+vint16m2_t test___riscv_vnot_v_i16m2(vint16m2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16m2(op1,vl);
+}
+
+
+vint16m4_t test___riscv_vnot_v_i16m4(vint16m4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16m4(op1,vl);
+}
+
+
+vint16m8_t test___riscv_vnot_v_i16m8(vint16m8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16m8(op1,vl);
+}
+
+
+vint32mf2_t test___riscv_vnot_v_i32mf2(vint32mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32mf2(op1,vl);
+}
+
+
+vint32m1_t test___riscv_vnot_v_i32m1(vint32m1_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32m1(op1,vl);
+}
+
+
+vint32m2_t test___riscv_vnot_v_i32m2(vint32m2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32m2(op1,vl);
+}
+
+
+vint32m4_t test___riscv_vnot_v_i32m4(vint32m4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32m4(op1,vl);
+}
+
+
+vint32m8_t test___riscv_vnot_v_i32m8(vint32m8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32m8(op1,vl);
+}
+
+
+vint64m1_t test___riscv_vnot_v_i64m1(vint64m1_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i64m1(op1,vl);
+}
+
+
+vint64m2_t test___riscv_vnot_v_i64m2(vint64m2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i64m2(op1,vl);
+}
+
+
+vint64m4_t test___riscv_vnot_v_i64m4(vint64m4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i64m4(op1,vl);
+}
+
+
+vint64m8_t test___riscv_vnot_v_i64m8(vint64m8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i64m8(op1,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v-2.c
new file mode 100644
index 00000000000..cc6aea7dcfc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v-2.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnot_v_i8mf8(vint8mf8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8mf8(op1,31);
+}
+
+
+vint8mf4_t test___riscv_vnot_v_i8mf4(vint8mf4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8mf4(op1,31);
+}
+
+
+vint8mf2_t test___riscv_vnot_v_i8mf2(vint8mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8mf2(op1,31);
+}
+
+
+vint8m1_t test___riscv_vnot_v_i8m1(vint8m1_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8m1(op1,31);
+}
+
+
+vint8m2_t test___riscv_vnot_v_i8m2(vint8m2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8m2(op1,31);
+}
+
+
+vint8m4_t test___riscv_vnot_v_i8m4(vint8m4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8m4(op1,31);
+}
+
+
+vint8m8_t test___riscv_vnot_v_i8m8(vint8m8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8m8(op1,31);
+}
+
+
+vint16mf4_t test___riscv_vnot_v_i16mf4(vint16mf4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16mf4(op1,31);
+}
+
+
+vint16mf2_t test___riscv_vnot_v_i16mf2(vint16mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16mf2(op1,31);
+}
+
+
+vint16m1_t test___riscv_vnot_v_i16m1(vint16m1_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16m1(op1,31);
+}
+
+
+vint16m2_t test___riscv_vnot_v_i16m2(vint16m2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16m2(op1,31);
+}
+
+
+vint16m4_t test___riscv_vnot_v_i16m4(vint16m4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16m4(op1,31);
+}
+
+
+vint16m8_t test___riscv_vnot_v_i16m8(vint16m8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16m8(op1,31);
+}
+
+
+vint32mf2_t test___riscv_vnot_v_i32mf2(vint32mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32mf2(op1,31);
+}
+
+
+vint32m1_t test___riscv_vnot_v_i32m1(vint32m1_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32m1(op1,31);
+}
+
+
+vint32m2_t test___riscv_vnot_v_i32m2(vint32m2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32m2(op1,31);
+}
+
+
+vint32m4_t test___riscv_vnot_v_i32m4(vint32m4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32m4(op1,31);
+}
+
+
+vint32m8_t test___riscv_vnot_v_i32m8(vint32m8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32m8(op1,31);
+}
+
+
+vint64m1_t test___riscv_vnot_v_i64m1(vint64m1_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i64m1(op1,31);
+}
+
+
+vint64m2_t test___riscv_vnot_v_i64m2(vint64m2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i64m2(op1,31);
+}
+
+
+vint64m4_t test___riscv_vnot_v_i64m4(vint64m4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i64m4(op1,31);
+}
+
+
+vint64m8_t test___riscv_vnot_v_i64m8(vint64m8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i64m8(op1,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v-3.c
new file mode 100644
index 00000000000..e18ff42a03a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v-3.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnot_v_i8mf8(vint8mf8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8mf8(op1,32);
+}
+
+
+vint8mf4_t test___riscv_vnot_v_i8mf4(vint8mf4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8mf4(op1,32);
+}
+
+
+vint8mf2_t test___riscv_vnot_v_i8mf2(vint8mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8mf2(op1,32);
+}
+
+
+vint8m1_t test___riscv_vnot_v_i8m1(vint8m1_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8m1(op1,32);
+}
+
+
+vint8m2_t test___riscv_vnot_v_i8m2(vint8m2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8m2(op1,32);
+}
+
+
+vint8m4_t test___riscv_vnot_v_i8m4(vint8m4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8m4(op1,32);
+}
+
+
+vint8m8_t test___riscv_vnot_v_i8m8(vint8m8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8m8(op1,32);
+}
+
+
+vint16mf4_t test___riscv_vnot_v_i16mf4(vint16mf4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16mf4(op1,32);
+}
+
+
+vint16mf2_t test___riscv_vnot_v_i16mf2(vint16mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16mf2(op1,32);
+}
+
+
+vint16m1_t test___riscv_vnot_v_i16m1(vint16m1_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16m1(op1,32);
+}
+
+
+vint16m2_t test___riscv_vnot_v_i16m2(vint16m2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16m2(op1,32);
+}
+
+
+vint16m4_t test___riscv_vnot_v_i16m4(vint16m4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16m4(op1,32);
+}
+
+
+vint16m8_t test___riscv_vnot_v_i16m8(vint16m8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16m8(op1,32);
+}
+
+
+vint32mf2_t test___riscv_vnot_v_i32mf2(vint32mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32mf2(op1,32);
+}
+
+
+vint32m1_t test___riscv_vnot_v_i32m1(vint32m1_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32m1(op1,32);
+}
+
+
+vint32m2_t test___riscv_vnot_v_i32m2(vint32m2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32m2(op1,32);
+}
+
+
+vint32m4_t test___riscv_vnot_v_i32m4(vint32m4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32m4(op1,32);
+}
+
+
+vint32m8_t test___riscv_vnot_v_i32m8(vint32m8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32m8(op1,32);
+}
+
+
+vint64m1_t test___riscv_vnot_v_i64m1(vint64m1_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i64m1(op1,32);
+}
+
+
+vint64m2_t test___riscv_vnot_v_i64m2(vint64m2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i64m2(op1,32);
+}
+
+
+vint64m4_t test___riscv_vnot_v_i64m4(vint64m4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i64m4(op1,32);
+}
+
+
+vint64m8_t test___riscv_vnot_v_i64m8(vint64m8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i64m8(op1,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_m-1.c
new file mode 100644
index 00000000000..87e187aaaf3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_m-1.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnot_v_i8mf8_m(vbool64_t mask,vint8mf8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8mf8_m(mask,op1,vl);
+}
+
+
+vint8mf4_t test___riscv_vnot_v_i8mf4_m(vbool32_t mask,vint8mf4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8mf4_m(mask,op1,vl);
+}
+
+
+vint8mf2_t test___riscv_vnot_v_i8mf2_m(vbool16_t mask,vint8mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8mf2_m(mask,op1,vl);
+}
+
+
+vint8m1_t test___riscv_vnot_v_i8m1_m(vbool8_t mask,vint8m1_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8m1_m(mask,op1,vl);
+}
+
+
+vint8m2_t test___riscv_vnot_v_i8m2_m(vbool4_t mask,vint8m2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8m2_m(mask,op1,vl);
+}
+
+
+vint8m4_t test___riscv_vnot_v_i8m4_m(vbool2_t mask,vint8m4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8m4_m(mask,op1,vl);
+}
+
+
+vint8m8_t test___riscv_vnot_v_i8m8_m(vbool1_t mask,vint8m8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8m8_m(mask,op1,vl);
+}
+
+
+vint16mf4_t test___riscv_vnot_v_i16mf4_m(vbool64_t mask,vint16mf4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16mf4_m(mask,op1,vl);
+}
+
+
+vint16mf2_t test___riscv_vnot_v_i16mf2_m(vbool32_t mask,vint16mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16mf2_m(mask,op1,vl);
+}
+
+
+vint16m1_t test___riscv_vnot_v_i16m1_m(vbool16_t mask,vint16m1_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16m1_m(mask,op1,vl);
+}
+
+
+vint16m2_t test___riscv_vnot_v_i16m2_m(vbool8_t mask,vint16m2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16m2_m(mask,op1,vl);
+}
+
+
+vint16m4_t test___riscv_vnot_v_i16m4_m(vbool4_t mask,vint16m4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16m4_m(mask,op1,vl);
+}
+
+
+vint16m8_t test___riscv_vnot_v_i16m8_m(vbool2_t mask,vint16m8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16m8_m(mask,op1,vl);
+}
+
+
+vint32mf2_t test___riscv_vnot_v_i32mf2_m(vbool64_t mask,vint32mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32mf2_m(mask,op1,vl);
+}
+
+
+vint32m1_t test___riscv_vnot_v_i32m1_m(vbool32_t mask,vint32m1_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32m1_m(mask,op1,vl);
+}
+
+
+vint32m2_t test___riscv_vnot_v_i32m2_m(vbool16_t mask,vint32m2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32m2_m(mask,op1,vl);
+}
+
+
+vint32m4_t test___riscv_vnot_v_i32m4_m(vbool8_t mask,vint32m4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32m4_m(mask,op1,vl);
+}
+
+
+vint32m8_t test___riscv_vnot_v_i32m8_m(vbool4_t mask,vint32m8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32m8_m(mask,op1,vl);
+}
+
+
+vint64m1_t test___riscv_vnot_v_i64m1_m(vbool64_t mask,vint64m1_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i64m1_m(mask,op1,vl);
+}
+
+
+vint64m2_t test___riscv_vnot_v_i64m2_m(vbool32_t mask,vint64m2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i64m2_m(mask,op1,vl);
+}
+
+
+vint64m4_t test___riscv_vnot_v_i64m4_m(vbool16_t mask,vint64m4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i64m4_m(mask,op1,vl);
+}
+
+
+vint64m8_t test___riscv_vnot_v_i64m8_m(vbool8_t mask,vint64m8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i64m8_m(mask,op1,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_m-2.c
new file mode 100644
index 00000000000..52d1a886a47
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_m-2.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnot_v_i8mf8_m(vbool64_t mask,vint8mf8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8mf8_m(mask,op1,31);
+}
+
+
+vint8mf4_t test___riscv_vnot_v_i8mf4_m(vbool32_t mask,vint8mf4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8mf4_m(mask,op1,31);
+}
+
+
+vint8mf2_t test___riscv_vnot_v_i8mf2_m(vbool16_t mask,vint8mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8mf2_m(mask,op1,31);
+}
+
+
+vint8m1_t test___riscv_vnot_v_i8m1_m(vbool8_t mask,vint8m1_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8m1_m(mask,op1,31);
+}
+
+
+vint8m2_t test___riscv_vnot_v_i8m2_m(vbool4_t mask,vint8m2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8m2_m(mask,op1,31);
+}
+
+
+vint8m4_t test___riscv_vnot_v_i8m4_m(vbool2_t mask,vint8m4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8m4_m(mask,op1,31);
+}
+
+
+vint8m8_t test___riscv_vnot_v_i8m8_m(vbool1_t mask,vint8m8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8m8_m(mask,op1,31);
+}
+
+
+vint16mf4_t test___riscv_vnot_v_i16mf4_m(vbool64_t mask,vint16mf4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16mf4_m(mask,op1,31);
+}
+
+
+vint16mf2_t test___riscv_vnot_v_i16mf2_m(vbool32_t mask,vint16mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16mf2_m(mask,op1,31);
+}
+
+
+vint16m1_t test___riscv_vnot_v_i16m1_m(vbool16_t mask,vint16m1_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16m1_m(mask,op1,31);
+}
+
+
+vint16m2_t test___riscv_vnot_v_i16m2_m(vbool8_t mask,vint16m2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16m2_m(mask,op1,31);
+}
+
+
+vint16m4_t test___riscv_vnot_v_i16m4_m(vbool4_t mask,vint16m4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16m4_m(mask,op1,31);
+}
+
+
+vint16m8_t test___riscv_vnot_v_i16m8_m(vbool2_t mask,vint16m8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16m8_m(mask,op1,31);
+}
+
+
+vint32mf2_t test___riscv_vnot_v_i32mf2_m(vbool64_t mask,vint32mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32mf2_m(mask,op1,31);
+}
+
+
+vint32m1_t test___riscv_vnot_v_i32m1_m(vbool32_t mask,vint32m1_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32m1_m(mask,op1,31);
+}
+
+
+vint32m2_t test___riscv_vnot_v_i32m2_m(vbool16_t mask,vint32m2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32m2_m(mask,op1,31);
+}
+
+
+vint32m4_t test___riscv_vnot_v_i32m4_m(vbool8_t mask,vint32m4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32m4_m(mask,op1,31);
+}
+
+
+vint32m8_t test___riscv_vnot_v_i32m8_m(vbool4_t mask,vint32m8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32m8_m(mask,op1,31);
+}
+
+
+vint64m1_t test___riscv_vnot_v_i64m1_m(vbool64_t mask,vint64m1_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i64m1_m(mask,op1,31);
+}
+
+
+vint64m2_t test___riscv_vnot_v_i64m2_m(vbool32_t mask,vint64m2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i64m2_m(mask,op1,31);
+}
+
+
+vint64m4_t test___riscv_vnot_v_i64m4_m(vbool16_t mask,vint64m4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i64m4_m(mask,op1,31);
+}
+
+
+vint64m8_t test___riscv_vnot_v_i64m8_m(vbool8_t mask,vint64m8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i64m8_m(mask,op1,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_m-3.c
new file mode 100644
index 00000000000..53098d58014
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_m-3.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnot_v_i8mf8_m(vbool64_t mask,vint8mf8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8mf8_m(mask,op1,32);
+}
+
+
+vint8mf4_t test___riscv_vnot_v_i8mf4_m(vbool32_t mask,vint8mf4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8mf4_m(mask,op1,32);
+}
+
+
+vint8mf2_t test___riscv_vnot_v_i8mf2_m(vbool16_t mask,vint8mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8mf2_m(mask,op1,32);
+}
+
+
+vint8m1_t test___riscv_vnot_v_i8m1_m(vbool8_t mask,vint8m1_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8m1_m(mask,op1,32);
+}
+
+
+vint8m2_t test___riscv_vnot_v_i8m2_m(vbool4_t mask,vint8m2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8m2_m(mask,op1,32);
+}
+
+
+vint8m4_t test___riscv_vnot_v_i8m4_m(vbool2_t mask,vint8m4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8m4_m(mask,op1,32);
+}
+
+
+vint8m8_t test___riscv_vnot_v_i8m8_m(vbool1_t mask,vint8m8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8m8_m(mask,op1,32);
+}
+
+
+vint16mf4_t test___riscv_vnot_v_i16mf4_m(vbool64_t mask,vint16mf4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16mf4_m(mask,op1,32);
+}
+
+
+vint16mf2_t test___riscv_vnot_v_i16mf2_m(vbool32_t mask,vint16mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16mf2_m(mask,op1,32);
+}
+
+
+vint16m1_t test___riscv_vnot_v_i16m1_m(vbool16_t mask,vint16m1_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16m1_m(mask,op1,32);
+}
+
+
+vint16m2_t test___riscv_vnot_v_i16m2_m(vbool8_t mask,vint16m2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16m2_m(mask,op1,32);
+}
+
+
+vint16m4_t test___riscv_vnot_v_i16m4_m(vbool4_t mask,vint16m4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16m4_m(mask,op1,32);
+}
+
+
+vint16m8_t test___riscv_vnot_v_i16m8_m(vbool2_t mask,vint16m8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16m8_m(mask,op1,32);
+}
+
+
+vint32mf2_t test___riscv_vnot_v_i32mf2_m(vbool64_t mask,vint32mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32mf2_m(mask,op1,32);
+}
+
+
+vint32m1_t test___riscv_vnot_v_i32m1_m(vbool32_t mask,vint32m1_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32m1_m(mask,op1,32);
+}
+
+
+vint32m2_t test___riscv_vnot_v_i32m2_m(vbool16_t mask,vint32m2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32m2_m(mask,op1,32);
+}
+
+
+vint32m4_t test___riscv_vnot_v_i32m4_m(vbool8_t mask,vint32m4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32m4_m(mask,op1,32);
+}
+
+
+vint32m8_t test___riscv_vnot_v_i32m8_m(vbool4_t mask,vint32m8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32m8_m(mask,op1,32);
+}
+
+
+vint64m1_t test___riscv_vnot_v_i64m1_m(vbool64_t mask,vint64m1_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i64m1_m(mask,op1,32);
+}
+
+
+vint64m2_t test___riscv_vnot_v_i64m2_m(vbool32_t mask,vint64m2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i64m2_m(mask,op1,32);
+}
+
+
+vint64m4_t test___riscv_vnot_v_i64m4_m(vbool16_t mask,vint64m4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i64m4_m(mask,op1,32);
+}
+
+
+vint64m8_t test___riscv_vnot_v_i64m8_m(vbool8_t mask,vint64m8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i64m8_m(mask,op1,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_mu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_mu-1.c
new file mode 100644
index 00000000000..6ca088f7e7a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_mu-1.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnot_v_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8mf8_mu(mask,merge,op1,vl);
+}
+
+
+vint8mf4_t test___riscv_vnot_v_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8mf4_mu(mask,merge,op1,vl);
+}
+
+
+vint8mf2_t test___riscv_vnot_v_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8mf2_mu(mask,merge,op1,vl);
+}
+
+
+vint8m1_t test___riscv_vnot_v_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8m1_mu(mask,merge,op1,vl);
+}
+
+
+vint8m2_t test___riscv_vnot_v_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8m2_mu(mask,merge,op1,vl);
+}
+
+
+vint8m4_t test___riscv_vnot_v_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8m4_mu(mask,merge,op1,vl);
+}
+
+
+vint8m8_t test___riscv_vnot_v_i8m8_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8m8_mu(mask,merge,op1,vl);
+}
+
+
+vint16mf4_t test___riscv_vnot_v_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16mf4_mu(mask,merge,op1,vl);
+}
+
+
+vint16mf2_t test___riscv_vnot_v_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16mf2_mu(mask,merge,op1,vl);
+}
+
+
+vint16m1_t test___riscv_vnot_v_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16m1_mu(mask,merge,op1,vl);
+}
+
+
+vint16m2_t test___riscv_vnot_v_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16m2_mu(mask,merge,op1,vl);
+}
+
+
+vint16m4_t test___riscv_vnot_v_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16m4_mu(mask,merge,op1,vl);
+}
+
+
+vint16m8_t test___riscv_vnot_v_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16m8_mu(mask,merge,op1,vl);
+}
+
+
+vint32mf2_t test___riscv_vnot_v_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32mf2_mu(mask,merge,op1,vl);
+}
+
+
+vint32m1_t test___riscv_vnot_v_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32m1_mu(mask,merge,op1,vl);
+}
+
+
+vint32m2_t test___riscv_vnot_v_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32m2_mu(mask,merge,op1,vl);
+}
+
+
+vint32m4_t test___riscv_vnot_v_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32m4_mu(mask,merge,op1,vl);
+}
+
+
+vint32m8_t test___riscv_vnot_v_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32m8_mu(mask,merge,op1,vl);
+}
+
+
+vint64m1_t test___riscv_vnot_v_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i64m1_mu(mask,merge,op1,vl);
+}
+
+
+vint64m2_t test___riscv_vnot_v_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i64m2_mu(mask,merge,op1,vl);
+}
+
+
+vint64m4_t test___riscv_vnot_v_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i64m4_mu(mask,merge,op1,vl);
+}
+
+
+vint64m8_t test___riscv_vnot_v_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i64m8_mu(mask,merge,op1,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_mu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_mu-2.c
new file mode 100644
index 00000000000..bbd9e2f11f2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_mu-2.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnot_v_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8mf8_mu(mask,merge,op1,31);
+}
+
+
+vint8mf4_t test___riscv_vnot_v_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8mf4_mu(mask,merge,op1,31);
+}
+
+
+vint8mf2_t test___riscv_vnot_v_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8mf2_mu(mask,merge,op1,31);
+}
+
+
+vint8m1_t test___riscv_vnot_v_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8m1_mu(mask,merge,op1,31);
+}
+
+
+vint8m2_t test___riscv_vnot_v_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8m2_mu(mask,merge,op1,31);
+}
+
+
+vint8m4_t test___riscv_vnot_v_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8m4_mu(mask,merge,op1,31);
+}
+
+
+vint8m8_t test___riscv_vnot_v_i8m8_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8m8_mu(mask,merge,op1,31);
+}
+
+
+vint16mf4_t test___riscv_vnot_v_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16mf4_mu(mask,merge,op1,31);
+}
+
+
+vint16mf2_t test___riscv_vnot_v_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16mf2_mu(mask,merge,op1,31);
+}
+
+
+vint16m1_t test___riscv_vnot_v_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16m1_mu(mask,merge,op1,31);
+}
+
+
+vint16m2_t test___riscv_vnot_v_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16m2_mu(mask,merge,op1,31);
+}
+
+
+vint16m4_t test___riscv_vnot_v_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16m4_mu(mask,merge,op1,31);
+}
+
+
+vint16m8_t test___riscv_vnot_v_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16m8_mu(mask,merge,op1,31);
+}
+
+
+vint32mf2_t test___riscv_vnot_v_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32mf2_mu(mask,merge,op1,31);
+}
+
+
+vint32m1_t test___riscv_vnot_v_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32m1_mu(mask,merge,op1,31);
+}
+
+
+vint32m2_t test___riscv_vnot_v_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32m2_mu(mask,merge,op1,31);
+}
+
+
+vint32m4_t test___riscv_vnot_v_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32m4_mu(mask,merge,op1,31);
+}
+
+
+vint32m8_t test___riscv_vnot_v_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32m8_mu(mask,merge,op1,31);
+}
+
+
+vint64m1_t test___riscv_vnot_v_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i64m1_mu(mask,merge,op1,31);
+}
+
+
+vint64m2_t test___riscv_vnot_v_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i64m2_mu(mask,merge,op1,31);
+}
+
+
+vint64m4_t test___riscv_vnot_v_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i64m4_mu(mask,merge,op1,31);
+}
+
+
+vint64m8_t test___riscv_vnot_v_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i64m8_mu(mask,merge,op1,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_mu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_mu-3.c
new file mode 100644
index 00000000000..7325d5299cd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_mu-3.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnot_v_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8mf8_mu(mask,merge,op1,32);
+}
+
+
+vint8mf4_t test___riscv_vnot_v_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8mf4_mu(mask,merge,op1,32);
+}
+
+
+vint8mf2_t test___riscv_vnot_v_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8mf2_mu(mask,merge,op1,32);
+}
+
+
+vint8m1_t test___riscv_vnot_v_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8m1_mu(mask,merge,op1,32);
+}
+
+
+vint8m2_t test___riscv_vnot_v_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8m2_mu(mask,merge,op1,32);
+}
+
+
+vint8m4_t test___riscv_vnot_v_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8m4_mu(mask,merge,op1,32);
+}
+
+
+vint8m8_t test___riscv_vnot_v_i8m8_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8m8_mu(mask,merge,op1,32);
+}
+
+
+vint16mf4_t test___riscv_vnot_v_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16mf4_mu(mask,merge,op1,32);
+}
+
+
+vint16mf2_t test___riscv_vnot_v_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16mf2_mu(mask,merge,op1,32);
+}
+
+
+vint16m1_t test___riscv_vnot_v_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16m1_mu(mask,merge,op1,32);
+}
+
+
+vint16m2_t test___riscv_vnot_v_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16m2_mu(mask,merge,op1,32);
+}
+
+
+vint16m4_t test___riscv_vnot_v_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16m4_mu(mask,merge,op1,32);
+}
+
+
+vint16m8_t test___riscv_vnot_v_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16m8_mu(mask,merge,op1,32);
+}
+
+
+vint32mf2_t test___riscv_vnot_v_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32mf2_mu(mask,merge,op1,32);
+}
+
+
+vint32m1_t test___riscv_vnot_v_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32m1_mu(mask,merge,op1,32);
+}
+
+
+vint32m2_t test___riscv_vnot_v_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32m2_mu(mask,merge,op1,32);
+}
+
+
+vint32m4_t test___riscv_vnot_v_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32m4_mu(mask,merge,op1,32);
+}
+
+
+vint32m8_t test___riscv_vnot_v_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32m8_mu(mask,merge,op1,32);
+}
+
+
+vint64m1_t test___riscv_vnot_v_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i64m1_mu(mask,merge,op1,32);
+}
+
+
+vint64m2_t test___riscv_vnot_v_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i64m2_mu(mask,merge,op1,32);
+}
+
+
+vint64m4_t test___riscv_vnot_v_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i64m4_mu(mask,merge,op1,32);
+}
+
+
+vint64m8_t test___riscv_vnot_v_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i64m8_mu(mask,merge,op1,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_tu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_tu-1.c
new file mode 100644
index 00000000000..35e8981c3b2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_tu-1.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnot_v_i8mf8_tu(vint8mf8_t merge,vint8mf8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8mf8_tu(merge,op1,vl);
+}
+
+
+vint8mf4_t test___riscv_vnot_v_i8mf4_tu(vint8mf4_t merge,vint8mf4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8mf4_tu(merge,op1,vl);
+}
+
+
+vint8mf2_t test___riscv_vnot_v_i8mf2_tu(vint8mf2_t merge,vint8mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8mf2_tu(merge,op1,vl);
+}
+
+
+vint8m1_t test___riscv_vnot_v_i8m1_tu(vint8m1_t merge,vint8m1_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8m1_tu(merge,op1,vl);
+}
+
+
+vint8m2_t test___riscv_vnot_v_i8m2_tu(vint8m2_t merge,vint8m2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8m2_tu(merge,op1,vl);
+}
+
+
+vint8m4_t test___riscv_vnot_v_i8m4_tu(vint8m4_t merge,vint8m4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8m4_tu(merge,op1,vl);
+}
+
+
+vint8m8_t test___riscv_vnot_v_i8m8_tu(vint8m8_t merge,vint8m8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8m8_tu(merge,op1,vl);
+}
+
+
+vint16mf4_t test___riscv_vnot_v_i16mf4_tu(vint16mf4_t merge,vint16mf4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16mf4_tu(merge,op1,vl);
+}
+
+
+vint16mf2_t test___riscv_vnot_v_i16mf2_tu(vint16mf2_t merge,vint16mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16mf2_tu(merge,op1,vl);
+}
+
+
+vint16m1_t test___riscv_vnot_v_i16m1_tu(vint16m1_t merge,vint16m1_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16m1_tu(merge,op1,vl);
+}
+
+
+vint16m2_t test___riscv_vnot_v_i16m2_tu(vint16m2_t merge,vint16m2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16m2_tu(merge,op1,vl);
+}
+
+
+vint16m4_t test___riscv_vnot_v_i16m4_tu(vint16m4_t merge,vint16m4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16m4_tu(merge,op1,vl);
+}
+
+
+vint16m8_t test___riscv_vnot_v_i16m8_tu(vint16m8_t merge,vint16m8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16m8_tu(merge,op1,vl);
+}
+
+
+vint32mf2_t test___riscv_vnot_v_i32mf2_tu(vint32mf2_t merge,vint32mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32mf2_tu(merge,op1,vl);
+}
+
+
+vint32m1_t test___riscv_vnot_v_i32m1_tu(vint32m1_t merge,vint32m1_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32m1_tu(merge,op1,vl);
+}
+
+
+vint32m2_t test___riscv_vnot_v_i32m2_tu(vint32m2_t merge,vint32m2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32m2_tu(merge,op1,vl);
+}
+
+
+vint32m4_t test___riscv_vnot_v_i32m4_tu(vint32m4_t merge,vint32m4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32m4_tu(merge,op1,vl);
+}
+
+
+vint32m8_t test___riscv_vnot_v_i32m8_tu(vint32m8_t merge,vint32m8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32m8_tu(merge,op1,vl);
+}
+
+
+vint64m1_t test___riscv_vnot_v_i64m1_tu(vint64m1_t merge,vint64m1_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i64m1_tu(merge,op1,vl);
+}
+
+
+vint64m2_t test___riscv_vnot_v_i64m2_tu(vint64m2_t merge,vint64m2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i64m2_tu(merge,op1,vl);
+}
+
+
+vint64m4_t test___riscv_vnot_v_i64m4_tu(vint64m4_t merge,vint64m4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i64m4_tu(merge,op1,vl);
+}
+
+
+vint64m8_t test___riscv_vnot_v_i64m8_tu(vint64m8_t merge,vint64m8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i64m8_tu(merge,op1,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_tu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_tu-2.c
new file mode 100644
index 00000000000..7a28ef0829e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_tu-2.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnot_v_i8mf8_tu(vint8mf8_t merge,vint8mf8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8mf8_tu(merge,op1,31);
+}
+
+
+vint8mf4_t test___riscv_vnot_v_i8mf4_tu(vint8mf4_t merge,vint8mf4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8mf4_tu(merge,op1,31);
+}
+
+
+vint8mf2_t test___riscv_vnot_v_i8mf2_tu(vint8mf2_t merge,vint8mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8mf2_tu(merge,op1,31);
+}
+
+
+vint8m1_t test___riscv_vnot_v_i8m1_tu(vint8m1_t merge,vint8m1_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8m1_tu(merge,op1,31);
+}
+
+
+vint8m2_t test___riscv_vnot_v_i8m2_tu(vint8m2_t merge,vint8m2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8m2_tu(merge,op1,31);
+}
+
+
+vint8m4_t test___riscv_vnot_v_i8m4_tu(vint8m4_t merge,vint8m4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8m4_tu(merge,op1,31);
+}
+
+
+vint8m8_t test___riscv_vnot_v_i8m8_tu(vint8m8_t merge,vint8m8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8m8_tu(merge,op1,31);
+}
+
+
+vint16mf4_t test___riscv_vnot_v_i16mf4_tu(vint16mf4_t merge,vint16mf4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16mf4_tu(merge,op1,31);
+}
+
+
+vint16mf2_t test___riscv_vnot_v_i16mf2_tu(vint16mf2_t merge,vint16mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16mf2_tu(merge,op1,31);
+}
+
+
+vint16m1_t test___riscv_vnot_v_i16m1_tu(vint16m1_t merge,vint16m1_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16m1_tu(merge,op1,31);
+}
+
+
+vint16m2_t test___riscv_vnot_v_i16m2_tu(vint16m2_t merge,vint16m2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16m2_tu(merge,op1,31);
+}
+
+
+vint16m4_t test___riscv_vnot_v_i16m4_tu(vint16m4_t merge,vint16m4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16m4_tu(merge,op1,31);
+}
+
+
+vint16m8_t test___riscv_vnot_v_i16m8_tu(vint16m8_t merge,vint16m8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16m8_tu(merge,op1,31);
+}
+
+
+vint32mf2_t test___riscv_vnot_v_i32mf2_tu(vint32mf2_t merge,vint32mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32mf2_tu(merge,op1,31);
+}
+
+
+vint32m1_t test___riscv_vnot_v_i32m1_tu(vint32m1_t merge,vint32m1_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32m1_tu(merge,op1,31);
+}
+
+
+vint32m2_t test___riscv_vnot_v_i32m2_tu(vint32m2_t merge,vint32m2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32m2_tu(merge,op1,31);
+}
+
+
+vint32m4_t test___riscv_vnot_v_i32m4_tu(vint32m4_t merge,vint32m4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32m4_tu(merge,op1,31);
+}
+
+
+vint32m8_t test___riscv_vnot_v_i32m8_tu(vint32m8_t merge,vint32m8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32m8_tu(merge,op1,31);
+}
+
+
+vint64m1_t test___riscv_vnot_v_i64m1_tu(vint64m1_t merge,vint64m1_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i64m1_tu(merge,op1,31);
+}
+
+
+vint64m2_t test___riscv_vnot_v_i64m2_tu(vint64m2_t merge,vint64m2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i64m2_tu(merge,op1,31);
+}
+
+
+vint64m4_t test___riscv_vnot_v_i64m4_tu(vint64m4_t merge,vint64m4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i64m4_tu(merge,op1,31);
+}
+
+
+vint64m8_t test___riscv_vnot_v_i64m8_tu(vint64m8_t merge,vint64m8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i64m8_tu(merge,op1,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_tu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_tu-3.c
new file mode 100644
index 00000000000..204b0884ab5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_tu-3.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnot_v_i8mf8_tu(vint8mf8_t merge,vint8mf8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8mf8_tu(merge,op1,32);
+}
+
+
+vint8mf4_t test___riscv_vnot_v_i8mf4_tu(vint8mf4_t merge,vint8mf4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8mf4_tu(merge,op1,32);
+}
+
+
+vint8mf2_t test___riscv_vnot_v_i8mf2_tu(vint8mf2_t merge,vint8mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8mf2_tu(merge,op1,32);
+}
+
+
+vint8m1_t test___riscv_vnot_v_i8m1_tu(vint8m1_t merge,vint8m1_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8m1_tu(merge,op1,32);
+}
+
+
+vint8m2_t test___riscv_vnot_v_i8m2_tu(vint8m2_t merge,vint8m2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8m2_tu(merge,op1,32);
+}
+
+
+vint8m4_t test___riscv_vnot_v_i8m4_tu(vint8m4_t merge,vint8m4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8m4_tu(merge,op1,32);
+}
+
+
+vint8m8_t test___riscv_vnot_v_i8m8_tu(vint8m8_t merge,vint8m8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8m8_tu(merge,op1,32);
+}
+
+
+vint16mf4_t test___riscv_vnot_v_i16mf4_tu(vint16mf4_t merge,vint16mf4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16mf4_tu(merge,op1,32);
+}
+
+
+vint16mf2_t test___riscv_vnot_v_i16mf2_tu(vint16mf2_t merge,vint16mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16mf2_tu(merge,op1,32);
+}
+
+
+vint16m1_t test___riscv_vnot_v_i16m1_tu(vint16m1_t merge,vint16m1_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16m1_tu(merge,op1,32);
+}
+
+
+vint16m2_t test___riscv_vnot_v_i16m2_tu(vint16m2_t merge,vint16m2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16m2_tu(merge,op1,32);
+}
+
+
+vint16m4_t test___riscv_vnot_v_i16m4_tu(vint16m4_t merge,vint16m4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16m4_tu(merge,op1,32);
+}
+
+
+vint16m8_t test___riscv_vnot_v_i16m8_tu(vint16m8_t merge,vint16m8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16m8_tu(merge,op1,32);
+}
+
+
+vint32mf2_t test___riscv_vnot_v_i32mf2_tu(vint32mf2_t merge,vint32mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32mf2_tu(merge,op1,32);
+}
+
+
+vint32m1_t test___riscv_vnot_v_i32m1_tu(vint32m1_t merge,vint32m1_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32m1_tu(merge,op1,32);
+}
+
+
+vint32m2_t test___riscv_vnot_v_i32m2_tu(vint32m2_t merge,vint32m2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32m2_tu(merge,op1,32);
+}
+
+
+vint32m4_t test___riscv_vnot_v_i32m4_tu(vint32m4_t merge,vint32m4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32m4_tu(merge,op1,32);
+}
+
+
+vint32m8_t test___riscv_vnot_v_i32m8_tu(vint32m8_t merge,vint32m8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32m8_tu(merge,op1,32);
+}
+
+
+vint64m1_t test___riscv_vnot_v_i64m1_tu(vint64m1_t merge,vint64m1_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i64m1_tu(merge,op1,32);
+}
+
+
+vint64m2_t test___riscv_vnot_v_i64m2_tu(vint64m2_t merge,vint64m2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i64m2_tu(merge,op1,32);
+}
+
+
+vint64m4_t test___riscv_vnot_v_i64m4_tu(vint64m4_t merge,vint64m4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i64m4_tu(merge,op1,32);
+}
+
+
+vint64m8_t test___riscv_vnot_v_i64m8_tu(vint64m8_t merge,vint64m8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i64m8_tu(merge,op1,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_tum-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_tum-1.c
new file mode 100644
index 00000000000..8cd42b2c118
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_tum-1.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnot_v_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8mf8_tum(mask,merge,op1,vl);
+}
+
+
+vint8mf4_t test___riscv_vnot_v_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8mf4_tum(mask,merge,op1,vl);
+}
+
+
+vint8mf2_t test___riscv_vnot_v_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8mf2_tum(mask,merge,op1,vl);
+}
+
+
+vint8m1_t test___riscv_vnot_v_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8m1_tum(mask,merge,op1,vl);
+}
+
+
+vint8m2_t test___riscv_vnot_v_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8m2_tum(mask,merge,op1,vl);
+}
+
+
+vint8m4_t test___riscv_vnot_v_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8m4_tum(mask,merge,op1,vl);
+}
+
+
+vint8m8_t test___riscv_vnot_v_i8m8_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8m8_tum(mask,merge,op1,vl);
+}
+
+
+vint16mf4_t test___riscv_vnot_v_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16mf4_tum(mask,merge,op1,vl);
+}
+
+
+vint16mf2_t test___riscv_vnot_v_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16mf2_tum(mask,merge,op1,vl);
+}
+
+
+vint16m1_t test___riscv_vnot_v_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16m1_tum(mask,merge,op1,vl);
+}
+
+
+vint16m2_t test___riscv_vnot_v_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16m2_tum(mask,merge,op1,vl);
+}
+
+
+vint16m4_t test___riscv_vnot_v_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16m4_tum(mask,merge,op1,vl);
+}
+
+
+vint16m8_t test___riscv_vnot_v_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16m8_tum(mask,merge,op1,vl);
+}
+
+
+vint32mf2_t test___riscv_vnot_v_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32mf2_tum(mask,merge,op1,vl);
+}
+
+
+vint32m1_t test___riscv_vnot_v_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32m1_tum(mask,merge,op1,vl);
+}
+
+
+vint32m2_t test___riscv_vnot_v_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32m2_tum(mask,merge,op1,vl);
+}
+
+
+vint32m4_t test___riscv_vnot_v_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32m4_tum(mask,merge,op1,vl);
+}
+
+
+vint32m8_t test___riscv_vnot_v_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32m8_tum(mask,merge,op1,vl);
+}
+
+
+vint64m1_t test___riscv_vnot_v_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i64m1_tum(mask,merge,op1,vl);
+}
+
+
+vint64m2_t test___riscv_vnot_v_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i64m2_tum(mask,merge,op1,vl);
+}
+
+
+vint64m4_t test___riscv_vnot_v_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i64m4_tum(mask,merge,op1,vl);
+}
+
+
+vint64m8_t test___riscv_vnot_v_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i64m8_tum(mask,merge,op1,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_tum-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_tum-2.c
new file mode 100644
index 00000000000..2cfd9b0f075
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_tum-2.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnot_v_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8mf8_tum(mask,merge,op1,31);
+}
+
+
+vint8mf4_t test___riscv_vnot_v_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8mf4_tum(mask,merge,op1,31);
+}
+
+
+vint8mf2_t test___riscv_vnot_v_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8mf2_tum(mask,merge,op1,31);
+}
+
+
+vint8m1_t test___riscv_vnot_v_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8m1_tum(mask,merge,op1,31);
+}
+
+
+vint8m2_t test___riscv_vnot_v_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8m2_tum(mask,merge,op1,31);
+}
+
+
+vint8m4_t test___riscv_vnot_v_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8m4_tum(mask,merge,op1,31);
+}
+
+
+vint8m8_t test___riscv_vnot_v_i8m8_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8m8_tum(mask,merge,op1,31);
+}
+
+
+vint16mf4_t test___riscv_vnot_v_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16mf4_tum(mask,merge,op1,31);
+}
+
+
+vint16mf2_t test___riscv_vnot_v_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16mf2_tum(mask,merge,op1,31);
+}
+
+
+vint16m1_t test___riscv_vnot_v_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16m1_tum(mask,merge,op1,31);
+}
+
+
+vint16m2_t test___riscv_vnot_v_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16m2_tum(mask,merge,op1,31);
+}
+
+
+vint16m4_t test___riscv_vnot_v_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16m4_tum(mask,merge,op1,31);
+}
+
+
+vint16m8_t test___riscv_vnot_v_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16m8_tum(mask,merge,op1,31);
+}
+
+
+vint32mf2_t test___riscv_vnot_v_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32mf2_tum(mask,merge,op1,31);
+}
+
+
+vint32m1_t test___riscv_vnot_v_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32m1_tum(mask,merge,op1,31);
+}
+
+
+vint32m2_t test___riscv_vnot_v_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32m2_tum(mask,merge,op1,31);
+}
+
+
+vint32m4_t test___riscv_vnot_v_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32m4_tum(mask,merge,op1,31);
+}
+
+
+vint32m8_t test___riscv_vnot_v_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32m8_tum(mask,merge,op1,31);
+}
+
+
+vint64m1_t test___riscv_vnot_v_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i64m1_tum(mask,merge,op1,31);
+}
+
+
+vint64m2_t test___riscv_vnot_v_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i64m2_tum(mask,merge,op1,31);
+}
+
+
+vint64m4_t test___riscv_vnot_v_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i64m4_tum(mask,merge,op1,31);
+}
+
+
+vint64m8_t test___riscv_vnot_v_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i64m8_tum(mask,merge,op1,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_tum-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_tum-3.c
new file mode 100644
index 00000000000..a374c3932ff
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_tum-3.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnot_v_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8mf8_tum(mask,merge,op1,32);
+}
+
+
+vint8mf4_t test___riscv_vnot_v_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8mf4_tum(mask,merge,op1,32);
+}
+
+
+vint8mf2_t test___riscv_vnot_v_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8mf2_tum(mask,merge,op1,32);
+}
+
+
+vint8m1_t test___riscv_vnot_v_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8m1_tum(mask,merge,op1,32);
+}
+
+
+vint8m2_t test___riscv_vnot_v_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8m2_tum(mask,merge,op1,32);
+}
+
+
+vint8m4_t test___riscv_vnot_v_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8m4_tum(mask,merge,op1,32);
+}
+
+
+vint8m8_t test___riscv_vnot_v_i8m8_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8m8_tum(mask,merge,op1,32);
+}
+
+
+vint16mf4_t test___riscv_vnot_v_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16mf4_tum(mask,merge,op1,32);
+}
+
+
+vint16mf2_t test___riscv_vnot_v_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16mf2_tum(mask,merge,op1,32);
+}
+
+
+vint16m1_t test___riscv_vnot_v_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16m1_tum(mask,merge,op1,32);
+}
+
+
+vint16m2_t test___riscv_vnot_v_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16m2_tum(mask,merge,op1,32);
+}
+
+
+vint16m4_t test___riscv_vnot_v_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16m4_tum(mask,merge,op1,32);
+}
+
+
+vint16m8_t test___riscv_vnot_v_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16m8_tum(mask,merge,op1,32);
+}
+
+
+vint32mf2_t test___riscv_vnot_v_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32mf2_tum(mask,merge,op1,32);
+}
+
+
+vint32m1_t test___riscv_vnot_v_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32m1_tum(mask,merge,op1,32);
+}
+
+
+vint32m2_t test___riscv_vnot_v_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32m2_tum(mask,merge,op1,32);
+}
+
+
+vint32m4_t test___riscv_vnot_v_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32m4_tum(mask,merge,op1,32);
+}
+
+
+vint32m8_t test___riscv_vnot_v_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32m8_tum(mask,merge,op1,32);
+}
+
+
+vint64m1_t test___riscv_vnot_v_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i64m1_tum(mask,merge,op1,32);
+}
+
+
+vint64m2_t test___riscv_vnot_v_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i64m2_tum(mask,merge,op1,32);
+}
+
+
+vint64m4_t test___riscv_vnot_v_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i64m4_tum(mask,merge,op1,32);
+}
+
+
+vint64m8_t test___riscv_vnot_v_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i64m8_tum(mask,merge,op1,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_tumu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_tumu-1.c
new file mode 100644
index 00000000000..bd118dd9744
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_tumu-1.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnot_v_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8mf8_tumu(mask,merge,op1,vl);
+}
+
+
+vint8mf4_t test___riscv_vnot_v_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8mf4_tumu(mask,merge,op1,vl);
+}
+
+
+vint8mf2_t test___riscv_vnot_v_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8mf2_tumu(mask,merge,op1,vl);
+}
+
+
+vint8m1_t test___riscv_vnot_v_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8m1_tumu(mask,merge,op1,vl);
+}
+
+
+vint8m2_t test___riscv_vnot_v_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8m2_tumu(mask,merge,op1,vl);
+}
+
+
+vint8m4_t test___riscv_vnot_v_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8m4_tumu(mask,merge,op1,vl);
+}
+
+
+vint8m8_t test___riscv_vnot_v_i8m8_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8m8_tumu(mask,merge,op1,vl);
+}
+
+
+vint16mf4_t test___riscv_vnot_v_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16mf4_tumu(mask,merge,op1,vl);
+}
+
+
+vint16mf2_t test___riscv_vnot_v_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16mf2_tumu(mask,merge,op1,vl);
+}
+
+
+vint16m1_t test___riscv_vnot_v_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16m1_tumu(mask,merge,op1,vl);
+}
+
+
+vint16m2_t test___riscv_vnot_v_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16m2_tumu(mask,merge,op1,vl);
+}
+
+
+vint16m4_t test___riscv_vnot_v_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16m4_tumu(mask,merge,op1,vl);
+}
+
+
+vint16m8_t test___riscv_vnot_v_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16m8_tumu(mask,merge,op1,vl);
+}
+
+
+vint32mf2_t test___riscv_vnot_v_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32mf2_tumu(mask,merge,op1,vl);
+}
+
+
+vint32m1_t test___riscv_vnot_v_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32m1_tumu(mask,merge,op1,vl);
+}
+
+
+vint32m2_t test___riscv_vnot_v_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32m2_tumu(mask,merge,op1,vl);
+}
+
+
+vint32m4_t test___riscv_vnot_v_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32m4_tumu(mask,merge,op1,vl);
+}
+
+
+vint32m8_t test___riscv_vnot_v_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32m8_tumu(mask,merge,op1,vl);
+}
+
+
+vint64m1_t test___riscv_vnot_v_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i64m1_tumu(mask,merge,op1,vl);
+}
+
+
+vint64m2_t test___riscv_vnot_v_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i64m2_tumu(mask,merge,op1,vl);
+}
+
+
+vint64m4_t test___riscv_vnot_v_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i64m4_tumu(mask,merge,op1,vl);
+}
+
+
+vint64m8_t test___riscv_vnot_v_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i64m8_tumu(mask,merge,op1,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_tumu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_tumu-2.c
new file mode 100644
index 00000000000..a18406a9c88
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_tumu-2.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnot_v_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8mf8_tumu(mask,merge,op1,31);
+}
+
+
+vint8mf4_t test___riscv_vnot_v_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8mf4_tumu(mask,merge,op1,31);
+}
+
+
+vint8mf2_t test___riscv_vnot_v_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8mf2_tumu(mask,merge,op1,31);
+}
+
+
+vint8m1_t test___riscv_vnot_v_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8m1_tumu(mask,merge,op1,31);
+}
+
+
+vint8m2_t test___riscv_vnot_v_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8m2_tumu(mask,merge,op1,31);
+}
+
+
+vint8m4_t test___riscv_vnot_v_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8m4_tumu(mask,merge,op1,31);
+}
+
+
+vint8m8_t test___riscv_vnot_v_i8m8_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8m8_tumu(mask,merge,op1,31);
+}
+
+
+vint16mf4_t test___riscv_vnot_v_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16mf4_tumu(mask,merge,op1,31);
+}
+
+
+vint16mf2_t test___riscv_vnot_v_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16mf2_tumu(mask,merge,op1,31);
+}
+
+
+vint16m1_t test___riscv_vnot_v_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16m1_tumu(mask,merge,op1,31);
+}
+
+
+vint16m2_t test___riscv_vnot_v_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16m2_tumu(mask,merge,op1,31);
+}
+
+
+vint16m4_t test___riscv_vnot_v_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16m4_tumu(mask,merge,op1,31);
+}
+
+
+vint16m8_t test___riscv_vnot_v_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16m8_tumu(mask,merge,op1,31);
+}
+
+
+vint32mf2_t test___riscv_vnot_v_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32mf2_tumu(mask,merge,op1,31);
+}
+
+
+vint32m1_t test___riscv_vnot_v_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32m1_tumu(mask,merge,op1,31);
+}
+
+
+vint32m2_t test___riscv_vnot_v_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32m2_tumu(mask,merge,op1,31);
+}
+
+
+vint32m4_t test___riscv_vnot_v_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32m4_tumu(mask,merge,op1,31);
+}
+
+
+vint32m8_t test___riscv_vnot_v_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32m8_tumu(mask,merge,op1,31);
+}
+
+
+vint64m1_t test___riscv_vnot_v_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i64m1_tumu(mask,merge,op1,31);
+}
+
+
+vint64m2_t test___riscv_vnot_v_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i64m2_tumu(mask,merge,op1,31);
+}
+
+
+vint64m4_t test___riscv_vnot_v_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i64m4_tumu(mask,merge,op1,31);
+}
+
+
+vint64m8_t test___riscv_vnot_v_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i64m8_tumu(mask,merge,op1,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_tumu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_tumu-3.c
new file mode 100644
index 00000000000..7418913af0a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vnot_v_tumu-3.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnot_v_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8mf8_tumu(mask,merge,op1,32);
+}
+
+
+vint8mf4_t test___riscv_vnot_v_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8mf4_tumu(mask,merge,op1,32);
+}
+
+
+vint8mf2_t test___riscv_vnot_v_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8mf2_tumu(mask,merge,op1,32);
+}
+
+
+vint8m1_t test___riscv_vnot_v_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8m1_tumu(mask,merge,op1,32);
+}
+
+
+vint8m2_t test___riscv_vnot_v_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8m2_tumu(mask,merge,op1,32);
+}
+
+
+vint8m4_t test___riscv_vnot_v_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8m4_tumu(mask,merge,op1,32);
+}
+
+
+vint8m8_t test___riscv_vnot_v_i8m8_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i8m8_tumu(mask,merge,op1,32);
+}
+
+
+vint16mf4_t test___riscv_vnot_v_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16mf4_tumu(mask,merge,op1,32);
+}
+
+
+vint16mf2_t test___riscv_vnot_v_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16mf2_tumu(mask,merge,op1,32);
+}
+
+
+vint16m1_t test___riscv_vnot_v_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16m1_tumu(mask,merge,op1,32);
+}
+
+
+vint16m2_t test___riscv_vnot_v_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16m2_tumu(mask,merge,op1,32);
+}
+
+
+vint16m4_t test___riscv_vnot_v_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16m4_tumu(mask,merge,op1,32);
+}
+
+
+vint16m8_t test___riscv_vnot_v_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i16m8_tumu(mask,merge,op1,32);
+}
+
+
+vint32mf2_t test___riscv_vnot_v_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32mf2_tumu(mask,merge,op1,32);
+}
+
+
+vint32m1_t test___riscv_vnot_v_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32m1_tumu(mask,merge,op1,32);
+}
+
+
+vint32m2_t test___riscv_vnot_v_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32m2_tumu(mask,merge,op1,32);
+}
+
+
+vint32m4_t test___riscv_vnot_v_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32m4_tumu(mask,merge,op1,32);
+}
+
+
+vint32m8_t test___riscv_vnot_v_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i32m8_tumu(mask,merge,op1,32);
+}
+
+
+vint64m1_t test___riscv_vnot_v_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i64m1_tumu(mask,merge,op1,32);
+}
+
+
+vint64m2_t test___riscv_vnot_v_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i64m2_tumu(mask,merge,op1,32);
+}
+
+
+vint64m4_t test___riscv_vnot_v_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i64m4_tumu(mask,merge,op1,32);
+}
+
+
+vint64m8_t test___riscv_vnot_v_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t vl)
+{
+    return __riscv_vnot_v_i64m8_tumu(mask,merge,op1,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
-- 
2.36.1


^ permalink raw reply	[flat|nested] 2+ messages in thread

* [PATCH] RISC-V: Add vnot.v C++ API tests
@ 2023-02-03 23:26 juzhe.zhong
  0 siblings, 0 replies; 2+ messages in thread
From: juzhe.zhong @ 2023-02-03 23:26 UTC (permalink / raw)
  To: gcc-patches; +Cc: kito.cheng, Ju-Zhe Zhong

From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>

gcc/testsuite/ChangeLog:

        * g++.target/riscv/rvv/base/vnot_v-1.C: New test.
        * g++.target/riscv/rvv/base/vnot_v-2.C: New test.
        * g++.target/riscv/rvv/base/vnot_v-3.C: New test.
        * g++.target/riscv/rvv/base/vnot_v_mu-1.C: New test.
        * g++.target/riscv/rvv/base/vnot_v_mu-2.C: New test.
        * g++.target/riscv/rvv/base/vnot_v_mu-3.C: New test.
        * g++.target/riscv/rvv/base/vnot_v_tu-1.C: New test.
        * g++.target/riscv/rvv/base/vnot_v_tu-2.C: New test.
        * g++.target/riscv/rvv/base/vnot_v_tu-3.C: New test.
        * g++.target/riscv/rvv/base/vnot_v_tum-1.C: New test.
        * g++.target/riscv/rvv/base/vnot_v_tum-2.C: New test.
        * g++.target/riscv/rvv/base/vnot_v_tum-3.C: New test.
        * g++.target/riscv/rvv/base/vnot_v_tumu-1.C: New test.
        * g++.target/riscv/rvv/base/vnot_v_tumu-2.C: New test.
        * g++.target/riscv/rvv/base/vnot_v_tumu-3.C: New test.

---
 .../g++.target/riscv/rvv/base/vnot_v-1.C      | 314 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vnot_v-2.C      | 314 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vnot_v-3.C      | 314 ++++++++++++++++++
 .../g++.target/riscv/rvv/base/vnot_v_mu-1.C   | 160 +++++++++
 .../g++.target/riscv/rvv/base/vnot_v_mu-2.C   | 160 +++++++++
 .../g++.target/riscv/rvv/base/vnot_v_mu-3.C   | 160 +++++++++
 .../g++.target/riscv/rvv/base/vnot_v_tu-1.C   | 160 +++++++++
 .../g++.target/riscv/rvv/base/vnot_v_tu-2.C   | 160 +++++++++
 .../g++.target/riscv/rvv/base/vnot_v_tu-3.C   | 160 +++++++++
 .../g++.target/riscv/rvv/base/vnot_v_tum-1.C  | 160 +++++++++
 .../g++.target/riscv/rvv/base/vnot_v_tum-2.C  | 160 +++++++++
 .../g++.target/riscv/rvv/base/vnot_v_tum-3.C  | 160 +++++++++
 .../g++.target/riscv/rvv/base/vnot_v_tumu-1.C | 160 +++++++++
 .../g++.target/riscv/rvv/base/vnot_v_tumu-2.C | 160 +++++++++
 .../g++.target/riscv/rvv/base/vnot_v_tumu-3.C | 160 +++++++++
 15 files changed, 2862 insertions(+)
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnot_v-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnot_v-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnot_v-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_mu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_mu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_mu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tu-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tum-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tum-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tum-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tumu-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tumu-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tumu-3.C

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v-1.C
new file mode 100644
index 00000000000..23e6f92c8c9
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v-1.C
@@ -0,0 +1,314 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnot(vint8mf8_t op1,size_t vl)
+{
+    return __riscv_vnot(op1,vl);
+}
+
+
+vint8mf4_t test___riscv_vnot(vint8mf4_t op1,size_t vl)
+{
+    return __riscv_vnot(op1,vl);
+}
+
+
+vint8mf2_t test___riscv_vnot(vint8mf2_t op1,size_t vl)
+{
+    return __riscv_vnot(op1,vl);
+}
+
+
+vint8m1_t test___riscv_vnot(vint8m1_t op1,size_t vl)
+{
+    return __riscv_vnot(op1,vl);
+}
+
+
+vint8m2_t test___riscv_vnot(vint8m2_t op1,size_t vl)
+{
+    return __riscv_vnot(op1,vl);
+}
+
+
+vint8m4_t test___riscv_vnot(vint8m4_t op1,size_t vl)
+{
+    return __riscv_vnot(op1,vl);
+}
+
+
+vint8m8_t test___riscv_vnot(vint8m8_t op1,size_t vl)
+{
+    return __riscv_vnot(op1,vl);
+}
+
+
+vint16mf4_t test___riscv_vnot(vint16mf4_t op1,size_t vl)
+{
+    return __riscv_vnot(op1,vl);
+}
+
+
+vint16mf2_t test___riscv_vnot(vint16mf2_t op1,size_t vl)
+{
+    return __riscv_vnot(op1,vl);
+}
+
+
+vint16m1_t test___riscv_vnot(vint16m1_t op1,size_t vl)
+{
+    return __riscv_vnot(op1,vl);
+}
+
+
+vint16m2_t test___riscv_vnot(vint16m2_t op1,size_t vl)
+{
+    return __riscv_vnot(op1,vl);
+}
+
+
+vint16m4_t test___riscv_vnot(vint16m4_t op1,size_t vl)
+{
+    return __riscv_vnot(op1,vl);
+}
+
+
+vint16m8_t test___riscv_vnot(vint16m8_t op1,size_t vl)
+{
+    return __riscv_vnot(op1,vl);
+}
+
+
+vint32mf2_t test___riscv_vnot(vint32mf2_t op1,size_t vl)
+{
+    return __riscv_vnot(op1,vl);
+}
+
+
+vint32m1_t test___riscv_vnot(vint32m1_t op1,size_t vl)
+{
+    return __riscv_vnot(op1,vl);
+}
+
+
+vint32m2_t test___riscv_vnot(vint32m2_t op1,size_t vl)
+{
+    return __riscv_vnot(op1,vl);
+}
+
+
+vint32m4_t test___riscv_vnot(vint32m4_t op1,size_t vl)
+{
+    return __riscv_vnot(op1,vl);
+}
+
+
+vint32m8_t test___riscv_vnot(vint32m8_t op1,size_t vl)
+{
+    return __riscv_vnot(op1,vl);
+}
+
+
+vint64m1_t test___riscv_vnot(vint64m1_t op1,size_t vl)
+{
+    return __riscv_vnot(op1,vl);
+}
+
+
+vint64m2_t test___riscv_vnot(vint64m2_t op1,size_t vl)
+{
+    return __riscv_vnot(op1,vl);
+}
+
+
+vint64m4_t test___riscv_vnot(vint64m4_t op1,size_t vl)
+{
+    return __riscv_vnot(op1,vl);
+}
+
+
+vint64m8_t test___riscv_vnot(vint64m8_t op1,size_t vl)
+{
+    return __riscv_vnot(op1,vl);
+}
+
+
+vint8mf8_t test___riscv_vnot(vbool64_t mask,vint8mf8_t op1,size_t vl)
+{
+    return __riscv_vnot(mask,op1,vl);
+}
+
+
+vint8mf4_t test___riscv_vnot(vbool32_t mask,vint8mf4_t op1,size_t vl)
+{
+    return __riscv_vnot(mask,op1,vl);
+}
+
+
+vint8mf2_t test___riscv_vnot(vbool16_t mask,vint8mf2_t op1,size_t vl)
+{
+    return __riscv_vnot(mask,op1,vl);
+}
+
+
+vint8m1_t test___riscv_vnot(vbool8_t mask,vint8m1_t op1,size_t vl)
+{
+    return __riscv_vnot(mask,op1,vl);
+}
+
+
+vint8m2_t test___riscv_vnot(vbool4_t mask,vint8m2_t op1,size_t vl)
+{
+    return __riscv_vnot(mask,op1,vl);
+}
+
+
+vint8m4_t test___riscv_vnot(vbool2_t mask,vint8m4_t op1,size_t vl)
+{
+    return __riscv_vnot(mask,op1,vl);
+}
+
+
+vint8m8_t test___riscv_vnot(vbool1_t mask,vint8m8_t op1,size_t vl)
+{
+    return __riscv_vnot(mask,op1,vl);
+}
+
+
+vint16mf4_t test___riscv_vnot(vbool64_t mask,vint16mf4_t op1,size_t vl)
+{
+    return __riscv_vnot(mask,op1,vl);
+}
+
+
+vint16mf2_t test___riscv_vnot(vbool32_t mask,vint16mf2_t op1,size_t vl)
+{
+    return __riscv_vnot(mask,op1,vl);
+}
+
+
+vint16m1_t test___riscv_vnot(vbool16_t mask,vint16m1_t op1,size_t vl)
+{
+    return __riscv_vnot(mask,op1,vl);
+}
+
+
+vint16m2_t test___riscv_vnot(vbool8_t mask,vint16m2_t op1,size_t vl)
+{
+    return __riscv_vnot(mask,op1,vl);
+}
+
+
+vint16m4_t test___riscv_vnot(vbool4_t mask,vint16m4_t op1,size_t vl)
+{
+    return __riscv_vnot(mask,op1,vl);
+}
+
+
+vint16m8_t test___riscv_vnot(vbool2_t mask,vint16m8_t op1,size_t vl)
+{
+    return __riscv_vnot(mask,op1,vl);
+}
+
+
+vint32mf2_t test___riscv_vnot(vbool64_t mask,vint32mf2_t op1,size_t vl)
+{
+    return __riscv_vnot(mask,op1,vl);
+}
+
+
+vint32m1_t test___riscv_vnot(vbool32_t mask,vint32m1_t op1,size_t vl)
+{
+    return __riscv_vnot(mask,op1,vl);
+}
+
+
+vint32m2_t test___riscv_vnot(vbool16_t mask,vint32m2_t op1,size_t vl)
+{
+    return __riscv_vnot(mask,op1,vl);
+}
+
+
+vint32m4_t test___riscv_vnot(vbool8_t mask,vint32m4_t op1,size_t vl)
+{
+    return __riscv_vnot(mask,op1,vl);
+}
+
+
+vint32m8_t test___riscv_vnot(vbool4_t mask,vint32m8_t op1,size_t vl)
+{
+    return __riscv_vnot(mask,op1,vl);
+}
+
+
+vint64m1_t test___riscv_vnot(vbool64_t mask,vint64m1_t op1,size_t vl)
+{
+    return __riscv_vnot(mask,op1,vl);
+}
+
+
+vint64m2_t test___riscv_vnot(vbool32_t mask,vint64m2_t op1,size_t vl)
+{
+    return __riscv_vnot(mask,op1,vl);
+}
+
+
+vint64m4_t test___riscv_vnot(vbool16_t mask,vint64m4_t op1,size_t vl)
+{
+    return __riscv_vnot(mask,op1,vl);
+}
+
+
+vint64m8_t test___riscv_vnot(vbool8_t mask,vint64m8_t op1,size_t vl)
+{
+    return __riscv_vnot(mask,op1,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v-2.C
new file mode 100644
index 00000000000..35426a06531
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v-2.C
@@ -0,0 +1,314 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnot(vint8mf8_t op1,size_t vl)
+{
+    return __riscv_vnot(op1,31);
+}
+
+
+vint8mf4_t test___riscv_vnot(vint8mf4_t op1,size_t vl)
+{
+    return __riscv_vnot(op1,31);
+}
+
+
+vint8mf2_t test___riscv_vnot(vint8mf2_t op1,size_t vl)
+{
+    return __riscv_vnot(op1,31);
+}
+
+
+vint8m1_t test___riscv_vnot(vint8m1_t op1,size_t vl)
+{
+    return __riscv_vnot(op1,31);
+}
+
+
+vint8m2_t test___riscv_vnot(vint8m2_t op1,size_t vl)
+{
+    return __riscv_vnot(op1,31);
+}
+
+
+vint8m4_t test___riscv_vnot(vint8m4_t op1,size_t vl)
+{
+    return __riscv_vnot(op1,31);
+}
+
+
+vint8m8_t test___riscv_vnot(vint8m8_t op1,size_t vl)
+{
+    return __riscv_vnot(op1,31);
+}
+
+
+vint16mf4_t test___riscv_vnot(vint16mf4_t op1,size_t vl)
+{
+    return __riscv_vnot(op1,31);
+}
+
+
+vint16mf2_t test___riscv_vnot(vint16mf2_t op1,size_t vl)
+{
+    return __riscv_vnot(op1,31);
+}
+
+
+vint16m1_t test___riscv_vnot(vint16m1_t op1,size_t vl)
+{
+    return __riscv_vnot(op1,31);
+}
+
+
+vint16m2_t test___riscv_vnot(vint16m2_t op1,size_t vl)
+{
+    return __riscv_vnot(op1,31);
+}
+
+
+vint16m4_t test___riscv_vnot(vint16m4_t op1,size_t vl)
+{
+    return __riscv_vnot(op1,31);
+}
+
+
+vint16m8_t test___riscv_vnot(vint16m8_t op1,size_t vl)
+{
+    return __riscv_vnot(op1,31);
+}
+
+
+vint32mf2_t test___riscv_vnot(vint32mf2_t op1,size_t vl)
+{
+    return __riscv_vnot(op1,31);
+}
+
+
+vint32m1_t test___riscv_vnot(vint32m1_t op1,size_t vl)
+{
+    return __riscv_vnot(op1,31);
+}
+
+
+vint32m2_t test___riscv_vnot(vint32m2_t op1,size_t vl)
+{
+    return __riscv_vnot(op1,31);
+}
+
+
+vint32m4_t test___riscv_vnot(vint32m4_t op1,size_t vl)
+{
+    return __riscv_vnot(op1,31);
+}
+
+
+vint32m8_t test___riscv_vnot(vint32m8_t op1,size_t vl)
+{
+    return __riscv_vnot(op1,31);
+}
+
+
+vint64m1_t test___riscv_vnot(vint64m1_t op1,size_t vl)
+{
+    return __riscv_vnot(op1,31);
+}
+
+
+vint64m2_t test___riscv_vnot(vint64m2_t op1,size_t vl)
+{
+    return __riscv_vnot(op1,31);
+}
+
+
+vint64m4_t test___riscv_vnot(vint64m4_t op1,size_t vl)
+{
+    return __riscv_vnot(op1,31);
+}
+
+
+vint64m8_t test___riscv_vnot(vint64m8_t op1,size_t vl)
+{
+    return __riscv_vnot(op1,31);
+}
+
+
+vint8mf8_t test___riscv_vnot(vbool64_t mask,vint8mf8_t op1,size_t vl)
+{
+    return __riscv_vnot(mask,op1,31);
+}
+
+
+vint8mf4_t test___riscv_vnot(vbool32_t mask,vint8mf4_t op1,size_t vl)
+{
+    return __riscv_vnot(mask,op1,31);
+}
+
+
+vint8mf2_t test___riscv_vnot(vbool16_t mask,vint8mf2_t op1,size_t vl)
+{
+    return __riscv_vnot(mask,op1,31);
+}
+
+
+vint8m1_t test___riscv_vnot(vbool8_t mask,vint8m1_t op1,size_t vl)
+{
+    return __riscv_vnot(mask,op1,31);
+}
+
+
+vint8m2_t test___riscv_vnot(vbool4_t mask,vint8m2_t op1,size_t vl)
+{
+    return __riscv_vnot(mask,op1,31);
+}
+
+
+vint8m4_t test___riscv_vnot(vbool2_t mask,vint8m4_t op1,size_t vl)
+{
+    return __riscv_vnot(mask,op1,31);
+}
+
+
+vint8m8_t test___riscv_vnot(vbool1_t mask,vint8m8_t op1,size_t vl)
+{
+    return __riscv_vnot(mask,op1,31);
+}
+
+
+vint16mf4_t test___riscv_vnot(vbool64_t mask,vint16mf4_t op1,size_t vl)
+{
+    return __riscv_vnot(mask,op1,31);
+}
+
+
+vint16mf2_t test___riscv_vnot(vbool32_t mask,vint16mf2_t op1,size_t vl)
+{
+    return __riscv_vnot(mask,op1,31);
+}
+
+
+vint16m1_t test___riscv_vnot(vbool16_t mask,vint16m1_t op1,size_t vl)
+{
+    return __riscv_vnot(mask,op1,31);
+}
+
+
+vint16m2_t test___riscv_vnot(vbool8_t mask,vint16m2_t op1,size_t vl)
+{
+    return __riscv_vnot(mask,op1,31);
+}
+
+
+vint16m4_t test___riscv_vnot(vbool4_t mask,vint16m4_t op1,size_t vl)
+{
+    return __riscv_vnot(mask,op1,31);
+}
+
+
+vint16m8_t test___riscv_vnot(vbool2_t mask,vint16m8_t op1,size_t vl)
+{
+    return __riscv_vnot(mask,op1,31);
+}
+
+
+vint32mf2_t test___riscv_vnot(vbool64_t mask,vint32mf2_t op1,size_t vl)
+{
+    return __riscv_vnot(mask,op1,31);
+}
+
+
+vint32m1_t test___riscv_vnot(vbool32_t mask,vint32m1_t op1,size_t vl)
+{
+    return __riscv_vnot(mask,op1,31);
+}
+
+
+vint32m2_t test___riscv_vnot(vbool16_t mask,vint32m2_t op1,size_t vl)
+{
+    return __riscv_vnot(mask,op1,31);
+}
+
+
+vint32m4_t test___riscv_vnot(vbool8_t mask,vint32m4_t op1,size_t vl)
+{
+    return __riscv_vnot(mask,op1,31);
+}
+
+
+vint32m8_t test___riscv_vnot(vbool4_t mask,vint32m8_t op1,size_t vl)
+{
+    return __riscv_vnot(mask,op1,31);
+}
+
+
+vint64m1_t test___riscv_vnot(vbool64_t mask,vint64m1_t op1,size_t vl)
+{
+    return __riscv_vnot(mask,op1,31);
+}
+
+
+vint64m2_t test___riscv_vnot(vbool32_t mask,vint64m2_t op1,size_t vl)
+{
+    return __riscv_vnot(mask,op1,31);
+}
+
+
+vint64m4_t test___riscv_vnot(vbool16_t mask,vint64m4_t op1,size_t vl)
+{
+    return __riscv_vnot(mask,op1,31);
+}
+
+
+vint64m8_t test___riscv_vnot(vbool8_t mask,vint64m8_t op1,size_t vl)
+{
+    return __riscv_vnot(mask,op1,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v-3.C
new file mode 100644
index 00000000000..42fd5054ea0
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v-3.C
@@ -0,0 +1,314 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnot(vint8mf8_t op1,size_t vl)
+{
+    return __riscv_vnot(op1,32);
+}
+
+
+vint8mf4_t test___riscv_vnot(vint8mf4_t op1,size_t vl)
+{
+    return __riscv_vnot(op1,32);
+}
+
+
+vint8mf2_t test___riscv_vnot(vint8mf2_t op1,size_t vl)
+{
+    return __riscv_vnot(op1,32);
+}
+
+
+vint8m1_t test___riscv_vnot(vint8m1_t op1,size_t vl)
+{
+    return __riscv_vnot(op1,32);
+}
+
+
+vint8m2_t test___riscv_vnot(vint8m2_t op1,size_t vl)
+{
+    return __riscv_vnot(op1,32);
+}
+
+
+vint8m4_t test___riscv_vnot(vint8m4_t op1,size_t vl)
+{
+    return __riscv_vnot(op1,32);
+}
+
+
+vint8m8_t test___riscv_vnot(vint8m8_t op1,size_t vl)
+{
+    return __riscv_vnot(op1,32);
+}
+
+
+vint16mf4_t test___riscv_vnot(vint16mf4_t op1,size_t vl)
+{
+    return __riscv_vnot(op1,32);
+}
+
+
+vint16mf2_t test___riscv_vnot(vint16mf2_t op1,size_t vl)
+{
+    return __riscv_vnot(op1,32);
+}
+
+
+vint16m1_t test___riscv_vnot(vint16m1_t op1,size_t vl)
+{
+    return __riscv_vnot(op1,32);
+}
+
+
+vint16m2_t test___riscv_vnot(vint16m2_t op1,size_t vl)
+{
+    return __riscv_vnot(op1,32);
+}
+
+
+vint16m4_t test___riscv_vnot(vint16m4_t op1,size_t vl)
+{
+    return __riscv_vnot(op1,32);
+}
+
+
+vint16m8_t test___riscv_vnot(vint16m8_t op1,size_t vl)
+{
+    return __riscv_vnot(op1,32);
+}
+
+
+vint32mf2_t test___riscv_vnot(vint32mf2_t op1,size_t vl)
+{
+    return __riscv_vnot(op1,32);
+}
+
+
+vint32m1_t test___riscv_vnot(vint32m1_t op1,size_t vl)
+{
+    return __riscv_vnot(op1,32);
+}
+
+
+vint32m2_t test___riscv_vnot(vint32m2_t op1,size_t vl)
+{
+    return __riscv_vnot(op1,32);
+}
+
+
+vint32m4_t test___riscv_vnot(vint32m4_t op1,size_t vl)
+{
+    return __riscv_vnot(op1,32);
+}
+
+
+vint32m8_t test___riscv_vnot(vint32m8_t op1,size_t vl)
+{
+    return __riscv_vnot(op1,32);
+}
+
+
+vint64m1_t test___riscv_vnot(vint64m1_t op1,size_t vl)
+{
+    return __riscv_vnot(op1,32);
+}
+
+
+vint64m2_t test___riscv_vnot(vint64m2_t op1,size_t vl)
+{
+    return __riscv_vnot(op1,32);
+}
+
+
+vint64m4_t test___riscv_vnot(vint64m4_t op1,size_t vl)
+{
+    return __riscv_vnot(op1,32);
+}
+
+
+vint64m8_t test___riscv_vnot(vint64m8_t op1,size_t vl)
+{
+    return __riscv_vnot(op1,32);
+}
+
+
+vint8mf8_t test___riscv_vnot(vbool64_t mask,vint8mf8_t op1,size_t vl)
+{
+    return __riscv_vnot(mask,op1,32);
+}
+
+
+vint8mf4_t test___riscv_vnot(vbool32_t mask,vint8mf4_t op1,size_t vl)
+{
+    return __riscv_vnot(mask,op1,32);
+}
+
+
+vint8mf2_t test___riscv_vnot(vbool16_t mask,vint8mf2_t op1,size_t vl)
+{
+    return __riscv_vnot(mask,op1,32);
+}
+
+
+vint8m1_t test___riscv_vnot(vbool8_t mask,vint8m1_t op1,size_t vl)
+{
+    return __riscv_vnot(mask,op1,32);
+}
+
+
+vint8m2_t test___riscv_vnot(vbool4_t mask,vint8m2_t op1,size_t vl)
+{
+    return __riscv_vnot(mask,op1,32);
+}
+
+
+vint8m4_t test___riscv_vnot(vbool2_t mask,vint8m4_t op1,size_t vl)
+{
+    return __riscv_vnot(mask,op1,32);
+}
+
+
+vint8m8_t test___riscv_vnot(vbool1_t mask,vint8m8_t op1,size_t vl)
+{
+    return __riscv_vnot(mask,op1,32);
+}
+
+
+vint16mf4_t test___riscv_vnot(vbool64_t mask,vint16mf4_t op1,size_t vl)
+{
+    return __riscv_vnot(mask,op1,32);
+}
+
+
+vint16mf2_t test___riscv_vnot(vbool32_t mask,vint16mf2_t op1,size_t vl)
+{
+    return __riscv_vnot(mask,op1,32);
+}
+
+
+vint16m1_t test___riscv_vnot(vbool16_t mask,vint16m1_t op1,size_t vl)
+{
+    return __riscv_vnot(mask,op1,32);
+}
+
+
+vint16m2_t test___riscv_vnot(vbool8_t mask,vint16m2_t op1,size_t vl)
+{
+    return __riscv_vnot(mask,op1,32);
+}
+
+
+vint16m4_t test___riscv_vnot(vbool4_t mask,vint16m4_t op1,size_t vl)
+{
+    return __riscv_vnot(mask,op1,32);
+}
+
+
+vint16m8_t test___riscv_vnot(vbool2_t mask,vint16m8_t op1,size_t vl)
+{
+    return __riscv_vnot(mask,op1,32);
+}
+
+
+vint32mf2_t test___riscv_vnot(vbool64_t mask,vint32mf2_t op1,size_t vl)
+{
+    return __riscv_vnot(mask,op1,32);
+}
+
+
+vint32m1_t test___riscv_vnot(vbool32_t mask,vint32m1_t op1,size_t vl)
+{
+    return __riscv_vnot(mask,op1,32);
+}
+
+
+vint32m2_t test___riscv_vnot(vbool16_t mask,vint32m2_t op1,size_t vl)
+{
+    return __riscv_vnot(mask,op1,32);
+}
+
+
+vint32m4_t test___riscv_vnot(vbool8_t mask,vint32m4_t op1,size_t vl)
+{
+    return __riscv_vnot(mask,op1,32);
+}
+
+
+vint32m8_t test___riscv_vnot(vbool4_t mask,vint32m8_t op1,size_t vl)
+{
+    return __riscv_vnot(mask,op1,32);
+}
+
+
+vint64m1_t test___riscv_vnot(vbool64_t mask,vint64m1_t op1,size_t vl)
+{
+    return __riscv_vnot(mask,op1,32);
+}
+
+
+vint64m2_t test___riscv_vnot(vbool32_t mask,vint64m2_t op1,size_t vl)
+{
+    return __riscv_vnot(mask,op1,32);
+}
+
+
+vint64m4_t test___riscv_vnot(vbool16_t mask,vint64m4_t op1,size_t vl)
+{
+    return __riscv_vnot(mask,op1,32);
+}
+
+
+vint64m8_t test___riscv_vnot(vbool8_t mask,vint64m8_t op1,size_t vl)
+{
+    return __riscv_vnot(mask,op1,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_mu-1.C
new file mode 100644
index 00000000000..3fcbf02aed5
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_mu-1.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnot_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t vl)
+{
+    return __riscv_vnot_mu(mask,merge,op1,vl);
+}
+
+
+vint8mf4_t test___riscv_vnot_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t vl)
+{
+    return __riscv_vnot_mu(mask,merge,op1,vl);
+}
+
+
+vint8mf2_t test___riscv_vnot_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_mu(mask,merge,op1,vl);
+}
+
+
+vint8m1_t test___riscv_vnot_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t vl)
+{
+    return __riscv_vnot_mu(mask,merge,op1,vl);
+}
+
+
+vint8m2_t test___riscv_vnot_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t vl)
+{
+    return __riscv_vnot_mu(mask,merge,op1,vl);
+}
+
+
+vint8m4_t test___riscv_vnot_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t vl)
+{
+    return __riscv_vnot_mu(mask,merge,op1,vl);
+}
+
+
+vint8m8_t test___riscv_vnot_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t vl)
+{
+    return __riscv_vnot_mu(mask,merge,op1,vl);
+}
+
+
+vint16mf4_t test___riscv_vnot_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t vl)
+{
+    return __riscv_vnot_mu(mask,merge,op1,vl);
+}
+
+
+vint16mf2_t test___riscv_vnot_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_mu(mask,merge,op1,vl);
+}
+
+
+vint16m1_t test___riscv_vnot_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t vl)
+{
+    return __riscv_vnot_mu(mask,merge,op1,vl);
+}
+
+
+vint16m2_t test___riscv_vnot_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t vl)
+{
+    return __riscv_vnot_mu(mask,merge,op1,vl);
+}
+
+
+vint16m4_t test___riscv_vnot_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t vl)
+{
+    return __riscv_vnot_mu(mask,merge,op1,vl);
+}
+
+
+vint16m8_t test___riscv_vnot_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t vl)
+{
+    return __riscv_vnot_mu(mask,merge,op1,vl);
+}
+
+
+vint32mf2_t test___riscv_vnot_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_mu(mask,merge,op1,vl);
+}
+
+
+vint32m1_t test___riscv_vnot_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t vl)
+{
+    return __riscv_vnot_mu(mask,merge,op1,vl);
+}
+
+
+vint32m2_t test___riscv_vnot_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t vl)
+{
+    return __riscv_vnot_mu(mask,merge,op1,vl);
+}
+
+
+vint32m4_t test___riscv_vnot_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t vl)
+{
+    return __riscv_vnot_mu(mask,merge,op1,vl);
+}
+
+
+vint32m8_t test___riscv_vnot_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t vl)
+{
+    return __riscv_vnot_mu(mask,merge,op1,vl);
+}
+
+
+vint64m1_t test___riscv_vnot_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t vl)
+{
+    return __riscv_vnot_mu(mask,merge,op1,vl);
+}
+
+
+vint64m2_t test___riscv_vnot_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t vl)
+{
+    return __riscv_vnot_mu(mask,merge,op1,vl);
+}
+
+
+vint64m4_t test___riscv_vnot_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t vl)
+{
+    return __riscv_vnot_mu(mask,merge,op1,vl);
+}
+
+
+vint64m8_t test___riscv_vnot_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t vl)
+{
+    return __riscv_vnot_mu(mask,merge,op1,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_mu-2.C
new file mode 100644
index 00000000000..5dde6117a43
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_mu-2.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnot_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t vl)
+{
+    return __riscv_vnot_mu(mask,merge,op1,31);
+}
+
+
+vint8mf4_t test___riscv_vnot_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t vl)
+{
+    return __riscv_vnot_mu(mask,merge,op1,31);
+}
+
+
+vint8mf2_t test___riscv_vnot_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_mu(mask,merge,op1,31);
+}
+
+
+vint8m1_t test___riscv_vnot_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t vl)
+{
+    return __riscv_vnot_mu(mask,merge,op1,31);
+}
+
+
+vint8m2_t test___riscv_vnot_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t vl)
+{
+    return __riscv_vnot_mu(mask,merge,op1,31);
+}
+
+
+vint8m4_t test___riscv_vnot_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t vl)
+{
+    return __riscv_vnot_mu(mask,merge,op1,31);
+}
+
+
+vint8m8_t test___riscv_vnot_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t vl)
+{
+    return __riscv_vnot_mu(mask,merge,op1,31);
+}
+
+
+vint16mf4_t test___riscv_vnot_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t vl)
+{
+    return __riscv_vnot_mu(mask,merge,op1,31);
+}
+
+
+vint16mf2_t test___riscv_vnot_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_mu(mask,merge,op1,31);
+}
+
+
+vint16m1_t test___riscv_vnot_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t vl)
+{
+    return __riscv_vnot_mu(mask,merge,op1,31);
+}
+
+
+vint16m2_t test___riscv_vnot_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t vl)
+{
+    return __riscv_vnot_mu(mask,merge,op1,31);
+}
+
+
+vint16m4_t test___riscv_vnot_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t vl)
+{
+    return __riscv_vnot_mu(mask,merge,op1,31);
+}
+
+
+vint16m8_t test___riscv_vnot_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t vl)
+{
+    return __riscv_vnot_mu(mask,merge,op1,31);
+}
+
+
+vint32mf2_t test___riscv_vnot_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_mu(mask,merge,op1,31);
+}
+
+
+vint32m1_t test___riscv_vnot_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t vl)
+{
+    return __riscv_vnot_mu(mask,merge,op1,31);
+}
+
+
+vint32m2_t test___riscv_vnot_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t vl)
+{
+    return __riscv_vnot_mu(mask,merge,op1,31);
+}
+
+
+vint32m4_t test___riscv_vnot_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t vl)
+{
+    return __riscv_vnot_mu(mask,merge,op1,31);
+}
+
+
+vint32m8_t test___riscv_vnot_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t vl)
+{
+    return __riscv_vnot_mu(mask,merge,op1,31);
+}
+
+
+vint64m1_t test___riscv_vnot_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t vl)
+{
+    return __riscv_vnot_mu(mask,merge,op1,31);
+}
+
+
+vint64m2_t test___riscv_vnot_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t vl)
+{
+    return __riscv_vnot_mu(mask,merge,op1,31);
+}
+
+
+vint64m4_t test___riscv_vnot_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t vl)
+{
+    return __riscv_vnot_mu(mask,merge,op1,31);
+}
+
+
+vint64m8_t test___riscv_vnot_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t vl)
+{
+    return __riscv_vnot_mu(mask,merge,op1,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_mu-3.C
new file mode 100644
index 00000000000..c3637b98b66
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_mu-3.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnot_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t vl)
+{
+    return __riscv_vnot_mu(mask,merge,op1,32);
+}
+
+
+vint8mf4_t test___riscv_vnot_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t vl)
+{
+    return __riscv_vnot_mu(mask,merge,op1,32);
+}
+
+
+vint8mf2_t test___riscv_vnot_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_mu(mask,merge,op1,32);
+}
+
+
+vint8m1_t test___riscv_vnot_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t vl)
+{
+    return __riscv_vnot_mu(mask,merge,op1,32);
+}
+
+
+vint8m2_t test___riscv_vnot_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t vl)
+{
+    return __riscv_vnot_mu(mask,merge,op1,32);
+}
+
+
+vint8m4_t test___riscv_vnot_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t vl)
+{
+    return __riscv_vnot_mu(mask,merge,op1,32);
+}
+
+
+vint8m8_t test___riscv_vnot_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t vl)
+{
+    return __riscv_vnot_mu(mask,merge,op1,32);
+}
+
+
+vint16mf4_t test___riscv_vnot_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t vl)
+{
+    return __riscv_vnot_mu(mask,merge,op1,32);
+}
+
+
+vint16mf2_t test___riscv_vnot_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_mu(mask,merge,op1,32);
+}
+
+
+vint16m1_t test___riscv_vnot_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t vl)
+{
+    return __riscv_vnot_mu(mask,merge,op1,32);
+}
+
+
+vint16m2_t test___riscv_vnot_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t vl)
+{
+    return __riscv_vnot_mu(mask,merge,op1,32);
+}
+
+
+vint16m4_t test___riscv_vnot_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t vl)
+{
+    return __riscv_vnot_mu(mask,merge,op1,32);
+}
+
+
+vint16m8_t test___riscv_vnot_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t vl)
+{
+    return __riscv_vnot_mu(mask,merge,op1,32);
+}
+
+
+vint32mf2_t test___riscv_vnot_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_mu(mask,merge,op1,32);
+}
+
+
+vint32m1_t test___riscv_vnot_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t vl)
+{
+    return __riscv_vnot_mu(mask,merge,op1,32);
+}
+
+
+vint32m2_t test___riscv_vnot_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t vl)
+{
+    return __riscv_vnot_mu(mask,merge,op1,32);
+}
+
+
+vint32m4_t test___riscv_vnot_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t vl)
+{
+    return __riscv_vnot_mu(mask,merge,op1,32);
+}
+
+
+vint32m8_t test___riscv_vnot_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t vl)
+{
+    return __riscv_vnot_mu(mask,merge,op1,32);
+}
+
+
+vint64m1_t test___riscv_vnot_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t vl)
+{
+    return __riscv_vnot_mu(mask,merge,op1,32);
+}
+
+
+vint64m2_t test___riscv_vnot_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t vl)
+{
+    return __riscv_vnot_mu(mask,merge,op1,32);
+}
+
+
+vint64m4_t test___riscv_vnot_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t vl)
+{
+    return __riscv_vnot_mu(mask,merge,op1,32);
+}
+
+
+vint64m8_t test___riscv_vnot_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t vl)
+{
+    return __riscv_vnot_mu(mask,merge,op1,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tu-1.C
new file mode 100644
index 00000000000..25fb8e93c91
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tu-1.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnot_tu(vint8mf8_t merge,vint8mf8_t op1,size_t vl)
+{
+    return __riscv_vnot_tu(merge,op1,vl);
+}
+
+
+vint8mf4_t test___riscv_vnot_tu(vint8mf4_t merge,vint8mf4_t op1,size_t vl)
+{
+    return __riscv_vnot_tu(merge,op1,vl);
+}
+
+
+vint8mf2_t test___riscv_vnot_tu(vint8mf2_t merge,vint8mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_tu(merge,op1,vl);
+}
+
+
+vint8m1_t test___riscv_vnot_tu(vint8m1_t merge,vint8m1_t op1,size_t vl)
+{
+    return __riscv_vnot_tu(merge,op1,vl);
+}
+
+
+vint8m2_t test___riscv_vnot_tu(vint8m2_t merge,vint8m2_t op1,size_t vl)
+{
+    return __riscv_vnot_tu(merge,op1,vl);
+}
+
+
+vint8m4_t test___riscv_vnot_tu(vint8m4_t merge,vint8m4_t op1,size_t vl)
+{
+    return __riscv_vnot_tu(merge,op1,vl);
+}
+
+
+vint8m8_t test___riscv_vnot_tu(vint8m8_t merge,vint8m8_t op1,size_t vl)
+{
+    return __riscv_vnot_tu(merge,op1,vl);
+}
+
+
+vint16mf4_t test___riscv_vnot_tu(vint16mf4_t merge,vint16mf4_t op1,size_t vl)
+{
+    return __riscv_vnot_tu(merge,op1,vl);
+}
+
+
+vint16mf2_t test___riscv_vnot_tu(vint16mf2_t merge,vint16mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_tu(merge,op1,vl);
+}
+
+
+vint16m1_t test___riscv_vnot_tu(vint16m1_t merge,vint16m1_t op1,size_t vl)
+{
+    return __riscv_vnot_tu(merge,op1,vl);
+}
+
+
+vint16m2_t test___riscv_vnot_tu(vint16m2_t merge,vint16m2_t op1,size_t vl)
+{
+    return __riscv_vnot_tu(merge,op1,vl);
+}
+
+
+vint16m4_t test___riscv_vnot_tu(vint16m4_t merge,vint16m4_t op1,size_t vl)
+{
+    return __riscv_vnot_tu(merge,op1,vl);
+}
+
+
+vint16m8_t test___riscv_vnot_tu(vint16m8_t merge,vint16m8_t op1,size_t vl)
+{
+    return __riscv_vnot_tu(merge,op1,vl);
+}
+
+
+vint32mf2_t test___riscv_vnot_tu(vint32mf2_t merge,vint32mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_tu(merge,op1,vl);
+}
+
+
+vint32m1_t test___riscv_vnot_tu(vint32m1_t merge,vint32m1_t op1,size_t vl)
+{
+    return __riscv_vnot_tu(merge,op1,vl);
+}
+
+
+vint32m2_t test___riscv_vnot_tu(vint32m2_t merge,vint32m2_t op1,size_t vl)
+{
+    return __riscv_vnot_tu(merge,op1,vl);
+}
+
+
+vint32m4_t test___riscv_vnot_tu(vint32m4_t merge,vint32m4_t op1,size_t vl)
+{
+    return __riscv_vnot_tu(merge,op1,vl);
+}
+
+
+vint32m8_t test___riscv_vnot_tu(vint32m8_t merge,vint32m8_t op1,size_t vl)
+{
+    return __riscv_vnot_tu(merge,op1,vl);
+}
+
+
+vint64m1_t test___riscv_vnot_tu(vint64m1_t merge,vint64m1_t op1,size_t vl)
+{
+    return __riscv_vnot_tu(merge,op1,vl);
+}
+
+
+vint64m2_t test___riscv_vnot_tu(vint64m2_t merge,vint64m2_t op1,size_t vl)
+{
+    return __riscv_vnot_tu(merge,op1,vl);
+}
+
+
+vint64m4_t test___riscv_vnot_tu(vint64m4_t merge,vint64m4_t op1,size_t vl)
+{
+    return __riscv_vnot_tu(merge,op1,vl);
+}
+
+
+vint64m8_t test___riscv_vnot_tu(vint64m8_t merge,vint64m8_t op1,size_t vl)
+{
+    return __riscv_vnot_tu(merge,op1,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tu-2.C
new file mode 100644
index 00000000000..b05b86fce83
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tu-2.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnot_tu(vint8mf8_t merge,vint8mf8_t op1,size_t vl)
+{
+    return __riscv_vnot_tu(merge,op1,31);
+}
+
+
+vint8mf4_t test___riscv_vnot_tu(vint8mf4_t merge,vint8mf4_t op1,size_t vl)
+{
+    return __riscv_vnot_tu(merge,op1,31);
+}
+
+
+vint8mf2_t test___riscv_vnot_tu(vint8mf2_t merge,vint8mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_tu(merge,op1,31);
+}
+
+
+vint8m1_t test___riscv_vnot_tu(vint8m1_t merge,vint8m1_t op1,size_t vl)
+{
+    return __riscv_vnot_tu(merge,op1,31);
+}
+
+
+vint8m2_t test___riscv_vnot_tu(vint8m2_t merge,vint8m2_t op1,size_t vl)
+{
+    return __riscv_vnot_tu(merge,op1,31);
+}
+
+
+vint8m4_t test___riscv_vnot_tu(vint8m4_t merge,vint8m4_t op1,size_t vl)
+{
+    return __riscv_vnot_tu(merge,op1,31);
+}
+
+
+vint8m8_t test___riscv_vnot_tu(vint8m8_t merge,vint8m8_t op1,size_t vl)
+{
+    return __riscv_vnot_tu(merge,op1,31);
+}
+
+
+vint16mf4_t test___riscv_vnot_tu(vint16mf4_t merge,vint16mf4_t op1,size_t vl)
+{
+    return __riscv_vnot_tu(merge,op1,31);
+}
+
+
+vint16mf2_t test___riscv_vnot_tu(vint16mf2_t merge,vint16mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_tu(merge,op1,31);
+}
+
+
+vint16m1_t test___riscv_vnot_tu(vint16m1_t merge,vint16m1_t op1,size_t vl)
+{
+    return __riscv_vnot_tu(merge,op1,31);
+}
+
+
+vint16m2_t test___riscv_vnot_tu(vint16m2_t merge,vint16m2_t op1,size_t vl)
+{
+    return __riscv_vnot_tu(merge,op1,31);
+}
+
+
+vint16m4_t test___riscv_vnot_tu(vint16m4_t merge,vint16m4_t op1,size_t vl)
+{
+    return __riscv_vnot_tu(merge,op1,31);
+}
+
+
+vint16m8_t test___riscv_vnot_tu(vint16m8_t merge,vint16m8_t op1,size_t vl)
+{
+    return __riscv_vnot_tu(merge,op1,31);
+}
+
+
+vint32mf2_t test___riscv_vnot_tu(vint32mf2_t merge,vint32mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_tu(merge,op1,31);
+}
+
+
+vint32m1_t test___riscv_vnot_tu(vint32m1_t merge,vint32m1_t op1,size_t vl)
+{
+    return __riscv_vnot_tu(merge,op1,31);
+}
+
+
+vint32m2_t test___riscv_vnot_tu(vint32m2_t merge,vint32m2_t op1,size_t vl)
+{
+    return __riscv_vnot_tu(merge,op1,31);
+}
+
+
+vint32m4_t test___riscv_vnot_tu(vint32m4_t merge,vint32m4_t op1,size_t vl)
+{
+    return __riscv_vnot_tu(merge,op1,31);
+}
+
+
+vint32m8_t test___riscv_vnot_tu(vint32m8_t merge,vint32m8_t op1,size_t vl)
+{
+    return __riscv_vnot_tu(merge,op1,31);
+}
+
+
+vint64m1_t test___riscv_vnot_tu(vint64m1_t merge,vint64m1_t op1,size_t vl)
+{
+    return __riscv_vnot_tu(merge,op1,31);
+}
+
+
+vint64m2_t test___riscv_vnot_tu(vint64m2_t merge,vint64m2_t op1,size_t vl)
+{
+    return __riscv_vnot_tu(merge,op1,31);
+}
+
+
+vint64m4_t test___riscv_vnot_tu(vint64m4_t merge,vint64m4_t op1,size_t vl)
+{
+    return __riscv_vnot_tu(merge,op1,31);
+}
+
+
+vint64m8_t test___riscv_vnot_tu(vint64m8_t merge,vint64m8_t op1,size_t vl)
+{
+    return __riscv_vnot_tu(merge,op1,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tu-3.C
new file mode 100644
index 00000000000..7048f9ecc99
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tu-3.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnot_tu(vint8mf8_t merge,vint8mf8_t op1,size_t vl)
+{
+    return __riscv_vnot_tu(merge,op1,32);
+}
+
+
+vint8mf4_t test___riscv_vnot_tu(vint8mf4_t merge,vint8mf4_t op1,size_t vl)
+{
+    return __riscv_vnot_tu(merge,op1,32);
+}
+
+
+vint8mf2_t test___riscv_vnot_tu(vint8mf2_t merge,vint8mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_tu(merge,op1,32);
+}
+
+
+vint8m1_t test___riscv_vnot_tu(vint8m1_t merge,vint8m1_t op1,size_t vl)
+{
+    return __riscv_vnot_tu(merge,op1,32);
+}
+
+
+vint8m2_t test___riscv_vnot_tu(vint8m2_t merge,vint8m2_t op1,size_t vl)
+{
+    return __riscv_vnot_tu(merge,op1,32);
+}
+
+
+vint8m4_t test___riscv_vnot_tu(vint8m4_t merge,vint8m4_t op1,size_t vl)
+{
+    return __riscv_vnot_tu(merge,op1,32);
+}
+
+
+vint8m8_t test___riscv_vnot_tu(vint8m8_t merge,vint8m8_t op1,size_t vl)
+{
+    return __riscv_vnot_tu(merge,op1,32);
+}
+
+
+vint16mf4_t test___riscv_vnot_tu(vint16mf4_t merge,vint16mf4_t op1,size_t vl)
+{
+    return __riscv_vnot_tu(merge,op1,32);
+}
+
+
+vint16mf2_t test___riscv_vnot_tu(vint16mf2_t merge,vint16mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_tu(merge,op1,32);
+}
+
+
+vint16m1_t test___riscv_vnot_tu(vint16m1_t merge,vint16m1_t op1,size_t vl)
+{
+    return __riscv_vnot_tu(merge,op1,32);
+}
+
+
+vint16m2_t test___riscv_vnot_tu(vint16m2_t merge,vint16m2_t op1,size_t vl)
+{
+    return __riscv_vnot_tu(merge,op1,32);
+}
+
+
+vint16m4_t test___riscv_vnot_tu(vint16m4_t merge,vint16m4_t op1,size_t vl)
+{
+    return __riscv_vnot_tu(merge,op1,32);
+}
+
+
+vint16m8_t test___riscv_vnot_tu(vint16m8_t merge,vint16m8_t op1,size_t vl)
+{
+    return __riscv_vnot_tu(merge,op1,32);
+}
+
+
+vint32mf2_t test___riscv_vnot_tu(vint32mf2_t merge,vint32mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_tu(merge,op1,32);
+}
+
+
+vint32m1_t test___riscv_vnot_tu(vint32m1_t merge,vint32m1_t op1,size_t vl)
+{
+    return __riscv_vnot_tu(merge,op1,32);
+}
+
+
+vint32m2_t test___riscv_vnot_tu(vint32m2_t merge,vint32m2_t op1,size_t vl)
+{
+    return __riscv_vnot_tu(merge,op1,32);
+}
+
+
+vint32m4_t test___riscv_vnot_tu(vint32m4_t merge,vint32m4_t op1,size_t vl)
+{
+    return __riscv_vnot_tu(merge,op1,32);
+}
+
+
+vint32m8_t test___riscv_vnot_tu(vint32m8_t merge,vint32m8_t op1,size_t vl)
+{
+    return __riscv_vnot_tu(merge,op1,32);
+}
+
+
+vint64m1_t test___riscv_vnot_tu(vint64m1_t merge,vint64m1_t op1,size_t vl)
+{
+    return __riscv_vnot_tu(merge,op1,32);
+}
+
+
+vint64m2_t test___riscv_vnot_tu(vint64m2_t merge,vint64m2_t op1,size_t vl)
+{
+    return __riscv_vnot_tu(merge,op1,32);
+}
+
+
+vint64m4_t test___riscv_vnot_tu(vint64m4_t merge,vint64m4_t op1,size_t vl)
+{
+    return __riscv_vnot_tu(merge,op1,32);
+}
+
+
+vint64m8_t test___riscv_vnot_tu(vint64m8_t merge,vint64m8_t op1,size_t vl)
+{
+    return __riscv_vnot_tu(merge,op1,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tum-1.C
new file mode 100644
index 00000000000..151f6559f9f
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tum-1.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnot_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t vl)
+{
+    return __riscv_vnot_tum(mask,merge,op1,vl);
+}
+
+
+vint8mf4_t test___riscv_vnot_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t vl)
+{
+    return __riscv_vnot_tum(mask,merge,op1,vl);
+}
+
+
+vint8mf2_t test___riscv_vnot_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_tum(mask,merge,op1,vl);
+}
+
+
+vint8m1_t test___riscv_vnot_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t vl)
+{
+    return __riscv_vnot_tum(mask,merge,op1,vl);
+}
+
+
+vint8m2_t test___riscv_vnot_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t vl)
+{
+    return __riscv_vnot_tum(mask,merge,op1,vl);
+}
+
+
+vint8m4_t test___riscv_vnot_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t vl)
+{
+    return __riscv_vnot_tum(mask,merge,op1,vl);
+}
+
+
+vint8m8_t test___riscv_vnot_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t vl)
+{
+    return __riscv_vnot_tum(mask,merge,op1,vl);
+}
+
+
+vint16mf4_t test___riscv_vnot_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t vl)
+{
+    return __riscv_vnot_tum(mask,merge,op1,vl);
+}
+
+
+vint16mf2_t test___riscv_vnot_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_tum(mask,merge,op1,vl);
+}
+
+
+vint16m1_t test___riscv_vnot_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t vl)
+{
+    return __riscv_vnot_tum(mask,merge,op1,vl);
+}
+
+
+vint16m2_t test___riscv_vnot_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t vl)
+{
+    return __riscv_vnot_tum(mask,merge,op1,vl);
+}
+
+
+vint16m4_t test___riscv_vnot_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t vl)
+{
+    return __riscv_vnot_tum(mask,merge,op1,vl);
+}
+
+
+vint16m8_t test___riscv_vnot_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t vl)
+{
+    return __riscv_vnot_tum(mask,merge,op1,vl);
+}
+
+
+vint32mf2_t test___riscv_vnot_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_tum(mask,merge,op1,vl);
+}
+
+
+vint32m1_t test___riscv_vnot_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t vl)
+{
+    return __riscv_vnot_tum(mask,merge,op1,vl);
+}
+
+
+vint32m2_t test___riscv_vnot_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t vl)
+{
+    return __riscv_vnot_tum(mask,merge,op1,vl);
+}
+
+
+vint32m4_t test___riscv_vnot_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t vl)
+{
+    return __riscv_vnot_tum(mask,merge,op1,vl);
+}
+
+
+vint32m8_t test___riscv_vnot_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t vl)
+{
+    return __riscv_vnot_tum(mask,merge,op1,vl);
+}
+
+
+vint64m1_t test___riscv_vnot_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t vl)
+{
+    return __riscv_vnot_tum(mask,merge,op1,vl);
+}
+
+
+vint64m2_t test___riscv_vnot_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t vl)
+{
+    return __riscv_vnot_tum(mask,merge,op1,vl);
+}
+
+
+vint64m4_t test___riscv_vnot_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t vl)
+{
+    return __riscv_vnot_tum(mask,merge,op1,vl);
+}
+
+
+vint64m8_t test___riscv_vnot_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t vl)
+{
+    return __riscv_vnot_tum(mask,merge,op1,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tum-2.C
new file mode 100644
index 00000000000..a9d767d88f4
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tum-2.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnot_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t vl)
+{
+    return __riscv_vnot_tum(mask,merge,op1,31);
+}
+
+
+vint8mf4_t test___riscv_vnot_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t vl)
+{
+    return __riscv_vnot_tum(mask,merge,op1,31);
+}
+
+
+vint8mf2_t test___riscv_vnot_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_tum(mask,merge,op1,31);
+}
+
+
+vint8m1_t test___riscv_vnot_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t vl)
+{
+    return __riscv_vnot_tum(mask,merge,op1,31);
+}
+
+
+vint8m2_t test___riscv_vnot_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t vl)
+{
+    return __riscv_vnot_tum(mask,merge,op1,31);
+}
+
+
+vint8m4_t test___riscv_vnot_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t vl)
+{
+    return __riscv_vnot_tum(mask,merge,op1,31);
+}
+
+
+vint8m8_t test___riscv_vnot_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t vl)
+{
+    return __riscv_vnot_tum(mask,merge,op1,31);
+}
+
+
+vint16mf4_t test___riscv_vnot_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t vl)
+{
+    return __riscv_vnot_tum(mask,merge,op1,31);
+}
+
+
+vint16mf2_t test___riscv_vnot_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_tum(mask,merge,op1,31);
+}
+
+
+vint16m1_t test___riscv_vnot_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t vl)
+{
+    return __riscv_vnot_tum(mask,merge,op1,31);
+}
+
+
+vint16m2_t test___riscv_vnot_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t vl)
+{
+    return __riscv_vnot_tum(mask,merge,op1,31);
+}
+
+
+vint16m4_t test___riscv_vnot_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t vl)
+{
+    return __riscv_vnot_tum(mask,merge,op1,31);
+}
+
+
+vint16m8_t test___riscv_vnot_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t vl)
+{
+    return __riscv_vnot_tum(mask,merge,op1,31);
+}
+
+
+vint32mf2_t test___riscv_vnot_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_tum(mask,merge,op1,31);
+}
+
+
+vint32m1_t test___riscv_vnot_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t vl)
+{
+    return __riscv_vnot_tum(mask,merge,op1,31);
+}
+
+
+vint32m2_t test___riscv_vnot_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t vl)
+{
+    return __riscv_vnot_tum(mask,merge,op1,31);
+}
+
+
+vint32m4_t test___riscv_vnot_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t vl)
+{
+    return __riscv_vnot_tum(mask,merge,op1,31);
+}
+
+
+vint32m8_t test___riscv_vnot_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t vl)
+{
+    return __riscv_vnot_tum(mask,merge,op1,31);
+}
+
+
+vint64m1_t test___riscv_vnot_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t vl)
+{
+    return __riscv_vnot_tum(mask,merge,op1,31);
+}
+
+
+vint64m2_t test___riscv_vnot_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t vl)
+{
+    return __riscv_vnot_tum(mask,merge,op1,31);
+}
+
+
+vint64m4_t test___riscv_vnot_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t vl)
+{
+    return __riscv_vnot_tum(mask,merge,op1,31);
+}
+
+
+vint64m8_t test___riscv_vnot_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t vl)
+{
+    return __riscv_vnot_tum(mask,merge,op1,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tum-3.C
new file mode 100644
index 00000000000..1d39bcc7349
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tum-3.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnot_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t vl)
+{
+    return __riscv_vnot_tum(mask,merge,op1,32);
+}
+
+
+vint8mf4_t test___riscv_vnot_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t vl)
+{
+    return __riscv_vnot_tum(mask,merge,op1,32);
+}
+
+
+vint8mf2_t test___riscv_vnot_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_tum(mask,merge,op1,32);
+}
+
+
+vint8m1_t test___riscv_vnot_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t vl)
+{
+    return __riscv_vnot_tum(mask,merge,op1,32);
+}
+
+
+vint8m2_t test___riscv_vnot_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t vl)
+{
+    return __riscv_vnot_tum(mask,merge,op1,32);
+}
+
+
+vint8m4_t test___riscv_vnot_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t vl)
+{
+    return __riscv_vnot_tum(mask,merge,op1,32);
+}
+
+
+vint8m8_t test___riscv_vnot_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t vl)
+{
+    return __riscv_vnot_tum(mask,merge,op1,32);
+}
+
+
+vint16mf4_t test___riscv_vnot_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t vl)
+{
+    return __riscv_vnot_tum(mask,merge,op1,32);
+}
+
+
+vint16mf2_t test___riscv_vnot_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_tum(mask,merge,op1,32);
+}
+
+
+vint16m1_t test___riscv_vnot_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t vl)
+{
+    return __riscv_vnot_tum(mask,merge,op1,32);
+}
+
+
+vint16m2_t test___riscv_vnot_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t vl)
+{
+    return __riscv_vnot_tum(mask,merge,op1,32);
+}
+
+
+vint16m4_t test___riscv_vnot_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t vl)
+{
+    return __riscv_vnot_tum(mask,merge,op1,32);
+}
+
+
+vint16m8_t test___riscv_vnot_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t vl)
+{
+    return __riscv_vnot_tum(mask,merge,op1,32);
+}
+
+
+vint32mf2_t test___riscv_vnot_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_tum(mask,merge,op1,32);
+}
+
+
+vint32m1_t test___riscv_vnot_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t vl)
+{
+    return __riscv_vnot_tum(mask,merge,op1,32);
+}
+
+
+vint32m2_t test___riscv_vnot_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t vl)
+{
+    return __riscv_vnot_tum(mask,merge,op1,32);
+}
+
+
+vint32m4_t test___riscv_vnot_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t vl)
+{
+    return __riscv_vnot_tum(mask,merge,op1,32);
+}
+
+
+vint32m8_t test___riscv_vnot_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t vl)
+{
+    return __riscv_vnot_tum(mask,merge,op1,32);
+}
+
+
+vint64m1_t test___riscv_vnot_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t vl)
+{
+    return __riscv_vnot_tum(mask,merge,op1,32);
+}
+
+
+vint64m2_t test___riscv_vnot_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t vl)
+{
+    return __riscv_vnot_tum(mask,merge,op1,32);
+}
+
+
+vint64m4_t test___riscv_vnot_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t vl)
+{
+    return __riscv_vnot_tum(mask,merge,op1,32);
+}
+
+
+vint64m8_t test___riscv_vnot_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t vl)
+{
+    return __riscv_vnot_tum(mask,merge,op1,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tumu-1.C
new file mode 100644
index 00000000000..9dfe96a8474
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tumu-1.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnot_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t vl)
+{
+    return __riscv_vnot_tumu(mask,merge,op1,vl);
+}
+
+
+vint8mf4_t test___riscv_vnot_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t vl)
+{
+    return __riscv_vnot_tumu(mask,merge,op1,vl);
+}
+
+
+vint8mf2_t test___riscv_vnot_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_tumu(mask,merge,op1,vl);
+}
+
+
+vint8m1_t test___riscv_vnot_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t vl)
+{
+    return __riscv_vnot_tumu(mask,merge,op1,vl);
+}
+
+
+vint8m2_t test___riscv_vnot_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t vl)
+{
+    return __riscv_vnot_tumu(mask,merge,op1,vl);
+}
+
+
+vint8m4_t test___riscv_vnot_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t vl)
+{
+    return __riscv_vnot_tumu(mask,merge,op1,vl);
+}
+
+
+vint8m8_t test___riscv_vnot_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t vl)
+{
+    return __riscv_vnot_tumu(mask,merge,op1,vl);
+}
+
+
+vint16mf4_t test___riscv_vnot_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t vl)
+{
+    return __riscv_vnot_tumu(mask,merge,op1,vl);
+}
+
+
+vint16mf2_t test___riscv_vnot_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_tumu(mask,merge,op1,vl);
+}
+
+
+vint16m1_t test___riscv_vnot_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t vl)
+{
+    return __riscv_vnot_tumu(mask,merge,op1,vl);
+}
+
+
+vint16m2_t test___riscv_vnot_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t vl)
+{
+    return __riscv_vnot_tumu(mask,merge,op1,vl);
+}
+
+
+vint16m4_t test___riscv_vnot_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t vl)
+{
+    return __riscv_vnot_tumu(mask,merge,op1,vl);
+}
+
+
+vint16m8_t test___riscv_vnot_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t vl)
+{
+    return __riscv_vnot_tumu(mask,merge,op1,vl);
+}
+
+
+vint32mf2_t test___riscv_vnot_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_tumu(mask,merge,op1,vl);
+}
+
+
+vint32m1_t test___riscv_vnot_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t vl)
+{
+    return __riscv_vnot_tumu(mask,merge,op1,vl);
+}
+
+
+vint32m2_t test___riscv_vnot_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t vl)
+{
+    return __riscv_vnot_tumu(mask,merge,op1,vl);
+}
+
+
+vint32m4_t test___riscv_vnot_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t vl)
+{
+    return __riscv_vnot_tumu(mask,merge,op1,vl);
+}
+
+
+vint32m8_t test___riscv_vnot_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t vl)
+{
+    return __riscv_vnot_tumu(mask,merge,op1,vl);
+}
+
+
+vint64m1_t test___riscv_vnot_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t vl)
+{
+    return __riscv_vnot_tumu(mask,merge,op1,vl);
+}
+
+
+vint64m2_t test___riscv_vnot_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t vl)
+{
+    return __riscv_vnot_tumu(mask,merge,op1,vl);
+}
+
+
+vint64m4_t test___riscv_vnot_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t vl)
+{
+    return __riscv_vnot_tumu(mask,merge,op1,vl);
+}
+
+
+vint64m8_t test___riscv_vnot_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t vl)
+{
+    return __riscv_vnot_tumu(mask,merge,op1,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tumu-2.C
new file mode 100644
index 00000000000..223b7ce3865
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tumu-2.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnot_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t vl)
+{
+    return __riscv_vnot_tumu(mask,merge,op1,31);
+}
+
+
+vint8mf4_t test___riscv_vnot_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t vl)
+{
+    return __riscv_vnot_tumu(mask,merge,op1,31);
+}
+
+
+vint8mf2_t test___riscv_vnot_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_tumu(mask,merge,op1,31);
+}
+
+
+vint8m1_t test___riscv_vnot_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t vl)
+{
+    return __riscv_vnot_tumu(mask,merge,op1,31);
+}
+
+
+vint8m2_t test___riscv_vnot_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t vl)
+{
+    return __riscv_vnot_tumu(mask,merge,op1,31);
+}
+
+
+vint8m4_t test___riscv_vnot_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t vl)
+{
+    return __riscv_vnot_tumu(mask,merge,op1,31);
+}
+
+
+vint8m8_t test___riscv_vnot_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t vl)
+{
+    return __riscv_vnot_tumu(mask,merge,op1,31);
+}
+
+
+vint16mf4_t test___riscv_vnot_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t vl)
+{
+    return __riscv_vnot_tumu(mask,merge,op1,31);
+}
+
+
+vint16mf2_t test___riscv_vnot_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_tumu(mask,merge,op1,31);
+}
+
+
+vint16m1_t test___riscv_vnot_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t vl)
+{
+    return __riscv_vnot_tumu(mask,merge,op1,31);
+}
+
+
+vint16m2_t test___riscv_vnot_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t vl)
+{
+    return __riscv_vnot_tumu(mask,merge,op1,31);
+}
+
+
+vint16m4_t test___riscv_vnot_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t vl)
+{
+    return __riscv_vnot_tumu(mask,merge,op1,31);
+}
+
+
+vint16m8_t test___riscv_vnot_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t vl)
+{
+    return __riscv_vnot_tumu(mask,merge,op1,31);
+}
+
+
+vint32mf2_t test___riscv_vnot_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_tumu(mask,merge,op1,31);
+}
+
+
+vint32m1_t test___riscv_vnot_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t vl)
+{
+    return __riscv_vnot_tumu(mask,merge,op1,31);
+}
+
+
+vint32m2_t test___riscv_vnot_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t vl)
+{
+    return __riscv_vnot_tumu(mask,merge,op1,31);
+}
+
+
+vint32m4_t test___riscv_vnot_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t vl)
+{
+    return __riscv_vnot_tumu(mask,merge,op1,31);
+}
+
+
+vint32m8_t test___riscv_vnot_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t vl)
+{
+    return __riscv_vnot_tumu(mask,merge,op1,31);
+}
+
+
+vint64m1_t test___riscv_vnot_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t vl)
+{
+    return __riscv_vnot_tumu(mask,merge,op1,31);
+}
+
+
+vint64m2_t test___riscv_vnot_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t vl)
+{
+    return __riscv_vnot_tumu(mask,merge,op1,31);
+}
+
+
+vint64m4_t test___riscv_vnot_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t vl)
+{
+    return __riscv_vnot_tumu(mask,merge,op1,31);
+}
+
+
+vint64m8_t test___riscv_vnot_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t vl)
+{
+    return __riscv_vnot_tumu(mask,merge,op1,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tumu-3.C
new file mode 100644
index 00000000000..492595d74b1
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vnot_v_tumu-3.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vnot_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t vl)
+{
+    return __riscv_vnot_tumu(mask,merge,op1,32);
+}
+
+
+vint8mf4_t test___riscv_vnot_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t vl)
+{
+    return __riscv_vnot_tumu(mask,merge,op1,32);
+}
+
+
+vint8mf2_t test___riscv_vnot_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_tumu(mask,merge,op1,32);
+}
+
+
+vint8m1_t test___riscv_vnot_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t vl)
+{
+    return __riscv_vnot_tumu(mask,merge,op1,32);
+}
+
+
+vint8m2_t test___riscv_vnot_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t vl)
+{
+    return __riscv_vnot_tumu(mask,merge,op1,32);
+}
+
+
+vint8m4_t test___riscv_vnot_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t vl)
+{
+    return __riscv_vnot_tumu(mask,merge,op1,32);
+}
+
+
+vint8m8_t test___riscv_vnot_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t vl)
+{
+    return __riscv_vnot_tumu(mask,merge,op1,32);
+}
+
+
+vint16mf4_t test___riscv_vnot_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t vl)
+{
+    return __riscv_vnot_tumu(mask,merge,op1,32);
+}
+
+
+vint16mf2_t test___riscv_vnot_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_tumu(mask,merge,op1,32);
+}
+
+
+vint16m1_t test___riscv_vnot_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t vl)
+{
+    return __riscv_vnot_tumu(mask,merge,op1,32);
+}
+
+
+vint16m2_t test___riscv_vnot_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t vl)
+{
+    return __riscv_vnot_tumu(mask,merge,op1,32);
+}
+
+
+vint16m4_t test___riscv_vnot_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t vl)
+{
+    return __riscv_vnot_tumu(mask,merge,op1,32);
+}
+
+
+vint16m8_t test___riscv_vnot_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t vl)
+{
+    return __riscv_vnot_tumu(mask,merge,op1,32);
+}
+
+
+vint32mf2_t test___riscv_vnot_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t vl)
+{
+    return __riscv_vnot_tumu(mask,merge,op1,32);
+}
+
+
+vint32m1_t test___riscv_vnot_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t vl)
+{
+    return __riscv_vnot_tumu(mask,merge,op1,32);
+}
+
+
+vint32m2_t test___riscv_vnot_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t vl)
+{
+    return __riscv_vnot_tumu(mask,merge,op1,32);
+}
+
+
+vint32m4_t test___riscv_vnot_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t vl)
+{
+    return __riscv_vnot_tumu(mask,merge,op1,32);
+}
+
+
+vint32m8_t test___riscv_vnot_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t vl)
+{
+    return __riscv_vnot_tumu(mask,merge,op1,32);
+}
+
+
+vint64m1_t test___riscv_vnot_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t vl)
+{
+    return __riscv_vnot_tumu(mask,merge,op1,32);
+}
+
+
+vint64m2_t test___riscv_vnot_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t vl)
+{
+    return __riscv_vnot_tumu(mask,merge,op1,32);
+}
+
+
+vint64m4_t test___riscv_vnot_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t vl)
+{
+    return __riscv_vnot_tumu(mask,merge,op1,32);
+}
+
+
+vint64m8_t test___riscv_vnot_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t vl)
+{
+    return __riscv_vnot_tumu(mask,merge,op1,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vnot\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
-- 
2.36.1


^ permalink raw reply	[flat|nested] 2+ messages in thread

end of thread, other threads:[~2023-02-03 23:26 UTC | newest]

Thread overview: 2+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-02-03 23:22 [PATCH] RISC-V: Add vnot.v C API tests juzhe.zhong
2023-02-03 23:26 [PATCH] RISC-V: Add vnot.v C++ " juzhe.zhong

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).