From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtpbguseast1.qq.com (smtpbguseast1.qq.com [54.204.34.129]) by sourceware.org (Postfix) with ESMTPS id E7A303858023 for ; Fri, 3 Feb 2023 23:24:14 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org E7A303858023 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp71t1675466650tzc6ziwd Received: from server1.localdomain ( [58.60.1.22]) by bizesmtp.qq.com (ESMTP) with id ; Sat, 04 Feb 2023 07:24:09 +0800 (CST) X-QQ-SSF: 01400000000000E0L000000A0000000 X-QQ-FEAT: i2nI4foPnFtRBjSsu8O89nCdyWb3N4m75fV9UUUlRYrocgzhaiXfoGKKubvp6 DO2IiVF8Ek2322jfN9iW1VEl2N98x+5VPVcJCfCpZ2YBfgYXRkXVfCINtgbGA6eGiEx/HLp UOJnWgxVGTqlRW0tnHSu2dFBqudW20ehOg8GlA3Bx6eDkgsV1Eq5DpvfaBptSElh1G0Pu9d hc4woTqqwtbUDY+TN3ALVxtv+s/eThlc5V9tvXCmbNDe59Aao1UcLz0LRNMGkwCmVH7pZaN 8n9uDw5qCHeXxHtySEv9R7l+/h0RR/BA5nIg65Zq+/H2jl8fa2mJmNF3mcYkbAGH3UAJ8dg htTiFsZoWRkHdftgxvJTkLvu38bgO9R7zUWDzsgEsPxueLWFTI= X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: Add vneg.v C/C++ API tests Date: Sat, 4 Feb 2023 07:24:08 +0800 Message-Id: <20230203232408.224338-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,KAM_SHORT,RCVD_IN_BARRACUDACENTRAL,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Ju-Zhe Zhong gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/vneg_v-1.c: New test. * gcc.target/riscv/rvv/base/vneg_v-2.c: New test. * gcc.target/riscv/rvv/base/vneg_v-3.c: New test. * gcc.target/riscv/rvv/base/vneg_v_m-1.c: New test. * gcc.target/riscv/rvv/base/vneg_v_m-2.c: New test. * gcc.target/riscv/rvv/base/vneg_v_m-3.c: New test. * gcc.target/riscv/rvv/base/vneg_v_mu-1.c: New test. * gcc.target/riscv/rvv/base/vneg_v_mu-2.c: New test. * gcc.target/riscv/rvv/base/vneg_v_mu-3.c: New test. * gcc.target/riscv/rvv/base/vneg_v_tu-1.c: New test. * gcc.target/riscv/rvv/base/vneg_v_tu-2.c: New test. * gcc.target/riscv/rvv/base/vneg_v_tu-3.c: New test. * gcc.target/riscv/rvv/base/vneg_v_tum-1.c: New test. * gcc.target/riscv/rvv/base/vneg_v_tum-2.c: New test. * gcc.target/riscv/rvv/base/vneg_v_tum-3.c: New test. * gcc.target/riscv/rvv/base/vneg_v_tumu-1.c: New test. * gcc.target/riscv/rvv/base/vneg_v_tumu-2.c: New test. * gcc.target/riscv/rvv/base/vneg_v_tumu-3.c: New test. --- .../gcc.target/riscv/rvv/base/vneg_v-1.c | 160 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vneg_v-2.c | 160 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vneg_v-3.c | 160 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vneg_v_m-1.c | 160 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vneg_v_m-2.c | 160 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vneg_v_m-3.c | 160 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vneg_v_mu-1.c | 160 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vneg_v_mu-2.c | 160 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vneg_v_mu-3.c | 160 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vneg_v_tu-1.c | 160 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vneg_v_tu-2.c | 160 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vneg_v_tu-3.c | 160 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vneg_v_tum-1.c | 160 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vneg_v_tum-2.c | 160 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vneg_v_tum-3.c | 160 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vneg_v_tumu-1.c | 160 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vneg_v_tumu-2.c | 160 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/vneg_v_tumu-3.c | 160 ++++++++++++++++++ 18 files changed, 2880 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_tumu-3.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v-1.c new file mode 100644 index 00000000000..e573a26e258 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v-1.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vneg_v_i8mf8(vint8mf8_t op1,size_t vl) +{ + return __riscv_vneg_v_i8mf8(op1,vl); +} + + +vint8mf4_t test___riscv_vneg_v_i8mf4(vint8mf4_t op1,size_t vl) +{ + return __riscv_vneg_v_i8mf4(op1,vl); +} + + +vint8mf2_t test___riscv_vneg_v_i8mf2(vint8mf2_t op1,size_t vl) +{ + return __riscv_vneg_v_i8mf2(op1,vl); +} + + +vint8m1_t test___riscv_vneg_v_i8m1(vint8m1_t op1,size_t vl) +{ + return __riscv_vneg_v_i8m1(op1,vl); +} + + +vint8m2_t test___riscv_vneg_v_i8m2(vint8m2_t op1,size_t vl) +{ + return __riscv_vneg_v_i8m2(op1,vl); +} + + +vint8m4_t test___riscv_vneg_v_i8m4(vint8m4_t op1,size_t vl) +{ + return __riscv_vneg_v_i8m4(op1,vl); +} + + +vint8m8_t test___riscv_vneg_v_i8m8(vint8m8_t op1,size_t vl) +{ + return __riscv_vneg_v_i8m8(op1,vl); +} + + +vint16mf4_t test___riscv_vneg_v_i16mf4(vint16mf4_t op1,size_t vl) +{ + return __riscv_vneg_v_i16mf4(op1,vl); +} + + +vint16mf2_t test___riscv_vneg_v_i16mf2(vint16mf2_t op1,size_t vl) +{ + return __riscv_vneg_v_i16mf2(op1,vl); +} + + +vint16m1_t test___riscv_vneg_v_i16m1(vint16m1_t op1,size_t vl) +{ + return __riscv_vneg_v_i16m1(op1,vl); +} + + +vint16m2_t test___riscv_vneg_v_i16m2(vint16m2_t op1,size_t vl) +{ + return __riscv_vneg_v_i16m2(op1,vl); +} + + +vint16m4_t test___riscv_vneg_v_i16m4(vint16m4_t op1,size_t vl) +{ + return __riscv_vneg_v_i16m4(op1,vl); +} + + +vint16m8_t test___riscv_vneg_v_i16m8(vint16m8_t op1,size_t vl) +{ + return __riscv_vneg_v_i16m8(op1,vl); +} + + +vint32mf2_t test___riscv_vneg_v_i32mf2(vint32mf2_t op1,size_t vl) +{ + return __riscv_vneg_v_i32mf2(op1,vl); +} + + +vint32m1_t test___riscv_vneg_v_i32m1(vint32m1_t op1,size_t vl) +{ + return __riscv_vneg_v_i32m1(op1,vl); +} + + +vint32m2_t test___riscv_vneg_v_i32m2(vint32m2_t op1,size_t vl) +{ + return __riscv_vneg_v_i32m2(op1,vl); +} + + +vint32m4_t test___riscv_vneg_v_i32m4(vint32m4_t op1,size_t vl) +{ + return __riscv_vneg_v_i32m4(op1,vl); +} + + +vint32m8_t test___riscv_vneg_v_i32m8(vint32m8_t op1,size_t vl) +{ + return __riscv_vneg_v_i32m8(op1,vl); +} + + +vint64m1_t test___riscv_vneg_v_i64m1(vint64m1_t op1,size_t vl) +{ + return __riscv_vneg_v_i64m1(op1,vl); +} + + +vint64m2_t test___riscv_vneg_v_i64m2(vint64m2_t op1,size_t vl) +{ + return __riscv_vneg_v_i64m2(op1,vl); +} + + +vint64m4_t test___riscv_vneg_v_i64m4(vint64m4_t op1,size_t vl) +{ + return __riscv_vneg_v_i64m4(op1,vl); +} + + +vint64m8_t test___riscv_vneg_v_i64m8(vint64m8_t op1,size_t vl) +{ + return __riscv_vneg_v_i64m8(op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v-2.c new file mode 100644 index 00000000000..c7bde883bf4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v-2.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vneg_v_i8mf8(vint8mf8_t op1,size_t vl) +{ + return __riscv_vneg_v_i8mf8(op1,31); +} + + +vint8mf4_t test___riscv_vneg_v_i8mf4(vint8mf4_t op1,size_t vl) +{ + return __riscv_vneg_v_i8mf4(op1,31); +} + + +vint8mf2_t test___riscv_vneg_v_i8mf2(vint8mf2_t op1,size_t vl) +{ + return __riscv_vneg_v_i8mf2(op1,31); +} + + +vint8m1_t test___riscv_vneg_v_i8m1(vint8m1_t op1,size_t vl) +{ + return __riscv_vneg_v_i8m1(op1,31); +} + + +vint8m2_t test___riscv_vneg_v_i8m2(vint8m2_t op1,size_t vl) +{ + return __riscv_vneg_v_i8m2(op1,31); +} + + +vint8m4_t test___riscv_vneg_v_i8m4(vint8m4_t op1,size_t vl) +{ + return __riscv_vneg_v_i8m4(op1,31); +} + + +vint8m8_t test___riscv_vneg_v_i8m8(vint8m8_t op1,size_t vl) +{ + return __riscv_vneg_v_i8m8(op1,31); +} + + +vint16mf4_t test___riscv_vneg_v_i16mf4(vint16mf4_t op1,size_t vl) +{ + return __riscv_vneg_v_i16mf4(op1,31); +} + + +vint16mf2_t test___riscv_vneg_v_i16mf2(vint16mf2_t op1,size_t vl) +{ + return __riscv_vneg_v_i16mf2(op1,31); +} + + +vint16m1_t test___riscv_vneg_v_i16m1(vint16m1_t op1,size_t vl) +{ + return __riscv_vneg_v_i16m1(op1,31); +} + + +vint16m2_t test___riscv_vneg_v_i16m2(vint16m2_t op1,size_t vl) +{ + return __riscv_vneg_v_i16m2(op1,31); +} + + +vint16m4_t test___riscv_vneg_v_i16m4(vint16m4_t op1,size_t vl) +{ + return __riscv_vneg_v_i16m4(op1,31); +} + + +vint16m8_t test___riscv_vneg_v_i16m8(vint16m8_t op1,size_t vl) +{ + return __riscv_vneg_v_i16m8(op1,31); +} + + +vint32mf2_t test___riscv_vneg_v_i32mf2(vint32mf2_t op1,size_t vl) +{ + return __riscv_vneg_v_i32mf2(op1,31); +} + + +vint32m1_t test___riscv_vneg_v_i32m1(vint32m1_t op1,size_t vl) +{ + return __riscv_vneg_v_i32m1(op1,31); +} + + +vint32m2_t test___riscv_vneg_v_i32m2(vint32m2_t op1,size_t vl) +{ + return __riscv_vneg_v_i32m2(op1,31); +} + + +vint32m4_t test___riscv_vneg_v_i32m4(vint32m4_t op1,size_t vl) +{ + return __riscv_vneg_v_i32m4(op1,31); +} + + +vint32m8_t test___riscv_vneg_v_i32m8(vint32m8_t op1,size_t vl) +{ + return __riscv_vneg_v_i32m8(op1,31); +} + + +vint64m1_t test___riscv_vneg_v_i64m1(vint64m1_t op1,size_t vl) +{ + return __riscv_vneg_v_i64m1(op1,31); +} + + +vint64m2_t test___riscv_vneg_v_i64m2(vint64m2_t op1,size_t vl) +{ + return __riscv_vneg_v_i64m2(op1,31); +} + + +vint64m4_t test___riscv_vneg_v_i64m4(vint64m4_t op1,size_t vl) +{ + return __riscv_vneg_v_i64m4(op1,31); +} + + +vint64m8_t test___riscv_vneg_v_i64m8(vint64m8_t op1,size_t vl) +{ + return __riscv_vneg_v_i64m8(op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v-3.c new file mode 100644 index 00000000000..882e9ffc922 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v-3.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vneg_v_i8mf8(vint8mf8_t op1,size_t vl) +{ + return __riscv_vneg_v_i8mf8(op1,32); +} + + +vint8mf4_t test___riscv_vneg_v_i8mf4(vint8mf4_t op1,size_t vl) +{ + return __riscv_vneg_v_i8mf4(op1,32); +} + + +vint8mf2_t test___riscv_vneg_v_i8mf2(vint8mf2_t op1,size_t vl) +{ + return __riscv_vneg_v_i8mf2(op1,32); +} + + +vint8m1_t test___riscv_vneg_v_i8m1(vint8m1_t op1,size_t vl) +{ + return __riscv_vneg_v_i8m1(op1,32); +} + + +vint8m2_t test___riscv_vneg_v_i8m2(vint8m2_t op1,size_t vl) +{ + return __riscv_vneg_v_i8m2(op1,32); +} + + +vint8m4_t test___riscv_vneg_v_i8m4(vint8m4_t op1,size_t vl) +{ + return __riscv_vneg_v_i8m4(op1,32); +} + + +vint8m8_t test___riscv_vneg_v_i8m8(vint8m8_t op1,size_t vl) +{ + return __riscv_vneg_v_i8m8(op1,32); +} + + +vint16mf4_t test___riscv_vneg_v_i16mf4(vint16mf4_t op1,size_t vl) +{ + return __riscv_vneg_v_i16mf4(op1,32); +} + + +vint16mf2_t test___riscv_vneg_v_i16mf2(vint16mf2_t op1,size_t vl) +{ + return __riscv_vneg_v_i16mf2(op1,32); +} + + +vint16m1_t test___riscv_vneg_v_i16m1(vint16m1_t op1,size_t vl) +{ + return __riscv_vneg_v_i16m1(op1,32); +} + + +vint16m2_t test___riscv_vneg_v_i16m2(vint16m2_t op1,size_t vl) +{ + return __riscv_vneg_v_i16m2(op1,32); +} + + +vint16m4_t test___riscv_vneg_v_i16m4(vint16m4_t op1,size_t vl) +{ + return __riscv_vneg_v_i16m4(op1,32); +} + + +vint16m8_t test___riscv_vneg_v_i16m8(vint16m8_t op1,size_t vl) +{ + return __riscv_vneg_v_i16m8(op1,32); +} + + +vint32mf2_t test___riscv_vneg_v_i32mf2(vint32mf2_t op1,size_t vl) +{ + return __riscv_vneg_v_i32mf2(op1,32); +} + + +vint32m1_t test___riscv_vneg_v_i32m1(vint32m1_t op1,size_t vl) +{ + return __riscv_vneg_v_i32m1(op1,32); +} + + +vint32m2_t test___riscv_vneg_v_i32m2(vint32m2_t op1,size_t vl) +{ + return __riscv_vneg_v_i32m2(op1,32); +} + + +vint32m4_t test___riscv_vneg_v_i32m4(vint32m4_t op1,size_t vl) +{ + return __riscv_vneg_v_i32m4(op1,32); +} + + +vint32m8_t test___riscv_vneg_v_i32m8(vint32m8_t op1,size_t vl) +{ + return __riscv_vneg_v_i32m8(op1,32); +} + + +vint64m1_t test___riscv_vneg_v_i64m1(vint64m1_t op1,size_t vl) +{ + return __riscv_vneg_v_i64m1(op1,32); +} + + +vint64m2_t test___riscv_vneg_v_i64m2(vint64m2_t op1,size_t vl) +{ + return __riscv_vneg_v_i64m2(op1,32); +} + + +vint64m4_t test___riscv_vneg_v_i64m4(vint64m4_t op1,size_t vl) +{ + return __riscv_vneg_v_i64m4(op1,32); +} + + +vint64m8_t test___riscv_vneg_v_i64m8(vint64m8_t op1,size_t vl) +{ + return __riscv_vneg_v_i64m8(op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_m-1.c new file mode 100644 index 00000000000..3af95e1cdd3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_m-1.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vneg_v_i8mf8_m(vbool64_t mask,vint8mf8_t op1,size_t vl) +{ + return __riscv_vneg_v_i8mf8_m(mask,op1,vl); +} + + +vint8mf4_t test___riscv_vneg_v_i8mf4_m(vbool32_t mask,vint8mf4_t op1,size_t vl) +{ + return __riscv_vneg_v_i8mf4_m(mask,op1,vl); +} + + +vint8mf2_t test___riscv_vneg_v_i8mf2_m(vbool16_t mask,vint8mf2_t op1,size_t vl) +{ + return __riscv_vneg_v_i8mf2_m(mask,op1,vl); +} + + +vint8m1_t test___riscv_vneg_v_i8m1_m(vbool8_t mask,vint8m1_t op1,size_t vl) +{ + return __riscv_vneg_v_i8m1_m(mask,op1,vl); +} + + +vint8m2_t test___riscv_vneg_v_i8m2_m(vbool4_t mask,vint8m2_t op1,size_t vl) +{ + return __riscv_vneg_v_i8m2_m(mask,op1,vl); +} + + +vint8m4_t test___riscv_vneg_v_i8m4_m(vbool2_t mask,vint8m4_t op1,size_t vl) +{ + return __riscv_vneg_v_i8m4_m(mask,op1,vl); +} + + +vint8m8_t test___riscv_vneg_v_i8m8_m(vbool1_t mask,vint8m8_t op1,size_t vl) +{ + return __riscv_vneg_v_i8m8_m(mask,op1,vl); +} + + +vint16mf4_t test___riscv_vneg_v_i16mf4_m(vbool64_t mask,vint16mf4_t op1,size_t vl) +{ + return __riscv_vneg_v_i16mf4_m(mask,op1,vl); +} + + +vint16mf2_t test___riscv_vneg_v_i16mf2_m(vbool32_t mask,vint16mf2_t op1,size_t vl) +{ + return __riscv_vneg_v_i16mf2_m(mask,op1,vl); +} + + +vint16m1_t test___riscv_vneg_v_i16m1_m(vbool16_t mask,vint16m1_t op1,size_t vl) +{ + return __riscv_vneg_v_i16m1_m(mask,op1,vl); +} + + +vint16m2_t test___riscv_vneg_v_i16m2_m(vbool8_t mask,vint16m2_t op1,size_t vl) +{ + return __riscv_vneg_v_i16m2_m(mask,op1,vl); +} + + +vint16m4_t test___riscv_vneg_v_i16m4_m(vbool4_t mask,vint16m4_t op1,size_t vl) +{ + return __riscv_vneg_v_i16m4_m(mask,op1,vl); +} + + +vint16m8_t test___riscv_vneg_v_i16m8_m(vbool2_t mask,vint16m8_t op1,size_t vl) +{ + return __riscv_vneg_v_i16m8_m(mask,op1,vl); +} + + +vint32mf2_t test___riscv_vneg_v_i32mf2_m(vbool64_t mask,vint32mf2_t op1,size_t vl) +{ + return __riscv_vneg_v_i32mf2_m(mask,op1,vl); +} + + +vint32m1_t test___riscv_vneg_v_i32m1_m(vbool32_t mask,vint32m1_t op1,size_t vl) +{ + return __riscv_vneg_v_i32m1_m(mask,op1,vl); +} + + +vint32m2_t test___riscv_vneg_v_i32m2_m(vbool16_t mask,vint32m2_t op1,size_t vl) +{ + return __riscv_vneg_v_i32m2_m(mask,op1,vl); +} + + +vint32m4_t test___riscv_vneg_v_i32m4_m(vbool8_t mask,vint32m4_t op1,size_t vl) +{ + return __riscv_vneg_v_i32m4_m(mask,op1,vl); +} + + +vint32m8_t test___riscv_vneg_v_i32m8_m(vbool4_t mask,vint32m8_t op1,size_t vl) +{ + return __riscv_vneg_v_i32m8_m(mask,op1,vl); +} + + +vint64m1_t test___riscv_vneg_v_i64m1_m(vbool64_t mask,vint64m1_t op1,size_t vl) +{ + return __riscv_vneg_v_i64m1_m(mask,op1,vl); +} + + +vint64m2_t test___riscv_vneg_v_i64m2_m(vbool32_t mask,vint64m2_t op1,size_t vl) +{ + return __riscv_vneg_v_i64m2_m(mask,op1,vl); +} + + +vint64m4_t test___riscv_vneg_v_i64m4_m(vbool16_t mask,vint64m4_t op1,size_t vl) +{ + return __riscv_vneg_v_i64m4_m(mask,op1,vl); +} + + +vint64m8_t test___riscv_vneg_v_i64m8_m(vbool8_t mask,vint64m8_t op1,size_t vl) +{ + return __riscv_vneg_v_i64m8_m(mask,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_m-2.c new file mode 100644 index 00000000000..75fd94e48a1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_m-2.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vneg_v_i8mf8_m(vbool64_t mask,vint8mf8_t op1,size_t vl) +{ + return __riscv_vneg_v_i8mf8_m(mask,op1,31); +} + + +vint8mf4_t test___riscv_vneg_v_i8mf4_m(vbool32_t mask,vint8mf4_t op1,size_t vl) +{ + return __riscv_vneg_v_i8mf4_m(mask,op1,31); +} + + +vint8mf2_t test___riscv_vneg_v_i8mf2_m(vbool16_t mask,vint8mf2_t op1,size_t vl) +{ + return __riscv_vneg_v_i8mf2_m(mask,op1,31); +} + + +vint8m1_t test___riscv_vneg_v_i8m1_m(vbool8_t mask,vint8m1_t op1,size_t vl) +{ + return __riscv_vneg_v_i8m1_m(mask,op1,31); +} + + +vint8m2_t test___riscv_vneg_v_i8m2_m(vbool4_t mask,vint8m2_t op1,size_t vl) +{ + return __riscv_vneg_v_i8m2_m(mask,op1,31); +} + + +vint8m4_t test___riscv_vneg_v_i8m4_m(vbool2_t mask,vint8m4_t op1,size_t vl) +{ + return __riscv_vneg_v_i8m4_m(mask,op1,31); +} + + +vint8m8_t test___riscv_vneg_v_i8m8_m(vbool1_t mask,vint8m8_t op1,size_t vl) +{ + return __riscv_vneg_v_i8m8_m(mask,op1,31); +} + + +vint16mf4_t test___riscv_vneg_v_i16mf4_m(vbool64_t mask,vint16mf4_t op1,size_t vl) +{ + return __riscv_vneg_v_i16mf4_m(mask,op1,31); +} + + +vint16mf2_t test___riscv_vneg_v_i16mf2_m(vbool32_t mask,vint16mf2_t op1,size_t vl) +{ + return __riscv_vneg_v_i16mf2_m(mask,op1,31); +} + + +vint16m1_t test___riscv_vneg_v_i16m1_m(vbool16_t mask,vint16m1_t op1,size_t vl) +{ + return __riscv_vneg_v_i16m1_m(mask,op1,31); +} + + +vint16m2_t test___riscv_vneg_v_i16m2_m(vbool8_t mask,vint16m2_t op1,size_t vl) +{ + return __riscv_vneg_v_i16m2_m(mask,op1,31); +} + + +vint16m4_t test___riscv_vneg_v_i16m4_m(vbool4_t mask,vint16m4_t op1,size_t vl) +{ + return __riscv_vneg_v_i16m4_m(mask,op1,31); +} + + +vint16m8_t test___riscv_vneg_v_i16m8_m(vbool2_t mask,vint16m8_t op1,size_t vl) +{ + return __riscv_vneg_v_i16m8_m(mask,op1,31); +} + + +vint32mf2_t test___riscv_vneg_v_i32mf2_m(vbool64_t mask,vint32mf2_t op1,size_t vl) +{ + return __riscv_vneg_v_i32mf2_m(mask,op1,31); +} + + +vint32m1_t test___riscv_vneg_v_i32m1_m(vbool32_t mask,vint32m1_t op1,size_t vl) +{ + return __riscv_vneg_v_i32m1_m(mask,op1,31); +} + + +vint32m2_t test___riscv_vneg_v_i32m2_m(vbool16_t mask,vint32m2_t op1,size_t vl) +{ + return __riscv_vneg_v_i32m2_m(mask,op1,31); +} + + +vint32m4_t test___riscv_vneg_v_i32m4_m(vbool8_t mask,vint32m4_t op1,size_t vl) +{ + return __riscv_vneg_v_i32m4_m(mask,op1,31); +} + + +vint32m8_t test___riscv_vneg_v_i32m8_m(vbool4_t mask,vint32m8_t op1,size_t vl) +{ + return __riscv_vneg_v_i32m8_m(mask,op1,31); +} + + +vint64m1_t test___riscv_vneg_v_i64m1_m(vbool64_t mask,vint64m1_t op1,size_t vl) +{ + return __riscv_vneg_v_i64m1_m(mask,op1,31); +} + + +vint64m2_t test___riscv_vneg_v_i64m2_m(vbool32_t mask,vint64m2_t op1,size_t vl) +{ + return __riscv_vneg_v_i64m2_m(mask,op1,31); +} + + +vint64m4_t test___riscv_vneg_v_i64m4_m(vbool16_t mask,vint64m4_t op1,size_t vl) +{ + return __riscv_vneg_v_i64m4_m(mask,op1,31); +} + + +vint64m8_t test___riscv_vneg_v_i64m8_m(vbool8_t mask,vint64m8_t op1,size_t vl) +{ + return __riscv_vneg_v_i64m8_m(mask,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_m-3.c new file mode 100644 index 00000000000..271f1f37b80 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_m-3.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vneg_v_i8mf8_m(vbool64_t mask,vint8mf8_t op1,size_t vl) +{ + return __riscv_vneg_v_i8mf8_m(mask,op1,32); +} + + +vint8mf4_t test___riscv_vneg_v_i8mf4_m(vbool32_t mask,vint8mf4_t op1,size_t vl) +{ + return __riscv_vneg_v_i8mf4_m(mask,op1,32); +} + + +vint8mf2_t test___riscv_vneg_v_i8mf2_m(vbool16_t mask,vint8mf2_t op1,size_t vl) +{ + return __riscv_vneg_v_i8mf2_m(mask,op1,32); +} + + +vint8m1_t test___riscv_vneg_v_i8m1_m(vbool8_t mask,vint8m1_t op1,size_t vl) +{ + return __riscv_vneg_v_i8m1_m(mask,op1,32); +} + + +vint8m2_t test___riscv_vneg_v_i8m2_m(vbool4_t mask,vint8m2_t op1,size_t vl) +{ + return __riscv_vneg_v_i8m2_m(mask,op1,32); +} + + +vint8m4_t test___riscv_vneg_v_i8m4_m(vbool2_t mask,vint8m4_t op1,size_t vl) +{ + return __riscv_vneg_v_i8m4_m(mask,op1,32); +} + + +vint8m8_t test___riscv_vneg_v_i8m8_m(vbool1_t mask,vint8m8_t op1,size_t vl) +{ + return __riscv_vneg_v_i8m8_m(mask,op1,32); +} + + +vint16mf4_t test___riscv_vneg_v_i16mf4_m(vbool64_t mask,vint16mf4_t op1,size_t vl) +{ + return __riscv_vneg_v_i16mf4_m(mask,op1,32); +} + + +vint16mf2_t test___riscv_vneg_v_i16mf2_m(vbool32_t mask,vint16mf2_t op1,size_t vl) +{ + return __riscv_vneg_v_i16mf2_m(mask,op1,32); +} + + +vint16m1_t test___riscv_vneg_v_i16m1_m(vbool16_t mask,vint16m1_t op1,size_t vl) +{ + return __riscv_vneg_v_i16m1_m(mask,op1,32); +} + + +vint16m2_t test___riscv_vneg_v_i16m2_m(vbool8_t mask,vint16m2_t op1,size_t vl) +{ + return __riscv_vneg_v_i16m2_m(mask,op1,32); +} + + +vint16m4_t test___riscv_vneg_v_i16m4_m(vbool4_t mask,vint16m4_t op1,size_t vl) +{ + return __riscv_vneg_v_i16m4_m(mask,op1,32); +} + + +vint16m8_t test___riscv_vneg_v_i16m8_m(vbool2_t mask,vint16m8_t op1,size_t vl) +{ + return __riscv_vneg_v_i16m8_m(mask,op1,32); +} + + +vint32mf2_t test___riscv_vneg_v_i32mf2_m(vbool64_t mask,vint32mf2_t op1,size_t vl) +{ + return __riscv_vneg_v_i32mf2_m(mask,op1,32); +} + + +vint32m1_t test___riscv_vneg_v_i32m1_m(vbool32_t mask,vint32m1_t op1,size_t vl) +{ + return __riscv_vneg_v_i32m1_m(mask,op1,32); +} + + +vint32m2_t test___riscv_vneg_v_i32m2_m(vbool16_t mask,vint32m2_t op1,size_t vl) +{ + return __riscv_vneg_v_i32m2_m(mask,op1,32); +} + + +vint32m4_t test___riscv_vneg_v_i32m4_m(vbool8_t mask,vint32m4_t op1,size_t vl) +{ + return __riscv_vneg_v_i32m4_m(mask,op1,32); +} + + +vint32m8_t test___riscv_vneg_v_i32m8_m(vbool4_t mask,vint32m8_t op1,size_t vl) +{ + return __riscv_vneg_v_i32m8_m(mask,op1,32); +} + + +vint64m1_t test___riscv_vneg_v_i64m1_m(vbool64_t mask,vint64m1_t op1,size_t vl) +{ + return __riscv_vneg_v_i64m1_m(mask,op1,32); +} + + +vint64m2_t test___riscv_vneg_v_i64m2_m(vbool32_t mask,vint64m2_t op1,size_t vl) +{ + return __riscv_vneg_v_i64m2_m(mask,op1,32); +} + + +vint64m4_t test___riscv_vneg_v_i64m4_m(vbool16_t mask,vint64m4_t op1,size_t vl) +{ + return __riscv_vneg_v_i64m4_m(mask,op1,32); +} + + +vint64m8_t test___riscv_vneg_v_i64m8_m(vbool8_t mask,vint64m8_t op1,size_t vl) +{ + return __riscv_vneg_v_i64m8_m(mask,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_mu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_mu-1.c new file mode 100644 index 00000000000..d19962bfa15 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_mu-1.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vneg_v_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vneg_v_i8mf8_mu(mask,merge,op1,vl); +} + + +vint8mf4_t test___riscv_vneg_v_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vneg_v_i8mf4_mu(mask,merge,op1,vl); +} + + +vint8mf2_t test___riscv_vneg_v_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vneg_v_i8mf2_mu(mask,merge,op1,vl); +} + + +vint8m1_t test___riscv_vneg_v_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vneg_v_i8m1_mu(mask,merge,op1,vl); +} + + +vint8m2_t test___riscv_vneg_v_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vneg_v_i8m2_mu(mask,merge,op1,vl); +} + + +vint8m4_t test___riscv_vneg_v_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t vl) +{ + return __riscv_vneg_v_i8m4_mu(mask,merge,op1,vl); +} + + +vint8m8_t test___riscv_vneg_v_i8m8_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t vl) +{ + return __riscv_vneg_v_i8m8_mu(mask,merge,op1,vl); +} + + +vint16mf4_t test___riscv_vneg_v_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vneg_v_i16mf4_mu(mask,merge,op1,vl); +} + + +vint16mf2_t test___riscv_vneg_v_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vneg_v_i16mf2_mu(mask,merge,op1,vl); +} + + +vint16m1_t test___riscv_vneg_v_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vneg_v_i16m1_mu(mask,merge,op1,vl); +} + + +vint16m2_t test___riscv_vneg_v_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vneg_v_i16m2_mu(mask,merge,op1,vl); +} + + +vint16m4_t test___riscv_vneg_v_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t vl) +{ + return __riscv_vneg_v_i16m4_mu(mask,merge,op1,vl); +} + + +vint16m8_t test___riscv_vneg_v_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t vl) +{ + return __riscv_vneg_v_i16m8_mu(mask,merge,op1,vl); +} + + +vint32mf2_t test___riscv_vneg_v_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t vl) +{ + return __riscv_vneg_v_i32mf2_mu(mask,merge,op1,vl); +} + + +vint32m1_t test___riscv_vneg_v_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t vl) +{ + return __riscv_vneg_v_i32m1_mu(mask,merge,op1,vl); +} + + +vint32m2_t test___riscv_vneg_v_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t vl) +{ + return __riscv_vneg_v_i32m2_mu(mask,merge,op1,vl); +} + + +vint32m4_t test___riscv_vneg_v_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t vl) +{ + return __riscv_vneg_v_i32m4_mu(mask,merge,op1,vl); +} + + +vint32m8_t test___riscv_vneg_v_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t vl) +{ + return __riscv_vneg_v_i32m8_mu(mask,merge,op1,vl); +} + + +vint64m1_t test___riscv_vneg_v_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t vl) +{ + return __riscv_vneg_v_i64m1_mu(mask,merge,op1,vl); +} + + +vint64m2_t test___riscv_vneg_v_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t vl) +{ + return __riscv_vneg_v_i64m2_mu(mask,merge,op1,vl); +} + + +vint64m4_t test___riscv_vneg_v_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t vl) +{ + return __riscv_vneg_v_i64m4_mu(mask,merge,op1,vl); +} + + +vint64m8_t test___riscv_vneg_v_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t vl) +{ + return __riscv_vneg_v_i64m8_mu(mask,merge,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_mu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_mu-2.c new file mode 100644 index 00000000000..e54160b7785 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_mu-2.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vneg_v_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vneg_v_i8mf8_mu(mask,merge,op1,31); +} + + +vint8mf4_t test___riscv_vneg_v_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vneg_v_i8mf4_mu(mask,merge,op1,31); +} + + +vint8mf2_t test___riscv_vneg_v_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vneg_v_i8mf2_mu(mask,merge,op1,31); +} + + +vint8m1_t test___riscv_vneg_v_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vneg_v_i8m1_mu(mask,merge,op1,31); +} + + +vint8m2_t test___riscv_vneg_v_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vneg_v_i8m2_mu(mask,merge,op1,31); +} + + +vint8m4_t test___riscv_vneg_v_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t vl) +{ + return __riscv_vneg_v_i8m4_mu(mask,merge,op1,31); +} + + +vint8m8_t test___riscv_vneg_v_i8m8_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t vl) +{ + return __riscv_vneg_v_i8m8_mu(mask,merge,op1,31); +} + + +vint16mf4_t test___riscv_vneg_v_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vneg_v_i16mf4_mu(mask,merge,op1,31); +} + + +vint16mf2_t test___riscv_vneg_v_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vneg_v_i16mf2_mu(mask,merge,op1,31); +} + + +vint16m1_t test___riscv_vneg_v_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vneg_v_i16m1_mu(mask,merge,op1,31); +} + + +vint16m2_t test___riscv_vneg_v_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vneg_v_i16m2_mu(mask,merge,op1,31); +} + + +vint16m4_t test___riscv_vneg_v_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t vl) +{ + return __riscv_vneg_v_i16m4_mu(mask,merge,op1,31); +} + + +vint16m8_t test___riscv_vneg_v_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t vl) +{ + return __riscv_vneg_v_i16m8_mu(mask,merge,op1,31); +} + + +vint32mf2_t test___riscv_vneg_v_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t vl) +{ + return __riscv_vneg_v_i32mf2_mu(mask,merge,op1,31); +} + + +vint32m1_t test___riscv_vneg_v_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t vl) +{ + return __riscv_vneg_v_i32m1_mu(mask,merge,op1,31); +} + + +vint32m2_t test___riscv_vneg_v_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t vl) +{ + return __riscv_vneg_v_i32m2_mu(mask,merge,op1,31); +} + + +vint32m4_t test___riscv_vneg_v_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t vl) +{ + return __riscv_vneg_v_i32m4_mu(mask,merge,op1,31); +} + + +vint32m8_t test___riscv_vneg_v_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t vl) +{ + return __riscv_vneg_v_i32m8_mu(mask,merge,op1,31); +} + + +vint64m1_t test___riscv_vneg_v_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t vl) +{ + return __riscv_vneg_v_i64m1_mu(mask,merge,op1,31); +} + + +vint64m2_t test___riscv_vneg_v_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t vl) +{ + return __riscv_vneg_v_i64m2_mu(mask,merge,op1,31); +} + + +vint64m4_t test___riscv_vneg_v_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t vl) +{ + return __riscv_vneg_v_i64m4_mu(mask,merge,op1,31); +} + + +vint64m8_t test___riscv_vneg_v_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t vl) +{ + return __riscv_vneg_v_i64m8_mu(mask,merge,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_mu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_mu-3.c new file mode 100644 index 00000000000..5bad6b479d2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_mu-3.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vneg_v_i8mf8_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vneg_v_i8mf8_mu(mask,merge,op1,32); +} + + +vint8mf4_t test___riscv_vneg_v_i8mf4_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vneg_v_i8mf4_mu(mask,merge,op1,32); +} + + +vint8mf2_t test___riscv_vneg_v_i8mf2_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vneg_v_i8mf2_mu(mask,merge,op1,32); +} + + +vint8m1_t test___riscv_vneg_v_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vneg_v_i8m1_mu(mask,merge,op1,32); +} + + +vint8m2_t test___riscv_vneg_v_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vneg_v_i8m2_mu(mask,merge,op1,32); +} + + +vint8m4_t test___riscv_vneg_v_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t vl) +{ + return __riscv_vneg_v_i8m4_mu(mask,merge,op1,32); +} + + +vint8m8_t test___riscv_vneg_v_i8m8_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t vl) +{ + return __riscv_vneg_v_i8m8_mu(mask,merge,op1,32); +} + + +vint16mf4_t test___riscv_vneg_v_i16mf4_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vneg_v_i16mf4_mu(mask,merge,op1,32); +} + + +vint16mf2_t test___riscv_vneg_v_i16mf2_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vneg_v_i16mf2_mu(mask,merge,op1,32); +} + + +vint16m1_t test___riscv_vneg_v_i16m1_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vneg_v_i16m1_mu(mask,merge,op1,32); +} + + +vint16m2_t test___riscv_vneg_v_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vneg_v_i16m2_mu(mask,merge,op1,32); +} + + +vint16m4_t test___riscv_vneg_v_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t vl) +{ + return __riscv_vneg_v_i16m4_mu(mask,merge,op1,32); +} + + +vint16m8_t test___riscv_vneg_v_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t vl) +{ + return __riscv_vneg_v_i16m8_mu(mask,merge,op1,32); +} + + +vint32mf2_t test___riscv_vneg_v_i32mf2_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t vl) +{ + return __riscv_vneg_v_i32mf2_mu(mask,merge,op1,32); +} + + +vint32m1_t test___riscv_vneg_v_i32m1_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t vl) +{ + return __riscv_vneg_v_i32m1_mu(mask,merge,op1,32); +} + + +vint32m2_t test___riscv_vneg_v_i32m2_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t vl) +{ + return __riscv_vneg_v_i32m2_mu(mask,merge,op1,32); +} + + +vint32m4_t test___riscv_vneg_v_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t vl) +{ + return __riscv_vneg_v_i32m4_mu(mask,merge,op1,32); +} + + +vint32m8_t test___riscv_vneg_v_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t vl) +{ + return __riscv_vneg_v_i32m8_mu(mask,merge,op1,32); +} + + +vint64m1_t test___riscv_vneg_v_i64m1_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t vl) +{ + return __riscv_vneg_v_i64m1_mu(mask,merge,op1,32); +} + + +vint64m2_t test___riscv_vneg_v_i64m2_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t vl) +{ + return __riscv_vneg_v_i64m2_mu(mask,merge,op1,32); +} + + +vint64m4_t test___riscv_vneg_v_i64m4_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t vl) +{ + return __riscv_vneg_v_i64m4_mu(mask,merge,op1,32); +} + + +vint64m8_t test___riscv_vneg_v_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t vl) +{ + return __riscv_vneg_v_i64m8_mu(mask,merge,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_tu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_tu-1.c new file mode 100644 index 00000000000..ab238068c26 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_tu-1.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vneg_v_i8mf8_tu(vint8mf8_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vneg_v_i8mf8_tu(merge,op1,vl); +} + + +vint8mf4_t test___riscv_vneg_v_i8mf4_tu(vint8mf4_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vneg_v_i8mf4_tu(merge,op1,vl); +} + + +vint8mf2_t test___riscv_vneg_v_i8mf2_tu(vint8mf2_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vneg_v_i8mf2_tu(merge,op1,vl); +} + + +vint8m1_t test___riscv_vneg_v_i8m1_tu(vint8m1_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vneg_v_i8m1_tu(merge,op1,vl); +} + + +vint8m2_t test___riscv_vneg_v_i8m2_tu(vint8m2_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vneg_v_i8m2_tu(merge,op1,vl); +} + + +vint8m4_t test___riscv_vneg_v_i8m4_tu(vint8m4_t merge,vint8m4_t op1,size_t vl) +{ + return __riscv_vneg_v_i8m4_tu(merge,op1,vl); +} + + +vint8m8_t test___riscv_vneg_v_i8m8_tu(vint8m8_t merge,vint8m8_t op1,size_t vl) +{ + return __riscv_vneg_v_i8m8_tu(merge,op1,vl); +} + + +vint16mf4_t test___riscv_vneg_v_i16mf4_tu(vint16mf4_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vneg_v_i16mf4_tu(merge,op1,vl); +} + + +vint16mf2_t test___riscv_vneg_v_i16mf2_tu(vint16mf2_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vneg_v_i16mf2_tu(merge,op1,vl); +} + + +vint16m1_t test___riscv_vneg_v_i16m1_tu(vint16m1_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vneg_v_i16m1_tu(merge,op1,vl); +} + + +vint16m2_t test___riscv_vneg_v_i16m2_tu(vint16m2_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vneg_v_i16m2_tu(merge,op1,vl); +} + + +vint16m4_t test___riscv_vneg_v_i16m4_tu(vint16m4_t merge,vint16m4_t op1,size_t vl) +{ + return __riscv_vneg_v_i16m4_tu(merge,op1,vl); +} + + +vint16m8_t test___riscv_vneg_v_i16m8_tu(vint16m8_t merge,vint16m8_t op1,size_t vl) +{ + return __riscv_vneg_v_i16m8_tu(merge,op1,vl); +} + + +vint32mf2_t test___riscv_vneg_v_i32mf2_tu(vint32mf2_t merge,vint32mf2_t op1,size_t vl) +{ + return __riscv_vneg_v_i32mf2_tu(merge,op1,vl); +} + + +vint32m1_t test___riscv_vneg_v_i32m1_tu(vint32m1_t merge,vint32m1_t op1,size_t vl) +{ + return __riscv_vneg_v_i32m1_tu(merge,op1,vl); +} + + +vint32m2_t test___riscv_vneg_v_i32m2_tu(vint32m2_t merge,vint32m2_t op1,size_t vl) +{ + return __riscv_vneg_v_i32m2_tu(merge,op1,vl); +} + + +vint32m4_t test___riscv_vneg_v_i32m4_tu(vint32m4_t merge,vint32m4_t op1,size_t vl) +{ + return __riscv_vneg_v_i32m4_tu(merge,op1,vl); +} + + +vint32m8_t test___riscv_vneg_v_i32m8_tu(vint32m8_t merge,vint32m8_t op1,size_t vl) +{ + return __riscv_vneg_v_i32m8_tu(merge,op1,vl); +} + + +vint64m1_t test___riscv_vneg_v_i64m1_tu(vint64m1_t merge,vint64m1_t op1,size_t vl) +{ + return __riscv_vneg_v_i64m1_tu(merge,op1,vl); +} + + +vint64m2_t test___riscv_vneg_v_i64m2_tu(vint64m2_t merge,vint64m2_t op1,size_t vl) +{ + return __riscv_vneg_v_i64m2_tu(merge,op1,vl); +} + + +vint64m4_t test___riscv_vneg_v_i64m4_tu(vint64m4_t merge,vint64m4_t op1,size_t vl) +{ + return __riscv_vneg_v_i64m4_tu(merge,op1,vl); +} + + +vint64m8_t test___riscv_vneg_v_i64m8_tu(vint64m8_t merge,vint64m8_t op1,size_t vl) +{ + return __riscv_vneg_v_i64m8_tu(merge,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_tu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_tu-2.c new file mode 100644 index 00000000000..59d8420c005 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_tu-2.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vneg_v_i8mf8_tu(vint8mf8_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vneg_v_i8mf8_tu(merge,op1,31); +} + + +vint8mf4_t test___riscv_vneg_v_i8mf4_tu(vint8mf4_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vneg_v_i8mf4_tu(merge,op1,31); +} + + +vint8mf2_t test___riscv_vneg_v_i8mf2_tu(vint8mf2_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vneg_v_i8mf2_tu(merge,op1,31); +} + + +vint8m1_t test___riscv_vneg_v_i8m1_tu(vint8m1_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vneg_v_i8m1_tu(merge,op1,31); +} + + +vint8m2_t test___riscv_vneg_v_i8m2_tu(vint8m2_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vneg_v_i8m2_tu(merge,op1,31); +} + + +vint8m4_t test___riscv_vneg_v_i8m4_tu(vint8m4_t merge,vint8m4_t op1,size_t vl) +{ + return __riscv_vneg_v_i8m4_tu(merge,op1,31); +} + + +vint8m8_t test___riscv_vneg_v_i8m8_tu(vint8m8_t merge,vint8m8_t op1,size_t vl) +{ + return __riscv_vneg_v_i8m8_tu(merge,op1,31); +} + + +vint16mf4_t test___riscv_vneg_v_i16mf4_tu(vint16mf4_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vneg_v_i16mf4_tu(merge,op1,31); +} + + +vint16mf2_t test___riscv_vneg_v_i16mf2_tu(vint16mf2_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vneg_v_i16mf2_tu(merge,op1,31); +} + + +vint16m1_t test___riscv_vneg_v_i16m1_tu(vint16m1_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vneg_v_i16m1_tu(merge,op1,31); +} + + +vint16m2_t test___riscv_vneg_v_i16m2_tu(vint16m2_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vneg_v_i16m2_tu(merge,op1,31); +} + + +vint16m4_t test___riscv_vneg_v_i16m4_tu(vint16m4_t merge,vint16m4_t op1,size_t vl) +{ + return __riscv_vneg_v_i16m4_tu(merge,op1,31); +} + + +vint16m8_t test___riscv_vneg_v_i16m8_tu(vint16m8_t merge,vint16m8_t op1,size_t vl) +{ + return __riscv_vneg_v_i16m8_tu(merge,op1,31); +} + + +vint32mf2_t test___riscv_vneg_v_i32mf2_tu(vint32mf2_t merge,vint32mf2_t op1,size_t vl) +{ + return __riscv_vneg_v_i32mf2_tu(merge,op1,31); +} + + +vint32m1_t test___riscv_vneg_v_i32m1_tu(vint32m1_t merge,vint32m1_t op1,size_t vl) +{ + return __riscv_vneg_v_i32m1_tu(merge,op1,31); +} + + +vint32m2_t test___riscv_vneg_v_i32m2_tu(vint32m2_t merge,vint32m2_t op1,size_t vl) +{ + return __riscv_vneg_v_i32m2_tu(merge,op1,31); +} + + +vint32m4_t test___riscv_vneg_v_i32m4_tu(vint32m4_t merge,vint32m4_t op1,size_t vl) +{ + return __riscv_vneg_v_i32m4_tu(merge,op1,31); +} + + +vint32m8_t test___riscv_vneg_v_i32m8_tu(vint32m8_t merge,vint32m8_t op1,size_t vl) +{ + return __riscv_vneg_v_i32m8_tu(merge,op1,31); +} + + +vint64m1_t test___riscv_vneg_v_i64m1_tu(vint64m1_t merge,vint64m1_t op1,size_t vl) +{ + return __riscv_vneg_v_i64m1_tu(merge,op1,31); +} + + +vint64m2_t test___riscv_vneg_v_i64m2_tu(vint64m2_t merge,vint64m2_t op1,size_t vl) +{ + return __riscv_vneg_v_i64m2_tu(merge,op1,31); +} + + +vint64m4_t test___riscv_vneg_v_i64m4_tu(vint64m4_t merge,vint64m4_t op1,size_t vl) +{ + return __riscv_vneg_v_i64m4_tu(merge,op1,31); +} + + +vint64m8_t test___riscv_vneg_v_i64m8_tu(vint64m8_t merge,vint64m8_t op1,size_t vl) +{ + return __riscv_vneg_v_i64m8_tu(merge,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_tu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_tu-3.c new file mode 100644 index 00000000000..0230992d69e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_tu-3.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vneg_v_i8mf8_tu(vint8mf8_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vneg_v_i8mf8_tu(merge,op1,32); +} + + +vint8mf4_t test___riscv_vneg_v_i8mf4_tu(vint8mf4_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vneg_v_i8mf4_tu(merge,op1,32); +} + + +vint8mf2_t test___riscv_vneg_v_i8mf2_tu(vint8mf2_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vneg_v_i8mf2_tu(merge,op1,32); +} + + +vint8m1_t test___riscv_vneg_v_i8m1_tu(vint8m1_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vneg_v_i8m1_tu(merge,op1,32); +} + + +vint8m2_t test___riscv_vneg_v_i8m2_tu(vint8m2_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vneg_v_i8m2_tu(merge,op1,32); +} + + +vint8m4_t test___riscv_vneg_v_i8m4_tu(vint8m4_t merge,vint8m4_t op1,size_t vl) +{ + return __riscv_vneg_v_i8m4_tu(merge,op1,32); +} + + +vint8m8_t test___riscv_vneg_v_i8m8_tu(vint8m8_t merge,vint8m8_t op1,size_t vl) +{ + return __riscv_vneg_v_i8m8_tu(merge,op1,32); +} + + +vint16mf4_t test___riscv_vneg_v_i16mf4_tu(vint16mf4_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vneg_v_i16mf4_tu(merge,op1,32); +} + + +vint16mf2_t test___riscv_vneg_v_i16mf2_tu(vint16mf2_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vneg_v_i16mf2_tu(merge,op1,32); +} + + +vint16m1_t test___riscv_vneg_v_i16m1_tu(vint16m1_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vneg_v_i16m1_tu(merge,op1,32); +} + + +vint16m2_t test___riscv_vneg_v_i16m2_tu(vint16m2_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vneg_v_i16m2_tu(merge,op1,32); +} + + +vint16m4_t test___riscv_vneg_v_i16m4_tu(vint16m4_t merge,vint16m4_t op1,size_t vl) +{ + return __riscv_vneg_v_i16m4_tu(merge,op1,32); +} + + +vint16m8_t test___riscv_vneg_v_i16m8_tu(vint16m8_t merge,vint16m8_t op1,size_t vl) +{ + return __riscv_vneg_v_i16m8_tu(merge,op1,32); +} + + +vint32mf2_t test___riscv_vneg_v_i32mf2_tu(vint32mf2_t merge,vint32mf2_t op1,size_t vl) +{ + return __riscv_vneg_v_i32mf2_tu(merge,op1,32); +} + + +vint32m1_t test___riscv_vneg_v_i32m1_tu(vint32m1_t merge,vint32m1_t op1,size_t vl) +{ + return __riscv_vneg_v_i32m1_tu(merge,op1,32); +} + + +vint32m2_t test___riscv_vneg_v_i32m2_tu(vint32m2_t merge,vint32m2_t op1,size_t vl) +{ + return __riscv_vneg_v_i32m2_tu(merge,op1,32); +} + + +vint32m4_t test___riscv_vneg_v_i32m4_tu(vint32m4_t merge,vint32m4_t op1,size_t vl) +{ + return __riscv_vneg_v_i32m4_tu(merge,op1,32); +} + + +vint32m8_t test___riscv_vneg_v_i32m8_tu(vint32m8_t merge,vint32m8_t op1,size_t vl) +{ + return __riscv_vneg_v_i32m8_tu(merge,op1,32); +} + + +vint64m1_t test___riscv_vneg_v_i64m1_tu(vint64m1_t merge,vint64m1_t op1,size_t vl) +{ + return __riscv_vneg_v_i64m1_tu(merge,op1,32); +} + + +vint64m2_t test___riscv_vneg_v_i64m2_tu(vint64m2_t merge,vint64m2_t op1,size_t vl) +{ + return __riscv_vneg_v_i64m2_tu(merge,op1,32); +} + + +vint64m4_t test___riscv_vneg_v_i64m4_tu(vint64m4_t merge,vint64m4_t op1,size_t vl) +{ + return __riscv_vneg_v_i64m4_tu(merge,op1,32); +} + + +vint64m8_t test___riscv_vneg_v_i64m8_tu(vint64m8_t merge,vint64m8_t op1,size_t vl) +{ + return __riscv_vneg_v_i64m8_tu(merge,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_tum-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_tum-1.c new file mode 100644 index 00000000000..a1491a3feb6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_tum-1.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vneg_v_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vneg_v_i8mf8_tum(mask,merge,op1,vl); +} + + +vint8mf4_t test___riscv_vneg_v_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vneg_v_i8mf4_tum(mask,merge,op1,vl); +} + + +vint8mf2_t test___riscv_vneg_v_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vneg_v_i8mf2_tum(mask,merge,op1,vl); +} + + +vint8m1_t test___riscv_vneg_v_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vneg_v_i8m1_tum(mask,merge,op1,vl); +} + + +vint8m2_t test___riscv_vneg_v_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vneg_v_i8m2_tum(mask,merge,op1,vl); +} + + +vint8m4_t test___riscv_vneg_v_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t vl) +{ + return __riscv_vneg_v_i8m4_tum(mask,merge,op1,vl); +} + + +vint8m8_t test___riscv_vneg_v_i8m8_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t vl) +{ + return __riscv_vneg_v_i8m8_tum(mask,merge,op1,vl); +} + + +vint16mf4_t test___riscv_vneg_v_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vneg_v_i16mf4_tum(mask,merge,op1,vl); +} + + +vint16mf2_t test___riscv_vneg_v_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vneg_v_i16mf2_tum(mask,merge,op1,vl); +} + + +vint16m1_t test___riscv_vneg_v_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vneg_v_i16m1_tum(mask,merge,op1,vl); +} + + +vint16m2_t test___riscv_vneg_v_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vneg_v_i16m2_tum(mask,merge,op1,vl); +} + + +vint16m4_t test___riscv_vneg_v_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t vl) +{ + return __riscv_vneg_v_i16m4_tum(mask,merge,op1,vl); +} + + +vint16m8_t test___riscv_vneg_v_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t vl) +{ + return __riscv_vneg_v_i16m8_tum(mask,merge,op1,vl); +} + + +vint32mf2_t test___riscv_vneg_v_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t vl) +{ + return __riscv_vneg_v_i32mf2_tum(mask,merge,op1,vl); +} + + +vint32m1_t test___riscv_vneg_v_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t vl) +{ + return __riscv_vneg_v_i32m1_tum(mask,merge,op1,vl); +} + + +vint32m2_t test___riscv_vneg_v_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t vl) +{ + return __riscv_vneg_v_i32m2_tum(mask,merge,op1,vl); +} + + +vint32m4_t test___riscv_vneg_v_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t vl) +{ + return __riscv_vneg_v_i32m4_tum(mask,merge,op1,vl); +} + + +vint32m8_t test___riscv_vneg_v_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t vl) +{ + return __riscv_vneg_v_i32m8_tum(mask,merge,op1,vl); +} + + +vint64m1_t test___riscv_vneg_v_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t vl) +{ + return __riscv_vneg_v_i64m1_tum(mask,merge,op1,vl); +} + + +vint64m2_t test___riscv_vneg_v_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t vl) +{ + return __riscv_vneg_v_i64m2_tum(mask,merge,op1,vl); +} + + +vint64m4_t test___riscv_vneg_v_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t vl) +{ + return __riscv_vneg_v_i64m4_tum(mask,merge,op1,vl); +} + + +vint64m8_t test___riscv_vneg_v_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t vl) +{ + return __riscv_vneg_v_i64m8_tum(mask,merge,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_tum-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_tum-2.c new file mode 100644 index 00000000000..c8af1d20ef5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_tum-2.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vneg_v_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vneg_v_i8mf8_tum(mask,merge,op1,31); +} + + +vint8mf4_t test___riscv_vneg_v_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vneg_v_i8mf4_tum(mask,merge,op1,31); +} + + +vint8mf2_t test___riscv_vneg_v_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vneg_v_i8mf2_tum(mask,merge,op1,31); +} + + +vint8m1_t test___riscv_vneg_v_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vneg_v_i8m1_tum(mask,merge,op1,31); +} + + +vint8m2_t test___riscv_vneg_v_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vneg_v_i8m2_tum(mask,merge,op1,31); +} + + +vint8m4_t test___riscv_vneg_v_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t vl) +{ + return __riscv_vneg_v_i8m4_tum(mask,merge,op1,31); +} + + +vint8m8_t test___riscv_vneg_v_i8m8_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t vl) +{ + return __riscv_vneg_v_i8m8_tum(mask,merge,op1,31); +} + + +vint16mf4_t test___riscv_vneg_v_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vneg_v_i16mf4_tum(mask,merge,op1,31); +} + + +vint16mf2_t test___riscv_vneg_v_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vneg_v_i16mf2_tum(mask,merge,op1,31); +} + + +vint16m1_t test___riscv_vneg_v_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vneg_v_i16m1_tum(mask,merge,op1,31); +} + + +vint16m2_t test___riscv_vneg_v_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vneg_v_i16m2_tum(mask,merge,op1,31); +} + + +vint16m4_t test___riscv_vneg_v_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t vl) +{ + return __riscv_vneg_v_i16m4_tum(mask,merge,op1,31); +} + + +vint16m8_t test___riscv_vneg_v_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t vl) +{ + return __riscv_vneg_v_i16m8_tum(mask,merge,op1,31); +} + + +vint32mf2_t test___riscv_vneg_v_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t vl) +{ + return __riscv_vneg_v_i32mf2_tum(mask,merge,op1,31); +} + + +vint32m1_t test___riscv_vneg_v_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t vl) +{ + return __riscv_vneg_v_i32m1_tum(mask,merge,op1,31); +} + + +vint32m2_t test___riscv_vneg_v_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t vl) +{ + return __riscv_vneg_v_i32m2_tum(mask,merge,op1,31); +} + + +vint32m4_t test___riscv_vneg_v_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t vl) +{ + return __riscv_vneg_v_i32m4_tum(mask,merge,op1,31); +} + + +vint32m8_t test___riscv_vneg_v_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t vl) +{ + return __riscv_vneg_v_i32m8_tum(mask,merge,op1,31); +} + + +vint64m1_t test___riscv_vneg_v_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t vl) +{ + return __riscv_vneg_v_i64m1_tum(mask,merge,op1,31); +} + + +vint64m2_t test___riscv_vneg_v_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t vl) +{ + return __riscv_vneg_v_i64m2_tum(mask,merge,op1,31); +} + + +vint64m4_t test___riscv_vneg_v_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t vl) +{ + return __riscv_vneg_v_i64m4_tum(mask,merge,op1,31); +} + + +vint64m8_t test___riscv_vneg_v_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t vl) +{ + return __riscv_vneg_v_i64m8_tum(mask,merge,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_tum-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_tum-3.c new file mode 100644 index 00000000000..a147b6a8acb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_tum-3.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vneg_v_i8mf8_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vneg_v_i8mf8_tum(mask,merge,op1,32); +} + + +vint8mf4_t test___riscv_vneg_v_i8mf4_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vneg_v_i8mf4_tum(mask,merge,op1,32); +} + + +vint8mf2_t test___riscv_vneg_v_i8mf2_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vneg_v_i8mf2_tum(mask,merge,op1,32); +} + + +vint8m1_t test___riscv_vneg_v_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vneg_v_i8m1_tum(mask,merge,op1,32); +} + + +vint8m2_t test___riscv_vneg_v_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vneg_v_i8m2_tum(mask,merge,op1,32); +} + + +vint8m4_t test___riscv_vneg_v_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t vl) +{ + return __riscv_vneg_v_i8m4_tum(mask,merge,op1,32); +} + + +vint8m8_t test___riscv_vneg_v_i8m8_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t vl) +{ + return __riscv_vneg_v_i8m8_tum(mask,merge,op1,32); +} + + +vint16mf4_t test___riscv_vneg_v_i16mf4_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vneg_v_i16mf4_tum(mask,merge,op1,32); +} + + +vint16mf2_t test___riscv_vneg_v_i16mf2_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vneg_v_i16mf2_tum(mask,merge,op1,32); +} + + +vint16m1_t test___riscv_vneg_v_i16m1_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vneg_v_i16m1_tum(mask,merge,op1,32); +} + + +vint16m2_t test___riscv_vneg_v_i16m2_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vneg_v_i16m2_tum(mask,merge,op1,32); +} + + +vint16m4_t test___riscv_vneg_v_i16m4_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t vl) +{ + return __riscv_vneg_v_i16m4_tum(mask,merge,op1,32); +} + + +vint16m8_t test___riscv_vneg_v_i16m8_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t vl) +{ + return __riscv_vneg_v_i16m8_tum(mask,merge,op1,32); +} + + +vint32mf2_t test___riscv_vneg_v_i32mf2_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t vl) +{ + return __riscv_vneg_v_i32mf2_tum(mask,merge,op1,32); +} + + +vint32m1_t test___riscv_vneg_v_i32m1_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t vl) +{ + return __riscv_vneg_v_i32m1_tum(mask,merge,op1,32); +} + + +vint32m2_t test___riscv_vneg_v_i32m2_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t vl) +{ + return __riscv_vneg_v_i32m2_tum(mask,merge,op1,32); +} + + +vint32m4_t test___riscv_vneg_v_i32m4_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t vl) +{ + return __riscv_vneg_v_i32m4_tum(mask,merge,op1,32); +} + + +vint32m8_t test___riscv_vneg_v_i32m8_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t vl) +{ + return __riscv_vneg_v_i32m8_tum(mask,merge,op1,32); +} + + +vint64m1_t test___riscv_vneg_v_i64m1_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t vl) +{ + return __riscv_vneg_v_i64m1_tum(mask,merge,op1,32); +} + + +vint64m2_t test___riscv_vneg_v_i64m2_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t vl) +{ + return __riscv_vneg_v_i64m2_tum(mask,merge,op1,32); +} + + +vint64m4_t test___riscv_vneg_v_i64m4_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t vl) +{ + return __riscv_vneg_v_i64m4_tum(mask,merge,op1,32); +} + + +vint64m8_t test___riscv_vneg_v_i64m8_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t vl) +{ + return __riscv_vneg_v_i64m8_tum(mask,merge,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_tumu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_tumu-1.c new file mode 100644 index 00000000000..07dde9a5a7c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_tumu-1.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vneg_v_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vneg_v_i8mf8_tumu(mask,merge,op1,vl); +} + + +vint8mf4_t test___riscv_vneg_v_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vneg_v_i8mf4_tumu(mask,merge,op1,vl); +} + + +vint8mf2_t test___riscv_vneg_v_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vneg_v_i8mf2_tumu(mask,merge,op1,vl); +} + + +vint8m1_t test___riscv_vneg_v_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vneg_v_i8m1_tumu(mask,merge,op1,vl); +} + + +vint8m2_t test___riscv_vneg_v_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vneg_v_i8m2_tumu(mask,merge,op1,vl); +} + + +vint8m4_t test___riscv_vneg_v_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t vl) +{ + return __riscv_vneg_v_i8m4_tumu(mask,merge,op1,vl); +} + + +vint8m8_t test___riscv_vneg_v_i8m8_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t vl) +{ + return __riscv_vneg_v_i8m8_tumu(mask,merge,op1,vl); +} + + +vint16mf4_t test___riscv_vneg_v_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vneg_v_i16mf4_tumu(mask,merge,op1,vl); +} + + +vint16mf2_t test___riscv_vneg_v_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vneg_v_i16mf2_tumu(mask,merge,op1,vl); +} + + +vint16m1_t test___riscv_vneg_v_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vneg_v_i16m1_tumu(mask,merge,op1,vl); +} + + +vint16m2_t test___riscv_vneg_v_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vneg_v_i16m2_tumu(mask,merge,op1,vl); +} + + +vint16m4_t test___riscv_vneg_v_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t vl) +{ + return __riscv_vneg_v_i16m4_tumu(mask,merge,op1,vl); +} + + +vint16m8_t test___riscv_vneg_v_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t vl) +{ + return __riscv_vneg_v_i16m8_tumu(mask,merge,op1,vl); +} + + +vint32mf2_t test___riscv_vneg_v_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t vl) +{ + return __riscv_vneg_v_i32mf2_tumu(mask,merge,op1,vl); +} + + +vint32m1_t test___riscv_vneg_v_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t vl) +{ + return __riscv_vneg_v_i32m1_tumu(mask,merge,op1,vl); +} + + +vint32m2_t test___riscv_vneg_v_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t vl) +{ + return __riscv_vneg_v_i32m2_tumu(mask,merge,op1,vl); +} + + +vint32m4_t test___riscv_vneg_v_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t vl) +{ + return __riscv_vneg_v_i32m4_tumu(mask,merge,op1,vl); +} + + +vint32m8_t test___riscv_vneg_v_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t vl) +{ + return __riscv_vneg_v_i32m8_tumu(mask,merge,op1,vl); +} + + +vint64m1_t test___riscv_vneg_v_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t vl) +{ + return __riscv_vneg_v_i64m1_tumu(mask,merge,op1,vl); +} + + +vint64m2_t test___riscv_vneg_v_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t vl) +{ + return __riscv_vneg_v_i64m2_tumu(mask,merge,op1,vl); +} + + +vint64m4_t test___riscv_vneg_v_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t vl) +{ + return __riscv_vneg_v_i64m4_tumu(mask,merge,op1,vl); +} + + +vint64m8_t test___riscv_vneg_v_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t vl) +{ + return __riscv_vneg_v_i64m8_tumu(mask,merge,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_tumu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_tumu-2.c new file mode 100644 index 00000000000..f62e8474428 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_tumu-2.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vneg_v_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vneg_v_i8mf8_tumu(mask,merge,op1,31); +} + + +vint8mf4_t test___riscv_vneg_v_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vneg_v_i8mf4_tumu(mask,merge,op1,31); +} + + +vint8mf2_t test___riscv_vneg_v_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vneg_v_i8mf2_tumu(mask,merge,op1,31); +} + + +vint8m1_t test___riscv_vneg_v_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vneg_v_i8m1_tumu(mask,merge,op1,31); +} + + +vint8m2_t test___riscv_vneg_v_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vneg_v_i8m2_tumu(mask,merge,op1,31); +} + + +vint8m4_t test___riscv_vneg_v_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t vl) +{ + return __riscv_vneg_v_i8m4_tumu(mask,merge,op1,31); +} + + +vint8m8_t test___riscv_vneg_v_i8m8_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t vl) +{ + return __riscv_vneg_v_i8m8_tumu(mask,merge,op1,31); +} + + +vint16mf4_t test___riscv_vneg_v_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vneg_v_i16mf4_tumu(mask,merge,op1,31); +} + + +vint16mf2_t test___riscv_vneg_v_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vneg_v_i16mf2_tumu(mask,merge,op1,31); +} + + +vint16m1_t test___riscv_vneg_v_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vneg_v_i16m1_tumu(mask,merge,op1,31); +} + + +vint16m2_t test___riscv_vneg_v_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vneg_v_i16m2_tumu(mask,merge,op1,31); +} + + +vint16m4_t test___riscv_vneg_v_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t vl) +{ + return __riscv_vneg_v_i16m4_tumu(mask,merge,op1,31); +} + + +vint16m8_t test___riscv_vneg_v_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t vl) +{ + return __riscv_vneg_v_i16m8_tumu(mask,merge,op1,31); +} + + +vint32mf2_t test___riscv_vneg_v_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t vl) +{ + return __riscv_vneg_v_i32mf2_tumu(mask,merge,op1,31); +} + + +vint32m1_t test___riscv_vneg_v_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t vl) +{ + return __riscv_vneg_v_i32m1_tumu(mask,merge,op1,31); +} + + +vint32m2_t test___riscv_vneg_v_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t vl) +{ + return __riscv_vneg_v_i32m2_tumu(mask,merge,op1,31); +} + + +vint32m4_t test___riscv_vneg_v_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t vl) +{ + return __riscv_vneg_v_i32m4_tumu(mask,merge,op1,31); +} + + +vint32m8_t test___riscv_vneg_v_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t vl) +{ + return __riscv_vneg_v_i32m8_tumu(mask,merge,op1,31); +} + + +vint64m1_t test___riscv_vneg_v_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t vl) +{ + return __riscv_vneg_v_i64m1_tumu(mask,merge,op1,31); +} + + +vint64m2_t test___riscv_vneg_v_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t vl) +{ + return __riscv_vneg_v_i64m2_tumu(mask,merge,op1,31); +} + + +vint64m4_t test___riscv_vneg_v_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t vl) +{ + return __riscv_vneg_v_i64m4_tumu(mask,merge,op1,31); +} + + +vint64m8_t test___riscv_vneg_v_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t vl) +{ + return __riscv_vneg_v_i64m8_tumu(mask,merge,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_tumu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_tumu-3.c new file mode 100644 index 00000000000..4a9d962e878 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vneg_v_tumu-3.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vneg_v_i8mf8_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,size_t vl) +{ + return __riscv_vneg_v_i8mf8_tumu(mask,merge,op1,32); +} + + +vint8mf4_t test___riscv_vneg_v_i8mf4_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,size_t vl) +{ + return __riscv_vneg_v_i8mf4_tumu(mask,merge,op1,32); +} + + +vint8mf2_t test___riscv_vneg_v_i8mf2_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,size_t vl) +{ + return __riscv_vneg_v_i8mf2_tumu(mask,merge,op1,32); +} + + +vint8m1_t test___riscv_vneg_v_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,size_t vl) +{ + return __riscv_vneg_v_i8m1_tumu(mask,merge,op1,32); +} + + +vint8m2_t test___riscv_vneg_v_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,size_t vl) +{ + return __riscv_vneg_v_i8m2_tumu(mask,merge,op1,32); +} + + +vint8m4_t test___riscv_vneg_v_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,size_t vl) +{ + return __riscv_vneg_v_i8m4_tumu(mask,merge,op1,32); +} + + +vint8m8_t test___riscv_vneg_v_i8m8_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,size_t vl) +{ + return __riscv_vneg_v_i8m8_tumu(mask,merge,op1,32); +} + + +vint16mf4_t test___riscv_vneg_v_i16mf4_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,size_t vl) +{ + return __riscv_vneg_v_i16mf4_tumu(mask,merge,op1,32); +} + + +vint16mf2_t test___riscv_vneg_v_i16mf2_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,size_t vl) +{ + return __riscv_vneg_v_i16mf2_tumu(mask,merge,op1,32); +} + + +vint16m1_t test___riscv_vneg_v_i16m1_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,size_t vl) +{ + return __riscv_vneg_v_i16m1_tumu(mask,merge,op1,32); +} + + +vint16m2_t test___riscv_vneg_v_i16m2_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,size_t vl) +{ + return __riscv_vneg_v_i16m2_tumu(mask,merge,op1,32); +} + + +vint16m4_t test___riscv_vneg_v_i16m4_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,size_t vl) +{ + return __riscv_vneg_v_i16m4_tumu(mask,merge,op1,32); +} + + +vint16m8_t test___riscv_vneg_v_i16m8_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,size_t vl) +{ + return __riscv_vneg_v_i16m8_tumu(mask,merge,op1,32); +} + + +vint32mf2_t test___riscv_vneg_v_i32mf2_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,size_t vl) +{ + return __riscv_vneg_v_i32mf2_tumu(mask,merge,op1,32); +} + + +vint32m1_t test___riscv_vneg_v_i32m1_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,size_t vl) +{ + return __riscv_vneg_v_i32m1_tumu(mask,merge,op1,32); +} + + +vint32m2_t test___riscv_vneg_v_i32m2_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,size_t vl) +{ + return __riscv_vneg_v_i32m2_tumu(mask,merge,op1,32); +} + + +vint32m4_t test___riscv_vneg_v_i32m4_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,size_t vl) +{ + return __riscv_vneg_v_i32m4_tumu(mask,merge,op1,32); +} + + +vint32m8_t test___riscv_vneg_v_i32m8_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,size_t vl) +{ + return __riscv_vneg_v_i32m8_tumu(mask,merge,op1,32); +} + + +vint64m1_t test___riscv_vneg_v_i64m1_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,size_t vl) +{ + return __riscv_vneg_v_i64m1_tumu(mask,merge,op1,32); +} + + +vint64m2_t test___riscv_vneg_v_i64m2_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,size_t vl) +{ + return __riscv_vneg_v_i64m2_tumu(mask,merge,op1,32); +} + + +vint64m4_t test___riscv_vneg_v_i64m4_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,size_t vl) +{ + return __riscv_vneg_v_i64m4_tumu(mask,merge,op1,32); +} + + +vint64m8_t test___riscv_vneg_v_i64m8_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,size_t vl) +{ + return __riscv_vneg_v_i64m8_tumu(mask,merge,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vneg\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ -- 2.36.1