From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtpbgeu2.qq.com (smtpbgeu2.qq.com [18.194.254.142]) by sourceware.org (Postfix) with ESMTPS id F2CC53858D1E for ; Mon, 6 Feb 2023 05:18:42 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org F2CC53858D1E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp83t1675660717tuyr1m24 Received: from server1.localdomain ( [58.60.1.22]) by bizesmtp.qq.com (ESMTP) with id ; Mon, 06 Feb 2023 13:18:37 +0800 (CST) X-QQ-SSF: 01400000000000E0L000000A0000000 X-QQ-FEAT: VpEAAF+twMIuJu8PAaxC08Mg/9MVUDzVHR+NEuD8X4qPrhUvy7D0Nya8yV4XU eL6dEtL8Iq/EjQB2dCNdajgUyK9gGOG1ZCXZ6MY+vFwbTWEOTgUHSGXNQPHZQVqIh0kGqGy UxQvtAhl0+4yxn4I4fpPNr8N9Y9975kfiOIGfNavq/77knHBwdEGOMISjahtv+gyfR68RPc h7VLjFPzyfUHGvviDyLTdjmfXJsnPeih9eb4v6ANVR2RNQcAMALrPKcc2ouE9PfgbfCfATE 5A5Qj6swXC71GXarNT67aIbyu4dNBEA7amshDto7lsS08sHYqMfXmPfZuK+Ed/yyAoMJTKv xnVJ7zK0FmIwrigSQx28T5Gcc2m0c+QjC1FXSBTul2DbcpVHQzTtHBQd41oNHDG4Ij5SaeQ FaG7tYf/OBs= X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: Add vsext constraint tests Date: Mon, 6 Feb 2023 13:18:36 +0800 Message-Id: <20230206051836.225790-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,KAM_SHORT,RCVD_IN_BARRACUDACENTRAL,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_PASS,TXREP,T_SPF_HELO_TEMPERROR autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Ju-Zhe Zhong gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/unop_v_constraint-2.c: New test. --- .../riscv/rvv/base/unop_v_constraint-2.c | 132 ++++++++++++++++++ 1 file changed, 132 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/unop_v_constraint-2.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/unop_v_constraint-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/unop_v_constraint-2.c new file mode 100644 index 00000000000..19f9365b42b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/unop_v_constraint-2.c @@ -0,0 +1,132 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ +#include "riscv_vector.h" + +/* +** f1: +** vsetivli\tzero,4,e32,m1,tu,ma +** vle16\.v\tv[0-9]+,0\([a-x0-9]+\) +** vle16\.v\tv[0-9]+,0\([a-x0-9]+\) +** vsext\.vf2\tv[0-9]+,\s*v[0-9]+ +** vsext\.vf2\tv[0-9]+,\s*v[0-9]+ +** vse32\.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f1 (void * in, void *out) +{ + vint16mf2_t v = __riscv_vle16_v_i16mf2 (in, 4); + vint16mf2_t v2 = __riscv_vle16_v_i16mf2_tu (v, in, 4); + vint32m1_t v3 = __riscv_vsext_vf2_i32m1 (v2, 4); + vint32m1_t v4 = __riscv_vsext_vf2_i32m1_tu (v3, v2, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f2: +** vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma +** vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** vsetivli\tzero,4,e32,m1,ta,ma +** vle16\.v\tv[0-9]+,0\([a-x0-9]+\) +** vsext\.vf2\tv[0-9]+,\s*v[0-9]+ +** vsetvli\tzero,zero,e64,m2,ta,ma +** vsext\.vf2\tv[1-9][0-9]?,\s*v[0-9]+,\s*v0.t +** vse64\.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f2 (void * in, void *out) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint16mf2_t v = __riscv_vle16_v_i16mf2 (in, 4); + vint32m1_t v3 = __riscv_vsext_vf2_i32m1 (v, 4); + vint64m2_t v4 = __riscv_vsext_vf2_i64m2_m (mask, v3, 4); + __riscv_vse64_v_i64m2 (out, v4, 4); +} + +/* +** f3: +** vsetvli\t[a-x0-9]+,zero,e8,mf4,ta,ma +** vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** vsetivli\tzero,4,e32,m1,tu,mu +** vle16\.v\tv[0-9]+,0\([a-x0-9]+\) +** vle16\.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** vsext\.vf2\tv[0-9]+,\s*v[0-9]+ +** vsext\.vf2\tv[1-9][0-9]?,\s*v[0-9]+,\s*v0.t +** vse32.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f3 (void * in, void *out) +{ + vbool32_t mask = *(vbool32_t*)in; + asm volatile ("":::"memory"); + vint16mf2_t v = __riscv_vle16_v_i16mf2 (in, 4); + vint16mf2_t v2 = __riscv_vle16_v_i16mf2_tumu (mask, v, in, 4); + vint32m1_t v3 = __riscv_vsext_vf2_i32m1 (v2, 4); + vint32m1_t v4 = __riscv_vsext_vf2_i32m1_tumu (mask, v3, v2, 4); + __riscv_vse32_v_i32m1 (out, v4, 4); +} + +/* +** f4: +** vsetivli\tzero,4,e16,mf4,tu,ma +** vle8\.v\tv[0-9]+,0\([a-x0-9]+\) +** vle8\.v\tv[0-9]+,0\([a-x0-9]+\) +** vsext\.vf2\tv[0-9]+,\s*v[0-9]+ +** vsext\.vf2\tv[0-9]+,\s*v[0-9]+ +** vse16\.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f4 (void * in, void *out) +{ + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in, 4); + vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tu (v, in, 4); + vint16mf4_t v3 = __riscv_vsext_vf2_i16mf4 (v2, 4); + vint16mf4_t v4 = __riscv_vsext_vf2_i16mf4_tu (v3, v2, 4); + __riscv_vse16_v_i16mf4 (out, v4, 4); +} + +/* +** f5: +** vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma +** vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** vsetivli\tzero,4,e16,mf4,ta,ma +** vle8.v\tv[0-9]+,0\([a-x0-9]+\) +** vsext\.vf2\tv[0-9]+,\s*v[0-9]+ +** vsetvli\tzero,zero,e32,mf2,ta,ma +** vsext\.vf2\tv[1-9][0-9]?,\s*v[0-9]+,\s*v0.t +** vse32.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f5 (void * in, void *out) +{ + vbool64_t mask = *(vbool64_t*)in; + asm volatile ("":::"memory"); + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in, 4); + vint16mf4_t v3 = __riscv_vsext_vf2_i16mf4 (v, 4); + vint32mf2_t v4 = __riscv_vsext_vf2_i32mf2_m (mask, v3, 4); + __riscv_vse32_v_i32mf2 (out, v4, 4); +} + +/* +** f6: +** vsetvli\t[a-x0-9]+,zero,e8,mf8,ta,ma +** vlm.v\tv[0-9]+,0\([a-x0-9]+\) +** vsetivli\tzero,4,e16,mf4,tu,mu +** vle8\.v\tv[0-9]+,0\([a-x0-9]+\) +** vle8.v\tv[0-9]+,0\([a-x0-9]+\),v0.t +** vsext\.vf2\tv[0-9]+,\s*v[0-9]+ +** vsext\.vf2\tv[1-9][0-9]?,\s*v[0-9]+,\s*v0.t +** vse16.v\tv[0-9]+,0\([a-x0-9]+\) +** ret +*/ +void f6 (void * in, void *out) +{ + vbool64_t mask = *(vbool64_t*)in; + asm volatile ("":::"memory"); + vint8mf8_t v = __riscv_vle8_v_i8mf8 (in, 4); + vint8mf8_t v2 = __riscv_vle8_v_i8mf8_tumu (mask, v, in, 4); + vint16mf4_t v3 = __riscv_vsext_vf2_i16mf4 (v2, 4); + vint16mf4_t v4 = __riscv_vsext_vf2_i16mf4_tumu (mask, v3, v2, 4); + __riscv_vse16_v_i16mf4 (out, v4, 4); +} -- 2.36.1