From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtpbgjp3.qq.com (smtpbgjp3.qq.com [54.92.39.34]) by sourceware.org (Postfix) with ESMTPS id A92E33858D1E for ; Tue, 7 Feb 2023 06:53:36 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org A92E33858D1E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp83t1675752811tfqjz2sj Received: from server1.localdomain ( [58.60.1.22]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 07 Feb 2023 14:53:30 +0800 (CST) X-QQ-SSF: 01400000000000E0L000000A0000000 X-QQ-FEAT: R/WWSfudiIFKjat1GaXZnMLJ1X+1GzF/HJCEBC3OOCLBCNiGPJLZmSe6HN9cy b8mwSnAcbjZ7mFlPmtGnyPs4MuFKtAGuERefvlBrsME+yyYi6zn5FdD2DuLR4o0fOMryHym R6wvqdko2PQ8pZdqqKAHnlaIKCanwR3DtSQgdUW+2lNlI8qHr/9lKlJ+SzvM4Kmsxd+8toy zlEeIJtgtXEgcF3NFnk7sM0cpEJhWtlQTPqA3kQrTqj2l7dDJYxA6dKi96O6g+wZh6lF1m8 pv2S/SJJYOFo0XbQREpeRHmlVhk22s9bIsqKO4Xsgs3dJiWO8ppF+e+sChJ+oYn6+TesIao iz9KeOn4+3Lfg7lKo6L7nCJ28/jgd2K1+z2D18xMmYwBsdBH/XiJTF40D/4cg== X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: Add vwadd.w C++ API tests Date: Tue, 7 Feb 2023 14:53:30 +0800 Message-Id: <20230207065330.50802-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,RCVD_IN_BARRACUDACENTRAL,RCVD_IN_DNSWL_NONE,SPF_HELO_PASS,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Ju-Zhe Zhong gcc/testsuite/ChangeLog: * g++.target/riscv/rvv/base/vwadd_wv-1.C: New test. * g++.target/riscv/rvv/base/vwadd_wv-2.C: New test. * g++.target/riscv/rvv/base/vwadd_wv-3.C: New test. * g++.target/riscv/rvv/base/vwadd_wv_mu-1.C: New test. * g++.target/riscv/rvv/base/vwadd_wv_mu-2.C: New test. * g++.target/riscv/rvv/base/vwadd_wv_mu-3.C: New test. * g++.target/riscv/rvv/base/vwadd_wv_tu-1.C: New test. * g++.target/riscv/rvv/base/vwadd_wv_tu-2.C: New test. * g++.target/riscv/rvv/base/vwadd_wv_tu-3.C: New test. * g++.target/riscv/rvv/base/vwadd_wv_tum-1.C: New test. * g++.target/riscv/rvv/base/vwadd_wv_tum-2.C: New test. * g++.target/riscv/rvv/base/vwadd_wv_tum-3.C: New test. * g++.target/riscv/rvv/base/vwadd_wv_tumu-1.C: New test. * g++.target/riscv/rvv/base/vwadd_wv_tumu-2.C: New test. * g++.target/riscv/rvv/base/vwadd_wv_tumu-3.C: New test. * g++.target/riscv/rvv/base/vwadd_wx-1.C: New test. * g++.target/riscv/rvv/base/vwadd_wx-2.C: New test. * g++.target/riscv/rvv/base/vwadd_wx-3.C: New test. * g++.target/riscv/rvv/base/vwadd_wx_mu-1.C: New test. * g++.target/riscv/rvv/base/vwadd_wx_mu-2.C: New test. * g++.target/riscv/rvv/base/vwadd_wx_mu-3.C: New test. * g++.target/riscv/rvv/base/vwadd_wx_tu-1.C: New test. * g++.target/riscv/rvv/base/vwadd_wx_tu-2.C: New test. * g++.target/riscv/rvv/base/vwadd_wx_tu-3.C: New test. * g++.target/riscv/rvv/base/vwadd_wx_tum-1.C: New test. * g++.target/riscv/rvv/base/vwadd_wx_tum-2.C: New test. * g++.target/riscv/rvv/base/vwadd_wx_tum-3.C: New test. * g++.target/riscv/rvv/base/vwadd_wx_tumu-1.C: New test. * g++.target/riscv/rvv/base/vwadd_wx_tumu-2.C: New test. * g++.target/riscv/rvv/base/vwadd_wx_tumu-3.C: New test. --- .../g++.target/riscv/rvv/base/vwadd_wv-1.C | 216 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vwadd_wv-2.C | 216 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vwadd_wv-3.C | 216 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vwadd_wv_mu-1.C | 111 +++++++++ .../g++.target/riscv/rvv/base/vwadd_wv_mu-2.C | 111 +++++++++ .../g++.target/riscv/rvv/base/vwadd_wv_mu-3.C | 111 +++++++++ .../g++.target/riscv/rvv/base/vwadd_wv_tu-1.C | 111 +++++++++ .../g++.target/riscv/rvv/base/vwadd_wv_tu-2.C | 111 +++++++++ .../g++.target/riscv/rvv/base/vwadd_wv_tu-3.C | 111 +++++++++ .../riscv/rvv/base/vwadd_wv_tum-1.C | 111 +++++++++ .../riscv/rvv/base/vwadd_wv_tum-2.C | 111 +++++++++ .../riscv/rvv/base/vwadd_wv_tum-3.C | 111 +++++++++ .../riscv/rvv/base/vwadd_wv_tumu-1.C | 111 +++++++++ .../riscv/rvv/base/vwadd_wv_tumu-2.C | 111 +++++++++ .../riscv/rvv/base/vwadd_wv_tumu-3.C | 111 +++++++++ .../g++.target/riscv/rvv/base/vwadd_wx-1.C | 216 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vwadd_wx-2.C | 216 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vwadd_wx-3.C | 216 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vwadd_wx_mu-1.C | 111 +++++++++ .../g++.target/riscv/rvv/base/vwadd_wx_mu-2.C | 111 +++++++++ .../g++.target/riscv/rvv/base/vwadd_wx_mu-3.C | 111 +++++++++ .../g++.target/riscv/rvv/base/vwadd_wx_tu-1.C | 111 +++++++++ .../g++.target/riscv/rvv/base/vwadd_wx_tu-2.C | 111 +++++++++ .../g++.target/riscv/rvv/base/vwadd_wx_tu-3.C | 111 +++++++++ .../riscv/rvv/base/vwadd_wx_tum-1.C | 111 +++++++++ .../riscv/rvv/base/vwadd_wx_tum-2.C | 111 +++++++++ .../riscv/rvv/base/vwadd_wx_tum-3.C | 111 +++++++++ .../riscv/rvv/base/vwadd_wx_tumu-1.C | 111 +++++++++ .../riscv/rvv/base/vwadd_wx_tumu-2.C | 111 +++++++++ .../riscv/rvv/base/vwadd_wx_tumu-3.C | 111 +++++++++ 30 files changed, 3960 insertions(+) create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx_tumu-3.C diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv-1.C new file mode 100644 index 00000000000..d4789dc4c70 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv-1.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwadd_wv(vint16mf4_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwadd_wv(op1,op2,vl); +} + + +vint16mf2_t test___riscv_vwadd_wv(vint16mf2_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwadd_wv(op1,op2,vl); +} + + +vint16m1_t test___riscv_vwadd_wv(vint16m1_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwadd_wv(op1,op2,vl); +} + + +vint16m2_t test___riscv_vwadd_wv(vint16m2_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwadd_wv(op1,op2,vl); +} + + +vint16m4_t test___riscv_vwadd_wv(vint16m4_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwadd_wv(op1,op2,vl); +} + + +vint16m8_t test___riscv_vwadd_wv(vint16m8_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwadd_wv(op1,op2,vl); +} + + +vint32mf2_t test___riscv_vwadd_wv(vint32mf2_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwadd_wv(op1,op2,vl); +} + + +vint32m1_t test___riscv_vwadd_wv(vint32m1_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwadd_wv(op1,op2,vl); +} + + +vint32m2_t test___riscv_vwadd_wv(vint32m2_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwadd_wv(op1,op2,vl); +} + + +vint32m4_t test___riscv_vwadd_wv(vint32m4_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwadd_wv(op1,op2,vl); +} + + +vint32m8_t test___riscv_vwadd_wv(vint32m8_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwadd_wv(op1,op2,vl); +} + + +vint64m1_t test___riscv_vwadd_wv(vint64m1_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwadd_wv(op1,op2,vl); +} + + +vint64m2_t test___riscv_vwadd_wv(vint64m2_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwadd_wv(op1,op2,vl); +} + + +vint64m4_t test___riscv_vwadd_wv(vint64m4_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwadd_wv(op1,op2,vl); +} + + +vint64m8_t test___riscv_vwadd_wv(vint64m8_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwadd_wv(op1,op2,vl); +} + + +vint16mf4_t test___riscv_vwadd_wv(vbool64_t mask,vint16mf4_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwadd_wv(mask,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vwadd_wv(vbool32_t mask,vint16mf2_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwadd_wv(mask,op1,op2,vl); +} + + +vint16m1_t test___riscv_vwadd_wv(vbool16_t mask,vint16m1_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwadd_wv(mask,op1,op2,vl); +} + + +vint16m2_t test___riscv_vwadd_wv(vbool8_t mask,vint16m2_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwadd_wv(mask,op1,op2,vl); +} + + +vint16m4_t test___riscv_vwadd_wv(vbool4_t mask,vint16m4_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwadd_wv(mask,op1,op2,vl); +} + + +vint16m8_t test___riscv_vwadd_wv(vbool2_t mask,vint16m8_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwadd_wv(mask,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vwadd_wv(vbool64_t mask,vint32mf2_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwadd_wv(mask,op1,op2,vl); +} + + +vint32m1_t test___riscv_vwadd_wv(vbool32_t mask,vint32m1_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwadd_wv(mask,op1,op2,vl); +} + + +vint32m2_t test___riscv_vwadd_wv(vbool16_t mask,vint32m2_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwadd_wv(mask,op1,op2,vl); +} + + +vint32m4_t test___riscv_vwadd_wv(vbool8_t mask,vint32m4_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwadd_wv(mask,op1,op2,vl); +} + + +vint32m8_t test___riscv_vwadd_wv(vbool4_t mask,vint32m8_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwadd_wv(mask,op1,op2,vl); +} + + +vint64m1_t test___riscv_vwadd_wv(vbool64_t mask,vint64m1_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwadd_wv(mask,op1,op2,vl); +} + + +vint64m2_t test___riscv_vwadd_wv(vbool32_t mask,vint64m2_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwadd_wv(mask,op1,op2,vl); +} + + +vint64m4_t test___riscv_vwadd_wv(vbool16_t mask,vint64m4_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwadd_wv(mask,op1,op2,vl); +} + + +vint64m8_t test___riscv_vwadd_wv(vbool8_t mask,vint64m8_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwadd_wv(mask,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv-2.C new file mode 100644 index 00000000000..b900041e174 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv-2.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwadd_wv(vint16mf4_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwadd_wv(op1,op2,31); +} + + +vint16mf2_t test___riscv_vwadd_wv(vint16mf2_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwadd_wv(op1,op2,31); +} + + +vint16m1_t test___riscv_vwadd_wv(vint16m1_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwadd_wv(op1,op2,31); +} + + +vint16m2_t test___riscv_vwadd_wv(vint16m2_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwadd_wv(op1,op2,31); +} + + +vint16m4_t test___riscv_vwadd_wv(vint16m4_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwadd_wv(op1,op2,31); +} + + +vint16m8_t test___riscv_vwadd_wv(vint16m8_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwadd_wv(op1,op2,31); +} + + +vint32mf2_t test___riscv_vwadd_wv(vint32mf2_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwadd_wv(op1,op2,31); +} + + +vint32m1_t test___riscv_vwadd_wv(vint32m1_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwadd_wv(op1,op2,31); +} + + +vint32m2_t test___riscv_vwadd_wv(vint32m2_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwadd_wv(op1,op2,31); +} + + +vint32m4_t test___riscv_vwadd_wv(vint32m4_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwadd_wv(op1,op2,31); +} + + +vint32m8_t test___riscv_vwadd_wv(vint32m8_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwadd_wv(op1,op2,31); +} + + +vint64m1_t test___riscv_vwadd_wv(vint64m1_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwadd_wv(op1,op2,31); +} + + +vint64m2_t test___riscv_vwadd_wv(vint64m2_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwadd_wv(op1,op2,31); +} + + +vint64m4_t test___riscv_vwadd_wv(vint64m4_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwadd_wv(op1,op2,31); +} + + +vint64m8_t test___riscv_vwadd_wv(vint64m8_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwadd_wv(op1,op2,31); +} + + +vint16mf4_t test___riscv_vwadd_wv(vbool64_t mask,vint16mf4_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwadd_wv(mask,op1,op2,31); +} + + +vint16mf2_t test___riscv_vwadd_wv(vbool32_t mask,vint16mf2_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwadd_wv(mask,op1,op2,31); +} + + +vint16m1_t test___riscv_vwadd_wv(vbool16_t mask,vint16m1_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwadd_wv(mask,op1,op2,31); +} + + +vint16m2_t test___riscv_vwadd_wv(vbool8_t mask,vint16m2_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwadd_wv(mask,op1,op2,31); +} + + +vint16m4_t test___riscv_vwadd_wv(vbool4_t mask,vint16m4_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwadd_wv(mask,op1,op2,31); +} + + +vint16m8_t test___riscv_vwadd_wv(vbool2_t mask,vint16m8_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwadd_wv(mask,op1,op2,31); +} + + +vint32mf2_t test___riscv_vwadd_wv(vbool64_t mask,vint32mf2_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwadd_wv(mask,op1,op2,31); +} + + +vint32m1_t test___riscv_vwadd_wv(vbool32_t mask,vint32m1_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwadd_wv(mask,op1,op2,31); +} + + +vint32m2_t test___riscv_vwadd_wv(vbool16_t mask,vint32m2_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwadd_wv(mask,op1,op2,31); +} + + +vint32m4_t test___riscv_vwadd_wv(vbool8_t mask,vint32m4_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwadd_wv(mask,op1,op2,31); +} + + +vint32m8_t test___riscv_vwadd_wv(vbool4_t mask,vint32m8_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwadd_wv(mask,op1,op2,31); +} + + +vint64m1_t test___riscv_vwadd_wv(vbool64_t mask,vint64m1_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwadd_wv(mask,op1,op2,31); +} + + +vint64m2_t test___riscv_vwadd_wv(vbool32_t mask,vint64m2_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwadd_wv(mask,op1,op2,31); +} + + +vint64m4_t test___riscv_vwadd_wv(vbool16_t mask,vint64m4_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwadd_wv(mask,op1,op2,31); +} + + +vint64m8_t test___riscv_vwadd_wv(vbool8_t mask,vint64m8_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwadd_wv(mask,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv-3.C new file mode 100644 index 00000000000..75eed0bd3fe --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv-3.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwadd_wv(vint16mf4_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwadd_wv(op1,op2,32); +} + + +vint16mf2_t test___riscv_vwadd_wv(vint16mf2_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwadd_wv(op1,op2,32); +} + + +vint16m1_t test___riscv_vwadd_wv(vint16m1_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwadd_wv(op1,op2,32); +} + + +vint16m2_t test___riscv_vwadd_wv(vint16m2_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwadd_wv(op1,op2,32); +} + + +vint16m4_t test___riscv_vwadd_wv(vint16m4_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwadd_wv(op1,op2,32); +} + + +vint16m8_t test___riscv_vwadd_wv(vint16m8_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwadd_wv(op1,op2,32); +} + + +vint32mf2_t test___riscv_vwadd_wv(vint32mf2_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwadd_wv(op1,op2,32); +} + + +vint32m1_t test___riscv_vwadd_wv(vint32m1_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwadd_wv(op1,op2,32); +} + + +vint32m2_t test___riscv_vwadd_wv(vint32m2_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwadd_wv(op1,op2,32); +} + + +vint32m4_t test___riscv_vwadd_wv(vint32m4_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwadd_wv(op1,op2,32); +} + + +vint32m8_t test___riscv_vwadd_wv(vint32m8_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwadd_wv(op1,op2,32); +} + + +vint64m1_t test___riscv_vwadd_wv(vint64m1_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwadd_wv(op1,op2,32); +} + + +vint64m2_t test___riscv_vwadd_wv(vint64m2_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwadd_wv(op1,op2,32); +} + + +vint64m4_t test___riscv_vwadd_wv(vint64m4_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwadd_wv(op1,op2,32); +} + + +vint64m8_t test___riscv_vwadd_wv(vint64m8_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwadd_wv(op1,op2,32); +} + + +vint16mf4_t test___riscv_vwadd_wv(vbool64_t mask,vint16mf4_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwadd_wv(mask,op1,op2,32); +} + + +vint16mf2_t test___riscv_vwadd_wv(vbool32_t mask,vint16mf2_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwadd_wv(mask,op1,op2,32); +} + + +vint16m1_t test___riscv_vwadd_wv(vbool16_t mask,vint16m1_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwadd_wv(mask,op1,op2,32); +} + + +vint16m2_t test___riscv_vwadd_wv(vbool8_t mask,vint16m2_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwadd_wv(mask,op1,op2,32); +} + + +vint16m4_t test___riscv_vwadd_wv(vbool4_t mask,vint16m4_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwadd_wv(mask,op1,op2,32); +} + + +vint16m8_t test___riscv_vwadd_wv(vbool2_t mask,vint16m8_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwadd_wv(mask,op1,op2,32); +} + + +vint32mf2_t test___riscv_vwadd_wv(vbool64_t mask,vint32mf2_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwadd_wv(mask,op1,op2,32); +} + + +vint32m1_t test___riscv_vwadd_wv(vbool32_t mask,vint32m1_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwadd_wv(mask,op1,op2,32); +} + + +vint32m2_t test___riscv_vwadd_wv(vbool16_t mask,vint32m2_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwadd_wv(mask,op1,op2,32); +} + + +vint32m4_t test___riscv_vwadd_wv(vbool8_t mask,vint32m4_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwadd_wv(mask,op1,op2,32); +} + + +vint32m8_t test___riscv_vwadd_wv(vbool4_t mask,vint32m8_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwadd_wv(mask,op1,op2,32); +} + + +vint64m1_t test___riscv_vwadd_wv(vbool64_t mask,vint64m1_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwadd_wv(mask,op1,op2,32); +} + + +vint64m2_t test___riscv_vwadd_wv(vbool32_t mask,vint64m2_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwadd_wv(mask,op1,op2,32); +} + + +vint64m4_t test___riscv_vwadd_wv(vbool16_t mask,vint64m4_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwadd_wv(mask,op1,op2,32); +} + + +vint64m8_t test___riscv_vwadd_wv(vbool8_t mask,vint64m8_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwadd_wv(mask,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv_mu-1.C new file mode 100644 index 00000000000..8b85281bf9c --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv_mu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwadd_wv_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwadd_wv_mu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vwadd_wv_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwadd_wv_mu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vwadd_wv_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwadd_wv_mu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vwadd_wv_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwadd_wv_mu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vwadd_wv_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwadd_wv_mu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vwadd_wv_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwadd_wv_mu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vwadd_wv_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwadd_wv_mu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vwadd_wv_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwadd_wv_mu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vwadd_wv_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwadd_wv_mu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vwadd_wv_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwadd_wv_mu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vwadd_wv_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwadd_wv_mu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vwadd_wv_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwadd_wv_mu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vwadd_wv_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwadd_wv_mu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vwadd_wv_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwadd_wv_mu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vwadd_wv_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwadd_wv_mu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv_mu-2.C new file mode 100644 index 00000000000..8fe88aaacf3 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv_mu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwadd_wv_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwadd_wv_mu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vwadd_wv_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwadd_wv_mu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vwadd_wv_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwadd_wv_mu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vwadd_wv_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwadd_wv_mu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vwadd_wv_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwadd_wv_mu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vwadd_wv_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwadd_wv_mu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vwadd_wv_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwadd_wv_mu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vwadd_wv_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwadd_wv_mu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vwadd_wv_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwadd_wv_mu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vwadd_wv_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwadd_wv_mu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vwadd_wv_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwadd_wv_mu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vwadd_wv_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwadd_wv_mu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vwadd_wv_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwadd_wv_mu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vwadd_wv_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwadd_wv_mu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vwadd_wv_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwadd_wv_mu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv_mu-3.C new file mode 100644 index 00000000000..41e6fde26cb --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv_mu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwadd_wv_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwadd_wv_mu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vwadd_wv_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwadd_wv_mu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vwadd_wv_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwadd_wv_mu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vwadd_wv_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwadd_wv_mu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vwadd_wv_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwadd_wv_mu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vwadd_wv_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwadd_wv_mu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vwadd_wv_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwadd_wv_mu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vwadd_wv_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwadd_wv_mu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vwadd_wv_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwadd_wv_mu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vwadd_wv_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwadd_wv_mu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vwadd_wv_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwadd_wv_mu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vwadd_wv_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwadd_wv_mu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vwadd_wv_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwadd_wv_mu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vwadd_wv_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwadd_wv_mu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vwadd_wv_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwadd_wv_mu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv_tu-1.C new file mode 100644 index 00000000000..aaeef67f864 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv_tu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwadd_wv_tu(vint16mf4_t merge,vint16mf4_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tu(merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vwadd_wv_tu(vint16mf2_t merge,vint16mf2_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tu(merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vwadd_wv_tu(vint16m1_t merge,vint16m1_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tu(merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vwadd_wv_tu(vint16m2_t merge,vint16m2_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tu(merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vwadd_wv_tu(vint16m4_t merge,vint16m4_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tu(merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vwadd_wv_tu(vint16m8_t merge,vint16m8_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tu(merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vwadd_wv_tu(vint32mf2_t merge,vint32mf2_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tu(merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vwadd_wv_tu(vint32m1_t merge,vint32m1_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tu(merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vwadd_wv_tu(vint32m2_t merge,vint32m2_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tu(merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vwadd_wv_tu(vint32m4_t merge,vint32m4_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tu(merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vwadd_wv_tu(vint32m8_t merge,vint32m8_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tu(merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vwadd_wv_tu(vint64m1_t merge,vint64m1_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tu(merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vwadd_wv_tu(vint64m2_t merge,vint64m2_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tu(merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vwadd_wv_tu(vint64m4_t merge,vint64m4_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tu(merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vwadd_wv_tu(vint64m8_t merge,vint64m8_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tu(merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv_tu-2.C new file mode 100644 index 00000000000..adc01a0a2dd --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv_tu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwadd_wv_tu(vint16mf4_t merge,vint16mf4_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tu(merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vwadd_wv_tu(vint16mf2_t merge,vint16mf2_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tu(merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vwadd_wv_tu(vint16m1_t merge,vint16m1_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tu(merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vwadd_wv_tu(vint16m2_t merge,vint16m2_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tu(merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vwadd_wv_tu(vint16m4_t merge,vint16m4_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tu(merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vwadd_wv_tu(vint16m8_t merge,vint16m8_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tu(merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vwadd_wv_tu(vint32mf2_t merge,vint32mf2_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tu(merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vwadd_wv_tu(vint32m1_t merge,vint32m1_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tu(merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vwadd_wv_tu(vint32m2_t merge,vint32m2_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tu(merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vwadd_wv_tu(vint32m4_t merge,vint32m4_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tu(merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vwadd_wv_tu(vint32m8_t merge,vint32m8_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tu(merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vwadd_wv_tu(vint64m1_t merge,vint64m1_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tu(merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vwadd_wv_tu(vint64m2_t merge,vint64m2_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tu(merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vwadd_wv_tu(vint64m4_t merge,vint64m4_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tu(merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vwadd_wv_tu(vint64m8_t merge,vint64m8_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tu(merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv_tu-3.C new file mode 100644 index 00000000000..9152b96ba4e --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv_tu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwadd_wv_tu(vint16mf4_t merge,vint16mf4_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tu(merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vwadd_wv_tu(vint16mf2_t merge,vint16mf2_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tu(merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vwadd_wv_tu(vint16m1_t merge,vint16m1_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tu(merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vwadd_wv_tu(vint16m2_t merge,vint16m2_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tu(merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vwadd_wv_tu(vint16m4_t merge,vint16m4_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tu(merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vwadd_wv_tu(vint16m8_t merge,vint16m8_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tu(merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vwadd_wv_tu(vint32mf2_t merge,vint32mf2_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tu(merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vwadd_wv_tu(vint32m1_t merge,vint32m1_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tu(merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vwadd_wv_tu(vint32m2_t merge,vint32m2_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tu(merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vwadd_wv_tu(vint32m4_t merge,vint32m4_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tu(merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vwadd_wv_tu(vint32m8_t merge,vint32m8_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tu(merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vwadd_wv_tu(vint64m1_t merge,vint64m1_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tu(merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vwadd_wv_tu(vint64m2_t merge,vint64m2_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tu(merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vwadd_wv_tu(vint64m4_t merge,vint64m4_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tu(merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vwadd_wv_tu(vint64m8_t merge,vint64m8_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tu(merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv_tum-1.C new file mode 100644 index 00000000000..db2fe034939 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv_tum-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwadd_wv_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tum(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vwadd_wv_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tum(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vwadd_wv_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tum(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vwadd_wv_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tum(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vwadd_wv_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tum(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vwadd_wv_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tum(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vwadd_wv_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tum(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vwadd_wv_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tum(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vwadd_wv_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tum(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vwadd_wv_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tum(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vwadd_wv_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tum(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vwadd_wv_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tum(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vwadd_wv_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tum(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vwadd_wv_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tum(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vwadd_wv_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tum(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv_tum-2.C new file mode 100644 index 00000000000..ed7ad4ee17c --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv_tum-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwadd_wv_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tum(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vwadd_wv_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tum(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vwadd_wv_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tum(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vwadd_wv_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tum(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vwadd_wv_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tum(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vwadd_wv_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tum(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vwadd_wv_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tum(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vwadd_wv_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tum(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vwadd_wv_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tum(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vwadd_wv_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tum(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vwadd_wv_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tum(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vwadd_wv_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tum(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vwadd_wv_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tum(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vwadd_wv_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tum(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vwadd_wv_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tum(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv_tum-3.C new file mode 100644 index 00000000000..d4e7dd3923c --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv_tum-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwadd_wv_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tum(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vwadd_wv_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tum(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vwadd_wv_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tum(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vwadd_wv_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tum(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vwadd_wv_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tum(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vwadd_wv_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tum(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vwadd_wv_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tum(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vwadd_wv_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tum(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vwadd_wv_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tum(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vwadd_wv_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tum(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vwadd_wv_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tum(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vwadd_wv_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tum(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vwadd_wv_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tum(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vwadd_wv_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tum(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vwadd_wv_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tum(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv_tumu-1.C new file mode 100644 index 00000000000..3d68e06e4ac --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv_tumu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwadd_wv_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tumu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vwadd_wv_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tumu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vwadd_wv_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tumu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vwadd_wv_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tumu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vwadd_wv_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tumu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vwadd_wv_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tumu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vwadd_wv_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tumu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vwadd_wv_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tumu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vwadd_wv_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tumu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vwadd_wv_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tumu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vwadd_wv_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tumu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vwadd_wv_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tumu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vwadd_wv_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tumu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vwadd_wv_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tumu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vwadd_wv_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tumu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv_tumu-2.C new file mode 100644 index 00000000000..494beffb6c4 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv_tumu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwadd_wv_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tumu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vwadd_wv_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tumu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vwadd_wv_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tumu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vwadd_wv_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tumu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vwadd_wv_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tumu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vwadd_wv_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tumu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vwadd_wv_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tumu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vwadd_wv_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tumu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vwadd_wv_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tumu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vwadd_wv_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tumu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vwadd_wv_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tumu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vwadd_wv_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tumu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vwadd_wv_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tumu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vwadd_wv_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tumu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vwadd_wv_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tumu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv_tumu-3.C new file mode 100644 index 00000000000..3b6d36ba5f4 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wv_tumu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwadd_wv_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tumu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vwadd_wv_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tumu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vwadd_wv_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tumu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vwadd_wv_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tumu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vwadd_wv_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tumu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vwadd_wv_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tumu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vwadd_wv_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tumu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vwadd_wv_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tumu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vwadd_wv_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tumu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vwadd_wv_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tumu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vwadd_wv_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tumu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vwadd_wv_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tumu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vwadd_wv_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tumu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vwadd_wv_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tumu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vwadd_wv_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwadd_wv_tumu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwadd\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx-1.C new file mode 100644 index 00000000000..1351b7abe67 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx-1.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwadd_wx(vint16mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx(op1,0xAA,vl); +} + + +vint16mf2_t test___riscv_vwadd_wx(vint16mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx(op1,0xAA,vl); +} + + +vint16m1_t test___riscv_vwadd_wx(vint16m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx(op1,0xAA,vl); +} + + +vint16m2_t test___riscv_vwadd_wx(vint16m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx(op1,0xAA,vl); +} + + +vint16m4_t test___riscv_vwadd_wx(vint16m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx(op1,0xAA,vl); +} + + +vint16m8_t test___riscv_vwadd_wx(vint16m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx(op1,0xAA,vl); +} + + +vint32mf2_t test___riscv_vwadd_wx(vint32mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx(op1,0xAA,vl); +} + + +vint32m1_t test___riscv_vwadd_wx(vint32m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx(op1,0xAA,vl); +} + + +vint32m2_t test___riscv_vwadd_wx(vint32m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx(op1,0xAA,vl); +} + + +vint32m4_t test___riscv_vwadd_wx(vint32m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx(op1,0xAA,vl); +} + + +vint32m8_t test___riscv_vwadd_wx(vint32m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx(op1,0xAA,vl); +} + + +vint64m1_t test___riscv_vwadd_wx(vint64m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_wx(op1,0xAA,vl); +} + + +vint64m2_t test___riscv_vwadd_wx(vint64m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_wx(op1,0xAA,vl); +} + + +vint64m4_t test___riscv_vwadd_wx(vint64m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_wx(op1,0xAA,vl); +} + + +vint64m8_t test___riscv_vwadd_wx(vint64m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_wx(op1,0xAA,vl); +} + + +vint16mf4_t test___riscv_vwadd_wx(vbool64_t mask,vint16mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx(mask,op1,0xAA,vl); +} + + +vint16mf2_t test___riscv_vwadd_wx(vbool32_t mask,vint16mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx(mask,op1,0xAA,vl); +} + + +vint16m1_t test___riscv_vwadd_wx(vbool16_t mask,vint16m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx(mask,op1,0xAA,vl); +} + + +vint16m2_t test___riscv_vwadd_wx(vbool8_t mask,vint16m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx(mask,op1,0xAA,vl); +} + + +vint16m4_t test___riscv_vwadd_wx(vbool4_t mask,vint16m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx(mask,op1,0xAA,vl); +} + + +vint16m8_t test___riscv_vwadd_wx(vbool2_t mask,vint16m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx(mask,op1,0xAA,vl); +} + + +vint32mf2_t test___riscv_vwadd_wx(vbool64_t mask,vint32mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx(mask,op1,0xAA,vl); +} + + +vint32m1_t test___riscv_vwadd_wx(vbool32_t mask,vint32m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx(mask,op1,0xAA,vl); +} + + +vint32m2_t test___riscv_vwadd_wx(vbool16_t mask,vint32m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx(mask,op1,0xAA,vl); +} + + +vint32m4_t test___riscv_vwadd_wx(vbool8_t mask,vint32m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx(mask,op1,0xAA,vl); +} + + +vint32m8_t test___riscv_vwadd_wx(vbool4_t mask,vint32m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx(mask,op1,0xAA,vl); +} + + +vint64m1_t test___riscv_vwadd_wx(vbool64_t mask,vint64m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_wx(mask,op1,0xAA,vl); +} + + +vint64m2_t test___riscv_vwadd_wx(vbool32_t mask,vint64m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_wx(mask,op1,0xAA,vl); +} + + +vint64m4_t test___riscv_vwadd_wx(vbool16_t mask,vint64m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_wx(mask,op1,0xAA,vl); +} + + +vint64m8_t test___riscv_vwadd_wx(vbool8_t mask,vint64m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_wx(mask,op1,0xAA,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx-2.C new file mode 100644 index 00000000000..fc7de281544 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx-2.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwadd_wx(vint16mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx(op1,0xAA,31); +} + + +vint16mf2_t test___riscv_vwadd_wx(vint16mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx(op1,0xAA,31); +} + + +vint16m1_t test___riscv_vwadd_wx(vint16m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx(op1,0xAA,31); +} + + +vint16m2_t test___riscv_vwadd_wx(vint16m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx(op1,0xAA,31); +} + + +vint16m4_t test___riscv_vwadd_wx(vint16m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx(op1,0xAA,31); +} + + +vint16m8_t test___riscv_vwadd_wx(vint16m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx(op1,0xAA,31); +} + + +vint32mf2_t test___riscv_vwadd_wx(vint32mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx(op1,0xAA,31); +} + + +vint32m1_t test___riscv_vwadd_wx(vint32m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx(op1,0xAA,31); +} + + +vint32m2_t test___riscv_vwadd_wx(vint32m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx(op1,0xAA,31); +} + + +vint32m4_t test___riscv_vwadd_wx(vint32m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx(op1,0xAA,31); +} + + +vint32m8_t test___riscv_vwadd_wx(vint32m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx(op1,0xAA,31); +} + + +vint64m1_t test___riscv_vwadd_wx(vint64m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_wx(op1,0xAA,31); +} + + +vint64m2_t test___riscv_vwadd_wx(vint64m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_wx(op1,0xAA,31); +} + + +vint64m4_t test___riscv_vwadd_wx(vint64m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_wx(op1,0xAA,31); +} + + +vint64m8_t test___riscv_vwadd_wx(vint64m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_wx(op1,0xAA,31); +} + + +vint16mf4_t test___riscv_vwadd_wx(vbool64_t mask,vint16mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx(mask,op1,0xAA,31); +} + + +vint16mf2_t test___riscv_vwadd_wx(vbool32_t mask,vint16mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx(mask,op1,0xAA,31); +} + + +vint16m1_t test___riscv_vwadd_wx(vbool16_t mask,vint16m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx(mask,op1,0xAA,31); +} + + +vint16m2_t test___riscv_vwadd_wx(vbool8_t mask,vint16m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx(mask,op1,0xAA,31); +} + + +vint16m4_t test___riscv_vwadd_wx(vbool4_t mask,vint16m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx(mask,op1,0xAA,31); +} + + +vint16m8_t test___riscv_vwadd_wx(vbool2_t mask,vint16m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx(mask,op1,0xAA,31); +} + + +vint32mf2_t test___riscv_vwadd_wx(vbool64_t mask,vint32mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx(mask,op1,0xAA,31); +} + + +vint32m1_t test___riscv_vwadd_wx(vbool32_t mask,vint32m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx(mask,op1,0xAA,31); +} + + +vint32m2_t test___riscv_vwadd_wx(vbool16_t mask,vint32m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx(mask,op1,0xAA,31); +} + + +vint32m4_t test___riscv_vwadd_wx(vbool8_t mask,vint32m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx(mask,op1,0xAA,31); +} + + +vint32m8_t test___riscv_vwadd_wx(vbool4_t mask,vint32m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx(mask,op1,0xAA,31); +} + + +vint64m1_t test___riscv_vwadd_wx(vbool64_t mask,vint64m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_wx(mask,op1,0xAA,31); +} + + +vint64m2_t test___riscv_vwadd_wx(vbool32_t mask,vint64m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_wx(mask,op1,0xAA,31); +} + + +vint64m4_t test___riscv_vwadd_wx(vbool16_t mask,vint64m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_wx(mask,op1,0xAA,31); +} + + +vint64m8_t test___riscv_vwadd_wx(vbool8_t mask,vint64m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_wx(mask,op1,0xAA,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx-3.C new file mode 100644 index 00000000000..fffa55e93a1 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx-3.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwadd_wx(vint16mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx(op1,0xAA,32); +} + + +vint16mf2_t test___riscv_vwadd_wx(vint16mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx(op1,0xAA,32); +} + + +vint16m1_t test___riscv_vwadd_wx(vint16m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx(op1,0xAA,32); +} + + +vint16m2_t test___riscv_vwadd_wx(vint16m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx(op1,0xAA,32); +} + + +vint16m4_t test___riscv_vwadd_wx(vint16m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx(op1,0xAA,32); +} + + +vint16m8_t test___riscv_vwadd_wx(vint16m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx(op1,0xAA,32); +} + + +vint32mf2_t test___riscv_vwadd_wx(vint32mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx(op1,0xAA,32); +} + + +vint32m1_t test___riscv_vwadd_wx(vint32m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx(op1,0xAA,32); +} + + +vint32m2_t test___riscv_vwadd_wx(vint32m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx(op1,0xAA,32); +} + + +vint32m4_t test___riscv_vwadd_wx(vint32m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx(op1,0xAA,32); +} + + +vint32m8_t test___riscv_vwadd_wx(vint32m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx(op1,0xAA,32); +} + + +vint64m1_t test___riscv_vwadd_wx(vint64m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_wx(op1,0xAA,32); +} + + +vint64m2_t test___riscv_vwadd_wx(vint64m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_wx(op1,0xAA,32); +} + + +vint64m4_t test___riscv_vwadd_wx(vint64m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_wx(op1,0xAA,32); +} + + +vint64m8_t test___riscv_vwadd_wx(vint64m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_wx(op1,0xAA,32); +} + + +vint16mf4_t test___riscv_vwadd_wx(vbool64_t mask,vint16mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx(mask,op1,0xAA,32); +} + + +vint16mf2_t test___riscv_vwadd_wx(vbool32_t mask,vint16mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx(mask,op1,0xAA,32); +} + + +vint16m1_t test___riscv_vwadd_wx(vbool16_t mask,vint16m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx(mask,op1,0xAA,32); +} + + +vint16m2_t test___riscv_vwadd_wx(vbool8_t mask,vint16m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx(mask,op1,0xAA,32); +} + + +vint16m4_t test___riscv_vwadd_wx(vbool4_t mask,vint16m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx(mask,op1,0xAA,32); +} + + +vint16m8_t test___riscv_vwadd_wx(vbool2_t mask,vint16m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx(mask,op1,0xAA,32); +} + + +vint32mf2_t test___riscv_vwadd_wx(vbool64_t mask,vint32mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx(mask,op1,0xAA,32); +} + + +vint32m1_t test___riscv_vwadd_wx(vbool32_t mask,vint32m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx(mask,op1,0xAA,32); +} + + +vint32m2_t test___riscv_vwadd_wx(vbool16_t mask,vint32m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx(mask,op1,0xAA,32); +} + + +vint32m4_t test___riscv_vwadd_wx(vbool8_t mask,vint32m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx(mask,op1,0xAA,32); +} + + +vint32m8_t test___riscv_vwadd_wx(vbool4_t mask,vint32m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx(mask,op1,0xAA,32); +} + + +vint64m1_t test___riscv_vwadd_wx(vbool64_t mask,vint64m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_wx(mask,op1,0xAA,32); +} + + +vint64m2_t test___riscv_vwadd_wx(vbool32_t mask,vint64m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_wx(mask,op1,0xAA,32); +} + + +vint64m4_t test___riscv_vwadd_wx(vbool16_t mask,vint64m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_wx(mask,op1,0xAA,32); +} + + +vint64m8_t test___riscv_vwadd_wx(vbool8_t mask,vint64m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_wx(mask,op1,0xAA,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx_mu-1.C new file mode 100644 index 00000000000..71d9f8cce9c --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx_mu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwadd_wx_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx_mu(mask,merge,op1,0xAA,vl); +} + + +vint16mf2_t test___riscv_vwadd_wx_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx_mu(mask,merge,op1,0xAA,vl); +} + + +vint16m1_t test___riscv_vwadd_wx_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx_mu(mask,merge,op1,0xAA,vl); +} + + +vint16m2_t test___riscv_vwadd_wx_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx_mu(mask,merge,op1,0xAA,vl); +} + + +vint16m4_t test___riscv_vwadd_wx_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx_mu(mask,merge,op1,0xAA,vl); +} + + +vint16m8_t test___riscv_vwadd_wx_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx_mu(mask,merge,op1,0xAA,vl); +} + + +vint32mf2_t test___riscv_vwadd_wx_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx_mu(mask,merge,op1,0xAA,vl); +} + + +vint32m1_t test___riscv_vwadd_wx_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx_mu(mask,merge,op1,0xAA,vl); +} + + +vint32m2_t test___riscv_vwadd_wx_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx_mu(mask,merge,op1,0xAA,vl); +} + + +vint32m4_t test___riscv_vwadd_wx_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx_mu(mask,merge,op1,0xAA,vl); +} + + +vint32m8_t test___riscv_vwadd_wx_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx_mu(mask,merge,op1,0xAA,vl); +} + + +vint64m1_t test___riscv_vwadd_wx_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_wx_mu(mask,merge,op1,0xAA,vl); +} + + +vint64m2_t test___riscv_vwadd_wx_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_wx_mu(mask,merge,op1,0xAA,vl); +} + + +vint64m4_t test___riscv_vwadd_wx_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_wx_mu(mask,merge,op1,0xAA,vl); +} + + +vint64m8_t test___riscv_vwadd_wx_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_wx_mu(mask,merge,op1,0xAA,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx_mu-2.C new file mode 100644 index 00000000000..256270a1761 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx_mu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwadd_wx_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx_mu(mask,merge,op1,0xAA,31); +} + + +vint16mf2_t test___riscv_vwadd_wx_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx_mu(mask,merge,op1,0xAA,31); +} + + +vint16m1_t test___riscv_vwadd_wx_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx_mu(mask,merge,op1,0xAA,31); +} + + +vint16m2_t test___riscv_vwadd_wx_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx_mu(mask,merge,op1,0xAA,31); +} + + +vint16m4_t test___riscv_vwadd_wx_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx_mu(mask,merge,op1,0xAA,31); +} + + +vint16m8_t test___riscv_vwadd_wx_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx_mu(mask,merge,op1,0xAA,31); +} + + +vint32mf2_t test___riscv_vwadd_wx_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx_mu(mask,merge,op1,0xAA,31); +} + + +vint32m1_t test___riscv_vwadd_wx_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx_mu(mask,merge,op1,0xAA,31); +} + + +vint32m2_t test___riscv_vwadd_wx_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx_mu(mask,merge,op1,0xAA,31); +} + + +vint32m4_t test___riscv_vwadd_wx_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx_mu(mask,merge,op1,0xAA,31); +} + + +vint32m8_t test___riscv_vwadd_wx_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx_mu(mask,merge,op1,0xAA,31); +} + + +vint64m1_t test___riscv_vwadd_wx_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_wx_mu(mask,merge,op1,0xAA,31); +} + + +vint64m2_t test___riscv_vwadd_wx_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_wx_mu(mask,merge,op1,0xAA,31); +} + + +vint64m4_t test___riscv_vwadd_wx_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_wx_mu(mask,merge,op1,0xAA,31); +} + + +vint64m8_t test___riscv_vwadd_wx_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_wx_mu(mask,merge,op1,0xAA,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx_mu-3.C new file mode 100644 index 00000000000..2c72c250707 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx_mu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwadd_wx_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx_mu(mask,merge,op1,0xAA,32); +} + + +vint16mf2_t test___riscv_vwadd_wx_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx_mu(mask,merge,op1,0xAA,32); +} + + +vint16m1_t test___riscv_vwadd_wx_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx_mu(mask,merge,op1,0xAA,32); +} + + +vint16m2_t test___riscv_vwadd_wx_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx_mu(mask,merge,op1,0xAA,32); +} + + +vint16m4_t test___riscv_vwadd_wx_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx_mu(mask,merge,op1,0xAA,32); +} + + +vint16m8_t test___riscv_vwadd_wx_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx_mu(mask,merge,op1,0xAA,32); +} + + +vint32mf2_t test___riscv_vwadd_wx_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx_mu(mask,merge,op1,0xAA,32); +} + + +vint32m1_t test___riscv_vwadd_wx_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx_mu(mask,merge,op1,0xAA,32); +} + + +vint32m2_t test___riscv_vwadd_wx_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx_mu(mask,merge,op1,0xAA,32); +} + + +vint32m4_t test___riscv_vwadd_wx_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx_mu(mask,merge,op1,0xAA,32); +} + + +vint32m8_t test___riscv_vwadd_wx_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx_mu(mask,merge,op1,0xAA,32); +} + + +vint64m1_t test___riscv_vwadd_wx_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_wx_mu(mask,merge,op1,0xAA,32); +} + + +vint64m2_t test___riscv_vwadd_wx_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_wx_mu(mask,merge,op1,0xAA,32); +} + + +vint64m4_t test___riscv_vwadd_wx_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_wx_mu(mask,merge,op1,0xAA,32); +} + + +vint64m8_t test___riscv_vwadd_wx_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_wx_mu(mask,merge,op1,0xAA,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx_tu-1.C new file mode 100644 index 00000000000..8ee81865291 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx_tu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwadd_wx_tu(vint16mf4_t merge,vint16mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tu(merge,op1,0xAA,vl); +} + + +vint16mf2_t test___riscv_vwadd_wx_tu(vint16mf2_t merge,vint16mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tu(merge,op1,0xAA,vl); +} + + +vint16m1_t test___riscv_vwadd_wx_tu(vint16m1_t merge,vint16m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tu(merge,op1,0xAA,vl); +} + + +vint16m2_t test___riscv_vwadd_wx_tu(vint16m2_t merge,vint16m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tu(merge,op1,0xAA,vl); +} + + +vint16m4_t test___riscv_vwadd_wx_tu(vint16m4_t merge,vint16m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tu(merge,op1,0xAA,vl); +} + + +vint16m8_t test___riscv_vwadd_wx_tu(vint16m8_t merge,vint16m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tu(merge,op1,0xAA,vl); +} + + +vint32mf2_t test___riscv_vwadd_wx_tu(vint32mf2_t merge,vint32mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tu(merge,op1,0xAA,vl); +} + + +vint32m1_t test___riscv_vwadd_wx_tu(vint32m1_t merge,vint32m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tu(merge,op1,0xAA,vl); +} + + +vint32m2_t test___riscv_vwadd_wx_tu(vint32m2_t merge,vint32m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tu(merge,op1,0xAA,vl); +} + + +vint32m4_t test___riscv_vwadd_wx_tu(vint32m4_t merge,vint32m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tu(merge,op1,0xAA,vl); +} + + +vint32m8_t test___riscv_vwadd_wx_tu(vint32m8_t merge,vint32m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tu(merge,op1,0xAA,vl); +} + + +vint64m1_t test___riscv_vwadd_wx_tu(vint64m1_t merge,vint64m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tu(merge,op1,0xAA,vl); +} + + +vint64m2_t test___riscv_vwadd_wx_tu(vint64m2_t merge,vint64m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tu(merge,op1,0xAA,vl); +} + + +vint64m4_t test___riscv_vwadd_wx_tu(vint64m4_t merge,vint64m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tu(merge,op1,0xAA,vl); +} + + +vint64m8_t test___riscv_vwadd_wx_tu(vint64m8_t merge,vint64m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tu(merge,op1,0xAA,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx_tu-2.C new file mode 100644 index 00000000000..284f4b07320 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx_tu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwadd_wx_tu(vint16mf4_t merge,vint16mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tu(merge,op1,0xAA,31); +} + + +vint16mf2_t test___riscv_vwadd_wx_tu(vint16mf2_t merge,vint16mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tu(merge,op1,0xAA,31); +} + + +vint16m1_t test___riscv_vwadd_wx_tu(vint16m1_t merge,vint16m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tu(merge,op1,0xAA,31); +} + + +vint16m2_t test___riscv_vwadd_wx_tu(vint16m2_t merge,vint16m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tu(merge,op1,0xAA,31); +} + + +vint16m4_t test___riscv_vwadd_wx_tu(vint16m4_t merge,vint16m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tu(merge,op1,0xAA,31); +} + + +vint16m8_t test___riscv_vwadd_wx_tu(vint16m8_t merge,vint16m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tu(merge,op1,0xAA,31); +} + + +vint32mf2_t test___riscv_vwadd_wx_tu(vint32mf2_t merge,vint32mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tu(merge,op1,0xAA,31); +} + + +vint32m1_t test___riscv_vwadd_wx_tu(vint32m1_t merge,vint32m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tu(merge,op1,0xAA,31); +} + + +vint32m2_t test___riscv_vwadd_wx_tu(vint32m2_t merge,vint32m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tu(merge,op1,0xAA,31); +} + + +vint32m4_t test___riscv_vwadd_wx_tu(vint32m4_t merge,vint32m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tu(merge,op1,0xAA,31); +} + + +vint32m8_t test___riscv_vwadd_wx_tu(vint32m8_t merge,vint32m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tu(merge,op1,0xAA,31); +} + + +vint64m1_t test___riscv_vwadd_wx_tu(vint64m1_t merge,vint64m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tu(merge,op1,0xAA,31); +} + + +vint64m2_t test___riscv_vwadd_wx_tu(vint64m2_t merge,vint64m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tu(merge,op1,0xAA,31); +} + + +vint64m4_t test___riscv_vwadd_wx_tu(vint64m4_t merge,vint64m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tu(merge,op1,0xAA,31); +} + + +vint64m8_t test___riscv_vwadd_wx_tu(vint64m8_t merge,vint64m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tu(merge,op1,0xAA,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx_tu-3.C new file mode 100644 index 00000000000..27ba74833c9 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx_tu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwadd_wx_tu(vint16mf4_t merge,vint16mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tu(merge,op1,0xAA,32); +} + + +vint16mf2_t test___riscv_vwadd_wx_tu(vint16mf2_t merge,vint16mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tu(merge,op1,0xAA,32); +} + + +vint16m1_t test___riscv_vwadd_wx_tu(vint16m1_t merge,vint16m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tu(merge,op1,0xAA,32); +} + + +vint16m2_t test___riscv_vwadd_wx_tu(vint16m2_t merge,vint16m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tu(merge,op1,0xAA,32); +} + + +vint16m4_t test___riscv_vwadd_wx_tu(vint16m4_t merge,vint16m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tu(merge,op1,0xAA,32); +} + + +vint16m8_t test___riscv_vwadd_wx_tu(vint16m8_t merge,vint16m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tu(merge,op1,0xAA,32); +} + + +vint32mf2_t test___riscv_vwadd_wx_tu(vint32mf2_t merge,vint32mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tu(merge,op1,0xAA,32); +} + + +vint32m1_t test___riscv_vwadd_wx_tu(vint32m1_t merge,vint32m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tu(merge,op1,0xAA,32); +} + + +vint32m2_t test___riscv_vwadd_wx_tu(vint32m2_t merge,vint32m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tu(merge,op1,0xAA,32); +} + + +vint32m4_t test___riscv_vwadd_wx_tu(vint32m4_t merge,vint32m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tu(merge,op1,0xAA,32); +} + + +vint32m8_t test___riscv_vwadd_wx_tu(vint32m8_t merge,vint32m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tu(merge,op1,0xAA,32); +} + + +vint64m1_t test___riscv_vwadd_wx_tu(vint64m1_t merge,vint64m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tu(merge,op1,0xAA,32); +} + + +vint64m2_t test___riscv_vwadd_wx_tu(vint64m2_t merge,vint64m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tu(merge,op1,0xAA,32); +} + + +vint64m4_t test___riscv_vwadd_wx_tu(vint64m4_t merge,vint64m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tu(merge,op1,0xAA,32); +} + + +vint64m8_t test___riscv_vwadd_wx_tu(vint64m8_t merge,vint64m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tu(merge,op1,0xAA,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx_tum-1.C new file mode 100644 index 00000000000..22d4d0eb508 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx_tum-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwadd_wx_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tum(mask,merge,op1,0xAA,vl); +} + + +vint16mf2_t test___riscv_vwadd_wx_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tum(mask,merge,op1,0xAA,vl); +} + + +vint16m1_t test___riscv_vwadd_wx_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tum(mask,merge,op1,0xAA,vl); +} + + +vint16m2_t test___riscv_vwadd_wx_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tum(mask,merge,op1,0xAA,vl); +} + + +vint16m4_t test___riscv_vwadd_wx_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tum(mask,merge,op1,0xAA,vl); +} + + +vint16m8_t test___riscv_vwadd_wx_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tum(mask,merge,op1,0xAA,vl); +} + + +vint32mf2_t test___riscv_vwadd_wx_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tum(mask,merge,op1,0xAA,vl); +} + + +vint32m1_t test___riscv_vwadd_wx_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tum(mask,merge,op1,0xAA,vl); +} + + +vint32m2_t test___riscv_vwadd_wx_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tum(mask,merge,op1,0xAA,vl); +} + + +vint32m4_t test___riscv_vwadd_wx_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tum(mask,merge,op1,0xAA,vl); +} + + +vint32m8_t test___riscv_vwadd_wx_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tum(mask,merge,op1,0xAA,vl); +} + + +vint64m1_t test___riscv_vwadd_wx_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tum(mask,merge,op1,0xAA,vl); +} + + +vint64m2_t test___riscv_vwadd_wx_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tum(mask,merge,op1,0xAA,vl); +} + + +vint64m4_t test___riscv_vwadd_wx_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tum(mask,merge,op1,0xAA,vl); +} + + +vint64m8_t test___riscv_vwadd_wx_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tum(mask,merge,op1,0xAA,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx_tum-2.C new file mode 100644 index 00000000000..db285a583a6 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx_tum-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwadd_wx_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tum(mask,merge,op1,0xAA,31); +} + + +vint16mf2_t test___riscv_vwadd_wx_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tum(mask,merge,op1,0xAA,31); +} + + +vint16m1_t test___riscv_vwadd_wx_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tum(mask,merge,op1,0xAA,31); +} + + +vint16m2_t test___riscv_vwadd_wx_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tum(mask,merge,op1,0xAA,31); +} + + +vint16m4_t test___riscv_vwadd_wx_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tum(mask,merge,op1,0xAA,31); +} + + +vint16m8_t test___riscv_vwadd_wx_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tum(mask,merge,op1,0xAA,31); +} + + +vint32mf2_t test___riscv_vwadd_wx_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tum(mask,merge,op1,0xAA,31); +} + + +vint32m1_t test___riscv_vwadd_wx_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tum(mask,merge,op1,0xAA,31); +} + + +vint32m2_t test___riscv_vwadd_wx_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tum(mask,merge,op1,0xAA,31); +} + + +vint32m4_t test___riscv_vwadd_wx_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tum(mask,merge,op1,0xAA,31); +} + + +vint32m8_t test___riscv_vwadd_wx_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tum(mask,merge,op1,0xAA,31); +} + + +vint64m1_t test___riscv_vwadd_wx_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tum(mask,merge,op1,0xAA,31); +} + + +vint64m2_t test___riscv_vwadd_wx_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tum(mask,merge,op1,0xAA,31); +} + + +vint64m4_t test___riscv_vwadd_wx_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tum(mask,merge,op1,0xAA,31); +} + + +vint64m8_t test___riscv_vwadd_wx_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tum(mask,merge,op1,0xAA,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx_tum-3.C new file mode 100644 index 00000000000..9c1cad1b83d --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx_tum-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwadd_wx_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tum(mask,merge,op1,0xAA,32); +} + + +vint16mf2_t test___riscv_vwadd_wx_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tum(mask,merge,op1,0xAA,32); +} + + +vint16m1_t test___riscv_vwadd_wx_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tum(mask,merge,op1,0xAA,32); +} + + +vint16m2_t test___riscv_vwadd_wx_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tum(mask,merge,op1,0xAA,32); +} + + +vint16m4_t test___riscv_vwadd_wx_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tum(mask,merge,op1,0xAA,32); +} + + +vint16m8_t test___riscv_vwadd_wx_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tum(mask,merge,op1,0xAA,32); +} + + +vint32mf2_t test___riscv_vwadd_wx_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tum(mask,merge,op1,0xAA,32); +} + + +vint32m1_t test___riscv_vwadd_wx_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tum(mask,merge,op1,0xAA,32); +} + + +vint32m2_t test___riscv_vwadd_wx_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tum(mask,merge,op1,0xAA,32); +} + + +vint32m4_t test___riscv_vwadd_wx_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tum(mask,merge,op1,0xAA,32); +} + + +vint32m8_t test___riscv_vwadd_wx_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tum(mask,merge,op1,0xAA,32); +} + + +vint64m1_t test___riscv_vwadd_wx_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tum(mask,merge,op1,0xAA,32); +} + + +vint64m2_t test___riscv_vwadd_wx_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tum(mask,merge,op1,0xAA,32); +} + + +vint64m4_t test___riscv_vwadd_wx_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tum(mask,merge,op1,0xAA,32); +} + + +vint64m8_t test___riscv_vwadd_wx_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tum(mask,merge,op1,0xAA,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx_tumu-1.C new file mode 100644 index 00000000000..15842274ac0 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx_tumu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwadd_wx_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tumu(mask,merge,op1,0xAA,vl); +} + + +vint16mf2_t test___riscv_vwadd_wx_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tumu(mask,merge,op1,0xAA,vl); +} + + +vint16m1_t test___riscv_vwadd_wx_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tumu(mask,merge,op1,0xAA,vl); +} + + +vint16m2_t test___riscv_vwadd_wx_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tumu(mask,merge,op1,0xAA,vl); +} + + +vint16m4_t test___riscv_vwadd_wx_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tumu(mask,merge,op1,0xAA,vl); +} + + +vint16m8_t test___riscv_vwadd_wx_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tumu(mask,merge,op1,0xAA,vl); +} + + +vint32mf2_t test___riscv_vwadd_wx_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tumu(mask,merge,op1,0xAA,vl); +} + + +vint32m1_t test___riscv_vwadd_wx_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tumu(mask,merge,op1,0xAA,vl); +} + + +vint32m2_t test___riscv_vwadd_wx_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tumu(mask,merge,op1,0xAA,vl); +} + + +vint32m4_t test___riscv_vwadd_wx_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tumu(mask,merge,op1,0xAA,vl); +} + + +vint32m8_t test___riscv_vwadd_wx_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tumu(mask,merge,op1,0xAA,vl); +} + + +vint64m1_t test___riscv_vwadd_wx_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tumu(mask,merge,op1,0xAA,vl); +} + + +vint64m2_t test___riscv_vwadd_wx_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tumu(mask,merge,op1,0xAA,vl); +} + + +vint64m4_t test___riscv_vwadd_wx_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tumu(mask,merge,op1,0xAA,vl); +} + + +vint64m8_t test___riscv_vwadd_wx_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tumu(mask,merge,op1,0xAA,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx_tumu-2.C new file mode 100644 index 00000000000..d818bbf1776 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx_tumu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwadd_wx_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tumu(mask,merge,op1,0xAA,31); +} + + +vint16mf2_t test___riscv_vwadd_wx_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tumu(mask,merge,op1,0xAA,31); +} + + +vint16m1_t test___riscv_vwadd_wx_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tumu(mask,merge,op1,0xAA,31); +} + + +vint16m2_t test___riscv_vwadd_wx_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tumu(mask,merge,op1,0xAA,31); +} + + +vint16m4_t test___riscv_vwadd_wx_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tumu(mask,merge,op1,0xAA,31); +} + + +vint16m8_t test___riscv_vwadd_wx_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tumu(mask,merge,op1,0xAA,31); +} + + +vint32mf2_t test___riscv_vwadd_wx_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tumu(mask,merge,op1,0xAA,31); +} + + +vint32m1_t test___riscv_vwadd_wx_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tumu(mask,merge,op1,0xAA,31); +} + + +vint32m2_t test___riscv_vwadd_wx_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tumu(mask,merge,op1,0xAA,31); +} + + +vint32m4_t test___riscv_vwadd_wx_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tumu(mask,merge,op1,0xAA,31); +} + + +vint32m8_t test___riscv_vwadd_wx_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tumu(mask,merge,op1,0xAA,31); +} + + +vint64m1_t test___riscv_vwadd_wx_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tumu(mask,merge,op1,0xAA,31); +} + + +vint64m2_t test___riscv_vwadd_wx_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tumu(mask,merge,op1,0xAA,31); +} + + +vint64m4_t test___riscv_vwadd_wx_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tumu(mask,merge,op1,0xAA,31); +} + + +vint64m8_t test___riscv_vwadd_wx_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tumu(mask,merge,op1,0xAA,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx_tumu-3.C new file mode 100644 index 00000000000..195d1643085 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_wx_tumu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwadd_wx_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tumu(mask,merge,op1,0xAA,32); +} + + +vint16mf2_t test___riscv_vwadd_wx_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tumu(mask,merge,op1,0xAA,32); +} + + +vint16m1_t test___riscv_vwadd_wx_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tumu(mask,merge,op1,0xAA,32); +} + + +vint16m2_t test___riscv_vwadd_wx_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tumu(mask,merge,op1,0xAA,32); +} + + +vint16m4_t test___riscv_vwadd_wx_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tumu(mask,merge,op1,0xAA,32); +} + + +vint16m8_t test___riscv_vwadd_wx_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tumu(mask,merge,op1,0xAA,32); +} + + +vint32mf2_t test___riscv_vwadd_wx_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tumu(mask,merge,op1,0xAA,32); +} + + +vint32m1_t test___riscv_vwadd_wx_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tumu(mask,merge,op1,0xAA,32); +} + + +vint32m2_t test___riscv_vwadd_wx_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tumu(mask,merge,op1,0xAA,32); +} + + +vint32m4_t test___riscv_vwadd_wx_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tumu(mask,merge,op1,0xAA,32); +} + + +vint32m8_t test___riscv_vwadd_wx_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tumu(mask,merge,op1,0xAA,32); +} + + +vint64m1_t test___riscv_vwadd_wx_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tumu(mask,merge,op1,0xAA,32); +} + + +vint64m2_t test___riscv_vwadd_wx_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tumu(mask,merge,op1,0xAA,32); +} + + +vint64m4_t test___riscv_vwadd_wx_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tumu(mask,merge,op1,0xAA,32); +} + + +vint64m8_t test___riscv_vwadd_wx_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_wx_tumu(mask,merge,op1,0xAA,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwadd\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ -- 2.36.1