From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtpbg154.qq.com (smtpbg154.qq.com [15.184.224.54]) by sourceware.org (Postfix) with ESMTPS id A483C3858D39 for ; Wed, 8 Feb 2023 02:53:39 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org A483C3858D39 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp85t1675824447ts2jfvui Received: from server1.localdomain ( [58.60.1.22]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 08 Feb 2023 10:47:26 +0800 (CST) X-QQ-SSF: 01400000000000E0L000000A0000000 X-QQ-FEAT: q+yjhizk/eL9N/qt4qtDVoyfxJZFd+cAKGYKcJAqMGjiERSIy700ZtCuqmTTj TfBnNnhjc4DRCD1Uopb96tUXIqYUv/ZP0LicSlehL9mCe1TSfFMQ0GthmwJwDYY978dfRkB Po79xYCyjWtBFstaE1jdFdvCVV14YptNfy7J/8pk73EgtqD04XEZGF5P6fKHaRTB0ElkG2E p+HC54C8A7E9xjCyihppo3JN27voM2EmhjxDcgUg196q0NvAtJsv6GY9qkRpcrgAgjLx9oC enJ17ulndu2j45ra6YhBDUEshEQMKD14y85KLo516eVddkfcI9GGUH36p0USd9yZnhNbf5p swhXK3Lv5tH44uPGzdUT6Z8bxSx2UNv539u5QCIcdz6+m/Yia4guo5qFs8sDA== X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: Add vadc C++ API tests Date: Wed, 8 Feb 2023 10:47:25 +0800 Message-Id: <20230208024725.229946-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,RCVD_IN_BARRACUDACENTRAL,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Ju-Zhe Zhong gcc/testsuite/ChangeLog: * g++.target/riscv/rvv/base/vadc_vvm-1.C: New test. * g++.target/riscv/rvv/base/vadc_vvm-2.C: New test. * g++.target/riscv/rvv/base/vadc_vvm-3.C: New test. * g++.target/riscv/rvv/base/vadc_vvm_tu-1.C: New test. * g++.target/riscv/rvv/base/vadc_vvm_tu-2.C: New test. * g++.target/riscv/rvv/base/vadc_vvm_tu-3.C: New test. * g++.target/riscv/rvv/base/vadc_vxm_rv32-1.C: New test. * g++.target/riscv/rvv/base/vadc_vxm_rv32-2.C: New test. * g++.target/riscv/rvv/base/vadc_vxm_rv32-3.C: New test. * g++.target/riscv/rvv/base/vadc_vxm_rv64-1.C: New test. * g++.target/riscv/rvv/base/vadc_vxm_rv64-2.C: New test. * g++.target/riscv/rvv/base/vadc_vxm_rv64-3.C: New test. * g++.target/riscv/rvv/base/vadc_vxm_tu_rv32-1.C: New test. * g++.target/riscv/rvv/base/vadc_vxm_tu_rv32-2.C: New test. * g++.target/riscv/rvv/base/vadc_vxm_tu_rv32-3.C: New test. * g++.target/riscv/rvv/base/vadc_vxm_tu_rv64-1.C: New test. * g++.target/riscv/rvv/base/vadc_vxm_tu_rv64-2.C: New test. * g++.target/riscv/rvv/base/vadc_vxm_tu_rv64-3.C: New test. --- .../g++.target/riscv/rvv/base/vadc_vvm-1.C | 292 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vadc_vvm-2.C | 292 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vadc_vvm-3.C | 292 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vadc_vvm_tu-1.C | 292 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vadc_vvm_tu-2.C | 292 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vadc_vvm_tu-3.C | 292 ++++++++++++++++++ .../riscv/rvv/base/vadc_vxm_rv32-1.C | 289 +++++++++++++++++ .../riscv/rvv/base/vadc_vxm_rv32-2.C | 289 +++++++++++++++++ .../riscv/rvv/base/vadc_vxm_rv32-3.C | 289 +++++++++++++++++ .../riscv/rvv/base/vadc_vxm_rv64-1.C | 292 ++++++++++++++++++ .../riscv/rvv/base/vadc_vxm_rv64-2.C | 292 ++++++++++++++++++ .../riscv/rvv/base/vadc_vxm_rv64-3.C | 292 ++++++++++++++++++ .../riscv/rvv/base/vadc_vxm_tu_rv32-1.C | 289 +++++++++++++++++ .../riscv/rvv/base/vadc_vxm_tu_rv32-2.C | 289 +++++++++++++++++ .../riscv/rvv/base/vadc_vxm_tu_rv32-3.C | 289 +++++++++++++++++ .../riscv/rvv/base/vadc_vxm_tu_rv64-1.C | 292 ++++++++++++++++++ .../riscv/rvv/base/vadc_vxm_tu_rv64-2.C | 292 ++++++++++++++++++ .../riscv/rvv/base/vadc_vxm_tu_rv64-3.C | 292 ++++++++++++++++++ 18 files changed, 5238 insertions(+) create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadc_vvm-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadc_vvm-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadc_vvm-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadc_vvm_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadc_vvm_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadc_vvm_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_tu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_tu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_tu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_tu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_tu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_tu_rv64-3.C diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vvm-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vvm-1.C new file mode 100644 index 00000000000..049b57fbd78 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vvm-1.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadc(vint8mf8_t op1,vint8mf8_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vint8mf4_t test___riscv_vadc(vint8mf4_t op1,vint8mf4_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vint8mf2_t test___riscv_vadc(vint8mf2_t op1,vint8mf2_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vint8m1_t test___riscv_vadc(vint8m1_t op1,vint8m1_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vint8m2_t test___riscv_vadc(vint8m2_t op1,vint8m2_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vint8m4_t test___riscv_vadc(vint8m4_t op1,vint8m4_t op2,vbool2_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vint8m8_t test___riscv_vadc(vint8m8_t op1,vint8m8_t op2,vbool1_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vint16mf4_t test___riscv_vadc(vint16mf4_t op1,vint16mf4_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vint16mf2_t test___riscv_vadc(vint16mf2_t op1,vint16mf2_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vint16m1_t test___riscv_vadc(vint16m1_t op1,vint16m1_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vint16m2_t test___riscv_vadc(vint16m2_t op1,vint16m2_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vint16m4_t test___riscv_vadc(vint16m4_t op1,vint16m4_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vint16m8_t test___riscv_vadc(vint16m8_t op1,vint16m8_t op2,vbool2_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vint32mf2_t test___riscv_vadc(vint32mf2_t op1,vint32mf2_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vint32m1_t test___riscv_vadc(vint32m1_t op1,vint32m1_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vint32m2_t test___riscv_vadc(vint32m2_t op1,vint32m2_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vint32m4_t test___riscv_vadc(vint32m4_t op1,vint32m4_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vint32m8_t test___riscv_vadc(vint32m8_t op1,vint32m8_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vint64m1_t test___riscv_vadc(vint64m1_t op1,vint64m1_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vint64m2_t test___riscv_vadc(vint64m2_t op1,vint64m2_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vint64m4_t test___riscv_vadc(vint64m4_t op1,vint64m4_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vint64m8_t test___riscv_vadc(vint64m8_t op1,vint64m8_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vuint8mf8_t test___riscv_vadc(vuint8mf8_t op1,vuint8mf8_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vuint8mf4_t test___riscv_vadc(vuint8mf4_t op1,vuint8mf4_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vuint8mf2_t test___riscv_vadc(vuint8mf2_t op1,vuint8mf2_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vuint8m1_t test___riscv_vadc(vuint8m1_t op1,vuint8m1_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vuint8m2_t test___riscv_vadc(vuint8m2_t op1,vuint8m2_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vuint8m4_t test___riscv_vadc(vuint8m4_t op1,vuint8m4_t op2,vbool2_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vuint8m8_t test___riscv_vadc(vuint8m8_t op1,vuint8m8_t op2,vbool1_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vuint16mf4_t test___riscv_vadc(vuint16mf4_t op1,vuint16mf4_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vuint16mf2_t test___riscv_vadc(vuint16mf2_t op1,vuint16mf2_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vuint16m1_t test___riscv_vadc(vuint16m1_t op1,vuint16m1_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vuint16m2_t test___riscv_vadc(vuint16m2_t op1,vuint16m2_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vuint16m4_t test___riscv_vadc(vuint16m4_t op1,vuint16m4_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vuint16m8_t test___riscv_vadc(vuint16m8_t op1,vuint16m8_t op2,vbool2_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vuint32mf2_t test___riscv_vadc(vuint32mf2_t op1,vuint32mf2_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vuint32m1_t test___riscv_vadc(vuint32m1_t op1,vuint32m1_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vuint32m2_t test___riscv_vadc(vuint32m2_t op1,vuint32m2_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vuint32m4_t test___riscv_vadc(vuint32m4_t op1,vuint32m4_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vuint32m8_t test___riscv_vadc(vuint32m8_t op1,vuint32m8_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vuint64m1_t test___riscv_vadc(vuint64m1_t op1,vuint64m1_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vuint64m2_t test___riscv_vadc(vuint64m2_t op1,vuint64m2_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vuint64m4_t test___riscv_vadc(vuint64m4_t op1,vuint64m4_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vuint64m8_t test___riscv_vadc(vuint64m8_t op1,vuint64m8_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vvm-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vvm-2.C new file mode 100644 index 00000000000..d1798cb181c --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vvm-2.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadc(vint8mf8_t op1,vint8mf8_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vint8mf4_t test___riscv_vadc(vint8mf4_t op1,vint8mf4_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vint8mf2_t test___riscv_vadc(vint8mf2_t op1,vint8mf2_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vint8m1_t test___riscv_vadc(vint8m1_t op1,vint8m1_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vint8m2_t test___riscv_vadc(vint8m2_t op1,vint8m2_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vint8m4_t test___riscv_vadc(vint8m4_t op1,vint8m4_t op2,vbool2_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vint8m8_t test___riscv_vadc(vint8m8_t op1,vint8m8_t op2,vbool1_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vint16mf4_t test___riscv_vadc(vint16mf4_t op1,vint16mf4_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vint16mf2_t test___riscv_vadc(vint16mf2_t op1,vint16mf2_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vint16m1_t test___riscv_vadc(vint16m1_t op1,vint16m1_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vint16m2_t test___riscv_vadc(vint16m2_t op1,vint16m2_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vint16m4_t test___riscv_vadc(vint16m4_t op1,vint16m4_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vint16m8_t test___riscv_vadc(vint16m8_t op1,vint16m8_t op2,vbool2_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vint32mf2_t test___riscv_vadc(vint32mf2_t op1,vint32mf2_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vint32m1_t test___riscv_vadc(vint32m1_t op1,vint32m1_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vint32m2_t test___riscv_vadc(vint32m2_t op1,vint32m2_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vint32m4_t test___riscv_vadc(vint32m4_t op1,vint32m4_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vint32m8_t test___riscv_vadc(vint32m8_t op1,vint32m8_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vint64m1_t test___riscv_vadc(vint64m1_t op1,vint64m1_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vint64m2_t test___riscv_vadc(vint64m2_t op1,vint64m2_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vint64m4_t test___riscv_vadc(vint64m4_t op1,vint64m4_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vint64m8_t test___riscv_vadc(vint64m8_t op1,vint64m8_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vuint8mf8_t test___riscv_vadc(vuint8mf8_t op1,vuint8mf8_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vuint8mf4_t test___riscv_vadc(vuint8mf4_t op1,vuint8mf4_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vuint8mf2_t test___riscv_vadc(vuint8mf2_t op1,vuint8mf2_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vuint8m1_t test___riscv_vadc(vuint8m1_t op1,vuint8m1_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vuint8m2_t test___riscv_vadc(vuint8m2_t op1,vuint8m2_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vuint8m4_t test___riscv_vadc(vuint8m4_t op1,vuint8m4_t op2,vbool2_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vuint8m8_t test___riscv_vadc(vuint8m8_t op1,vuint8m8_t op2,vbool1_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vuint16mf4_t test___riscv_vadc(vuint16mf4_t op1,vuint16mf4_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vuint16mf2_t test___riscv_vadc(vuint16mf2_t op1,vuint16mf2_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vuint16m1_t test___riscv_vadc(vuint16m1_t op1,vuint16m1_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vuint16m2_t test___riscv_vadc(vuint16m2_t op1,vuint16m2_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vuint16m4_t test___riscv_vadc(vuint16m4_t op1,vuint16m4_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vuint16m8_t test___riscv_vadc(vuint16m8_t op1,vuint16m8_t op2,vbool2_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vuint32mf2_t test___riscv_vadc(vuint32mf2_t op1,vuint32mf2_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vuint32m1_t test___riscv_vadc(vuint32m1_t op1,vuint32m1_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vuint32m2_t test___riscv_vadc(vuint32m2_t op1,vuint32m2_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vuint32m4_t test___riscv_vadc(vuint32m4_t op1,vuint32m4_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vuint32m8_t test___riscv_vadc(vuint32m8_t op1,vuint32m8_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vuint64m1_t test___riscv_vadc(vuint64m1_t op1,vuint64m1_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vuint64m2_t test___riscv_vadc(vuint64m2_t op1,vuint64m2_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vuint64m4_t test___riscv_vadc(vuint64m4_t op1,vuint64m4_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vuint64m8_t test___riscv_vadc(vuint64m8_t op1,vuint64m8_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vvm-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vvm-3.C new file mode 100644 index 00000000000..1367c6e1deb --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vvm-3.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadc(vint8mf8_t op1,vint8mf8_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vint8mf4_t test___riscv_vadc(vint8mf4_t op1,vint8mf4_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vint8mf2_t test___riscv_vadc(vint8mf2_t op1,vint8mf2_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vint8m1_t test___riscv_vadc(vint8m1_t op1,vint8m1_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vint8m2_t test___riscv_vadc(vint8m2_t op1,vint8m2_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vint8m4_t test___riscv_vadc(vint8m4_t op1,vint8m4_t op2,vbool2_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vint8m8_t test___riscv_vadc(vint8m8_t op1,vint8m8_t op2,vbool1_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vint16mf4_t test___riscv_vadc(vint16mf4_t op1,vint16mf4_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vint16mf2_t test___riscv_vadc(vint16mf2_t op1,vint16mf2_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vint16m1_t test___riscv_vadc(vint16m1_t op1,vint16m1_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vint16m2_t test___riscv_vadc(vint16m2_t op1,vint16m2_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vint16m4_t test___riscv_vadc(vint16m4_t op1,vint16m4_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vint16m8_t test___riscv_vadc(vint16m8_t op1,vint16m8_t op2,vbool2_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vint32mf2_t test___riscv_vadc(vint32mf2_t op1,vint32mf2_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vint32m1_t test___riscv_vadc(vint32m1_t op1,vint32m1_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vint32m2_t test___riscv_vadc(vint32m2_t op1,vint32m2_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vint32m4_t test___riscv_vadc(vint32m4_t op1,vint32m4_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vint32m8_t test___riscv_vadc(vint32m8_t op1,vint32m8_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vint64m1_t test___riscv_vadc(vint64m1_t op1,vint64m1_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vint64m2_t test___riscv_vadc(vint64m2_t op1,vint64m2_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vint64m4_t test___riscv_vadc(vint64m4_t op1,vint64m4_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vint64m8_t test___riscv_vadc(vint64m8_t op1,vint64m8_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vuint8mf8_t test___riscv_vadc(vuint8mf8_t op1,vuint8mf8_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vuint8mf4_t test___riscv_vadc(vuint8mf4_t op1,vuint8mf4_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vuint8mf2_t test___riscv_vadc(vuint8mf2_t op1,vuint8mf2_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vuint8m1_t test___riscv_vadc(vuint8m1_t op1,vuint8m1_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vuint8m2_t test___riscv_vadc(vuint8m2_t op1,vuint8m2_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vuint8m4_t test___riscv_vadc(vuint8m4_t op1,vuint8m4_t op2,vbool2_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vuint8m8_t test___riscv_vadc(vuint8m8_t op1,vuint8m8_t op2,vbool1_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vuint16mf4_t test___riscv_vadc(vuint16mf4_t op1,vuint16mf4_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vuint16mf2_t test___riscv_vadc(vuint16mf2_t op1,vuint16mf2_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vuint16m1_t test___riscv_vadc(vuint16m1_t op1,vuint16m1_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vuint16m2_t test___riscv_vadc(vuint16m2_t op1,vuint16m2_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vuint16m4_t test___riscv_vadc(vuint16m4_t op1,vuint16m4_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vuint16m8_t test___riscv_vadc(vuint16m8_t op1,vuint16m8_t op2,vbool2_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vuint32mf2_t test___riscv_vadc(vuint32mf2_t op1,vuint32mf2_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vuint32m1_t test___riscv_vadc(vuint32m1_t op1,vuint32m1_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vuint32m2_t test___riscv_vadc(vuint32m2_t op1,vuint32m2_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vuint32m4_t test___riscv_vadc(vuint32m4_t op1,vuint32m4_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vuint32m8_t test___riscv_vadc(vuint32m8_t op1,vuint32m8_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vuint64m1_t test___riscv_vadc(vuint64m1_t op1,vuint64m1_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vuint64m2_t test___riscv_vadc(vuint64m2_t op1,vuint64m2_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vuint64m4_t test___riscv_vadc(vuint64m4_t op1,vuint64m4_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vuint64m8_t test___riscv_vadc(vuint64m8_t op1,vuint64m8_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vvm_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vvm_tu-1.C new file mode 100644 index 00000000000..a4fe7cc8816 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vvm_tu-1.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test____riscv_vadc_tu(vint8mf8_t maskedoff,vint8mf8_t op1,vint8mf8_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vint8mf4_t test____riscv_vadc_tu(vint8mf4_t maskedoff,vint8mf4_t op1,vint8mf4_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vint8mf2_t test____riscv_vadc_tu(vint8mf2_t maskedoff,vint8mf2_t op1,vint8mf2_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vint8m1_t test____riscv_vadc_tu(vint8m1_t maskedoff,vint8m1_t op1,vint8m1_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vint8m2_t test____riscv_vadc_tu(vint8m2_t maskedoff,vint8m2_t op1,vint8m2_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vint8m4_t test____riscv_vadc_tu(vint8m4_t maskedoff,vint8m4_t op1,vint8m4_t op2,vbool2_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vint8m8_t test____riscv_vadc_tu(vint8m8_t maskedoff,vint8m8_t op1,vint8m8_t op2,vbool1_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vint16mf4_t test____riscv_vadc_tu(vint16mf4_t maskedoff,vint16mf4_t op1,vint16mf4_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vint16mf2_t test____riscv_vadc_tu(vint16mf2_t maskedoff,vint16mf2_t op1,vint16mf2_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vint16m1_t test____riscv_vadc_tu(vint16m1_t maskedoff,vint16m1_t op1,vint16m1_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vint16m2_t test____riscv_vadc_tu(vint16m2_t maskedoff,vint16m2_t op1,vint16m2_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vint16m4_t test____riscv_vadc_tu(vint16m4_t maskedoff,vint16m4_t op1,vint16m4_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vint16m8_t test____riscv_vadc_tu(vint16m8_t maskedoff,vint16m8_t op1,vint16m8_t op2,vbool2_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vint32mf2_t test____riscv_vadc_tu(vint32mf2_t maskedoff,vint32mf2_t op1,vint32mf2_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vint32m1_t test____riscv_vadc_tu(vint32m1_t maskedoff,vint32m1_t op1,vint32m1_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vint32m2_t test____riscv_vadc_tu(vint32m2_t maskedoff,vint32m2_t op1,vint32m2_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vint32m4_t test____riscv_vadc_tu(vint32m4_t maskedoff,vint32m4_t op1,vint32m4_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vint32m8_t test____riscv_vadc_tu(vint32m8_t maskedoff,vint32m8_t op1,vint32m8_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vint64m1_t test____riscv_vadc_tu(vint64m1_t maskedoff,vint64m1_t op1,vint64m1_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vint64m2_t test____riscv_vadc_tu(vint64m2_t maskedoff,vint64m2_t op1,vint64m2_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vint64m4_t test____riscv_vadc_tu(vint64m4_t maskedoff,vint64m4_t op1,vint64m4_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vint64m8_t test____riscv_vadc_tu(vint64m8_t maskedoff,vint64m8_t op1,vint64m8_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vuint8mf8_t test____riscv_vadc_tu(vuint8mf8_t maskedoff,vuint8mf8_t op1,vuint8mf8_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vuint8mf4_t test____riscv_vadc_tu(vuint8mf4_t maskedoff,vuint8mf4_t op1,vuint8mf4_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vuint8mf2_t test____riscv_vadc_tu(vuint8mf2_t maskedoff,vuint8mf2_t op1,vuint8mf2_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vuint8m1_t test____riscv_vadc_tu(vuint8m1_t maskedoff,vuint8m1_t op1,vuint8m1_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vuint8m2_t test____riscv_vadc_tu(vuint8m2_t maskedoff,vuint8m2_t op1,vuint8m2_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vuint8m4_t test____riscv_vadc_tu(vuint8m4_t maskedoff,vuint8m4_t op1,vuint8m4_t op2,vbool2_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vuint8m8_t test____riscv_vadc_tu(vuint8m8_t maskedoff,vuint8m8_t op1,vuint8m8_t op2,vbool1_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vuint16mf4_t test____riscv_vadc_tu(vuint16mf4_t maskedoff,vuint16mf4_t op1,vuint16mf4_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vuint16mf2_t test____riscv_vadc_tu(vuint16mf2_t maskedoff,vuint16mf2_t op1,vuint16mf2_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vuint16m1_t test____riscv_vadc_tu(vuint16m1_t maskedoff,vuint16m1_t op1,vuint16m1_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vuint16m2_t test____riscv_vadc_tu(vuint16m2_t maskedoff,vuint16m2_t op1,vuint16m2_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vuint16m4_t test____riscv_vadc_tu(vuint16m4_t maskedoff,vuint16m4_t op1,vuint16m4_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vuint16m8_t test____riscv_vadc_tu(vuint16m8_t maskedoff,vuint16m8_t op1,vuint16m8_t op2,vbool2_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vuint32mf2_t test____riscv_vadc_tu(vuint32mf2_t maskedoff,vuint32mf2_t op1,vuint32mf2_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vuint32m1_t test____riscv_vadc_tu(vuint32m1_t maskedoff,vuint32m1_t op1,vuint32m1_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vuint32m2_t test____riscv_vadc_tu(vuint32m2_t maskedoff,vuint32m2_t op1,vuint32m2_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vuint32m4_t test____riscv_vadc_tu(vuint32m4_t maskedoff,vuint32m4_t op1,vuint32m4_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vuint32m8_t test____riscv_vadc_tu(vuint32m8_t maskedoff,vuint32m8_t op1,vuint32m8_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vuint64m1_t test____riscv_vadc_tu(vuint64m1_t maskedoff,vuint64m1_t op1,vuint64m1_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vuint64m2_t test____riscv_vadc_tu(vuint64m2_t maskedoff,vuint64m2_t op1,vuint64m2_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vuint64m4_t test____riscv_vadc_tu(vuint64m4_t maskedoff,vuint64m4_t op1,vuint64m4_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vuint64m8_t test____riscv_vadc_tu(vuint64m8_t maskedoff,vuint64m8_t op1,vuint64m8_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vvm_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vvm_tu-2.C new file mode 100644 index 00000000000..941bb79e9a0 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vvm_tu-2.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test____riscv_vadc_tu(vint8mf8_t maskedoff,vint8mf8_t op1,vint8mf8_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vint8mf4_t test____riscv_vadc_tu(vint8mf4_t maskedoff,vint8mf4_t op1,vint8mf4_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vint8mf2_t test____riscv_vadc_tu(vint8mf2_t maskedoff,vint8mf2_t op1,vint8mf2_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vint8m1_t test____riscv_vadc_tu(vint8m1_t maskedoff,vint8m1_t op1,vint8m1_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vint8m2_t test____riscv_vadc_tu(vint8m2_t maskedoff,vint8m2_t op1,vint8m2_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vint8m4_t test____riscv_vadc_tu(vint8m4_t maskedoff,vint8m4_t op1,vint8m4_t op2,vbool2_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vint8m8_t test____riscv_vadc_tu(vint8m8_t maskedoff,vint8m8_t op1,vint8m8_t op2,vbool1_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vint16mf4_t test____riscv_vadc_tu(vint16mf4_t maskedoff,vint16mf4_t op1,vint16mf4_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vint16mf2_t test____riscv_vadc_tu(vint16mf2_t maskedoff,vint16mf2_t op1,vint16mf2_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vint16m1_t test____riscv_vadc_tu(vint16m1_t maskedoff,vint16m1_t op1,vint16m1_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vint16m2_t test____riscv_vadc_tu(vint16m2_t maskedoff,vint16m2_t op1,vint16m2_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vint16m4_t test____riscv_vadc_tu(vint16m4_t maskedoff,vint16m4_t op1,vint16m4_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vint16m8_t test____riscv_vadc_tu(vint16m8_t maskedoff,vint16m8_t op1,vint16m8_t op2,vbool2_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vint32mf2_t test____riscv_vadc_tu(vint32mf2_t maskedoff,vint32mf2_t op1,vint32mf2_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vint32m1_t test____riscv_vadc_tu(vint32m1_t maskedoff,vint32m1_t op1,vint32m1_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vint32m2_t test____riscv_vadc_tu(vint32m2_t maskedoff,vint32m2_t op1,vint32m2_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vint32m4_t test____riscv_vadc_tu(vint32m4_t maskedoff,vint32m4_t op1,vint32m4_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vint32m8_t test____riscv_vadc_tu(vint32m8_t maskedoff,vint32m8_t op1,vint32m8_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vint64m1_t test____riscv_vadc_tu(vint64m1_t maskedoff,vint64m1_t op1,vint64m1_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vint64m2_t test____riscv_vadc_tu(vint64m2_t maskedoff,vint64m2_t op1,vint64m2_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vint64m4_t test____riscv_vadc_tu(vint64m4_t maskedoff,vint64m4_t op1,vint64m4_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vint64m8_t test____riscv_vadc_tu(vint64m8_t maskedoff,vint64m8_t op1,vint64m8_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vuint8mf8_t test____riscv_vadc_tu(vuint8mf8_t maskedoff,vuint8mf8_t op1,vuint8mf8_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vuint8mf4_t test____riscv_vadc_tu(vuint8mf4_t maskedoff,vuint8mf4_t op1,vuint8mf4_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vuint8mf2_t test____riscv_vadc_tu(vuint8mf2_t maskedoff,vuint8mf2_t op1,vuint8mf2_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vuint8m1_t test____riscv_vadc_tu(vuint8m1_t maskedoff,vuint8m1_t op1,vuint8m1_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vuint8m2_t test____riscv_vadc_tu(vuint8m2_t maskedoff,vuint8m2_t op1,vuint8m2_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vuint8m4_t test____riscv_vadc_tu(vuint8m4_t maskedoff,vuint8m4_t op1,vuint8m4_t op2,vbool2_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vuint8m8_t test____riscv_vadc_tu(vuint8m8_t maskedoff,vuint8m8_t op1,vuint8m8_t op2,vbool1_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vuint16mf4_t test____riscv_vadc_tu(vuint16mf4_t maskedoff,vuint16mf4_t op1,vuint16mf4_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vuint16mf2_t test____riscv_vadc_tu(vuint16mf2_t maskedoff,vuint16mf2_t op1,vuint16mf2_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vuint16m1_t test____riscv_vadc_tu(vuint16m1_t maskedoff,vuint16m1_t op1,vuint16m1_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vuint16m2_t test____riscv_vadc_tu(vuint16m2_t maskedoff,vuint16m2_t op1,vuint16m2_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vuint16m4_t test____riscv_vadc_tu(vuint16m4_t maskedoff,vuint16m4_t op1,vuint16m4_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vuint16m8_t test____riscv_vadc_tu(vuint16m8_t maskedoff,vuint16m8_t op1,vuint16m8_t op2,vbool2_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vuint32mf2_t test____riscv_vadc_tu(vuint32mf2_t maskedoff,vuint32mf2_t op1,vuint32mf2_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vuint32m1_t test____riscv_vadc_tu(vuint32m1_t maskedoff,vuint32m1_t op1,vuint32m1_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vuint32m2_t test____riscv_vadc_tu(vuint32m2_t maskedoff,vuint32m2_t op1,vuint32m2_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vuint32m4_t test____riscv_vadc_tu(vuint32m4_t maskedoff,vuint32m4_t op1,vuint32m4_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vuint32m8_t test____riscv_vadc_tu(vuint32m8_t maskedoff,vuint32m8_t op1,vuint32m8_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vuint64m1_t test____riscv_vadc_tu(vuint64m1_t maskedoff,vuint64m1_t op1,vuint64m1_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vuint64m2_t test____riscv_vadc_tu(vuint64m2_t maskedoff,vuint64m2_t op1,vuint64m2_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vuint64m4_t test____riscv_vadc_tu(vuint64m4_t maskedoff,vuint64m4_t op1,vuint64m4_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vuint64m8_t test____riscv_vadc_tu(vuint64m8_t maskedoff,vuint64m8_t op1,vuint64m8_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vvm_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vvm_tu-3.C new file mode 100644 index 00000000000..501ccfe3f32 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vvm_tu-3.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test____riscv_vadc_tu(vint8mf8_t maskedoff,vint8mf8_t op1,vint8mf8_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vint8mf4_t test____riscv_vadc_tu(vint8mf4_t maskedoff,vint8mf4_t op1,vint8mf4_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vint8mf2_t test____riscv_vadc_tu(vint8mf2_t maskedoff,vint8mf2_t op1,vint8mf2_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vint8m1_t test____riscv_vadc_tu(vint8m1_t maskedoff,vint8m1_t op1,vint8m1_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vint8m2_t test____riscv_vadc_tu(vint8m2_t maskedoff,vint8m2_t op1,vint8m2_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vint8m4_t test____riscv_vadc_tu(vint8m4_t maskedoff,vint8m4_t op1,vint8m4_t op2,vbool2_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vint8m8_t test____riscv_vadc_tu(vint8m8_t maskedoff,vint8m8_t op1,vint8m8_t op2,vbool1_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vint16mf4_t test____riscv_vadc_tu(vint16mf4_t maskedoff,vint16mf4_t op1,vint16mf4_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vint16mf2_t test____riscv_vadc_tu(vint16mf2_t maskedoff,vint16mf2_t op1,vint16mf2_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vint16m1_t test____riscv_vadc_tu(vint16m1_t maskedoff,vint16m1_t op1,vint16m1_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vint16m2_t test____riscv_vadc_tu(vint16m2_t maskedoff,vint16m2_t op1,vint16m2_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vint16m4_t test____riscv_vadc_tu(vint16m4_t maskedoff,vint16m4_t op1,vint16m4_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vint16m8_t test____riscv_vadc_tu(vint16m8_t maskedoff,vint16m8_t op1,vint16m8_t op2,vbool2_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vint32mf2_t test____riscv_vadc_tu(vint32mf2_t maskedoff,vint32mf2_t op1,vint32mf2_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vint32m1_t test____riscv_vadc_tu(vint32m1_t maskedoff,vint32m1_t op1,vint32m1_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vint32m2_t test____riscv_vadc_tu(vint32m2_t maskedoff,vint32m2_t op1,vint32m2_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vint32m4_t test____riscv_vadc_tu(vint32m4_t maskedoff,vint32m4_t op1,vint32m4_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vint32m8_t test____riscv_vadc_tu(vint32m8_t maskedoff,vint32m8_t op1,vint32m8_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vint64m1_t test____riscv_vadc_tu(vint64m1_t maskedoff,vint64m1_t op1,vint64m1_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vint64m2_t test____riscv_vadc_tu(vint64m2_t maskedoff,vint64m2_t op1,vint64m2_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vint64m4_t test____riscv_vadc_tu(vint64m4_t maskedoff,vint64m4_t op1,vint64m4_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vint64m8_t test____riscv_vadc_tu(vint64m8_t maskedoff,vint64m8_t op1,vint64m8_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vuint8mf8_t test____riscv_vadc_tu(vuint8mf8_t maskedoff,vuint8mf8_t op1,vuint8mf8_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vuint8mf4_t test____riscv_vadc_tu(vuint8mf4_t maskedoff,vuint8mf4_t op1,vuint8mf4_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vuint8mf2_t test____riscv_vadc_tu(vuint8mf2_t maskedoff,vuint8mf2_t op1,vuint8mf2_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vuint8m1_t test____riscv_vadc_tu(vuint8m1_t maskedoff,vuint8m1_t op1,vuint8m1_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vuint8m2_t test____riscv_vadc_tu(vuint8m2_t maskedoff,vuint8m2_t op1,vuint8m2_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vuint8m4_t test____riscv_vadc_tu(vuint8m4_t maskedoff,vuint8m4_t op1,vuint8m4_t op2,vbool2_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vuint8m8_t test____riscv_vadc_tu(vuint8m8_t maskedoff,vuint8m8_t op1,vuint8m8_t op2,vbool1_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vuint16mf4_t test____riscv_vadc_tu(vuint16mf4_t maskedoff,vuint16mf4_t op1,vuint16mf4_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vuint16mf2_t test____riscv_vadc_tu(vuint16mf2_t maskedoff,vuint16mf2_t op1,vuint16mf2_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vuint16m1_t test____riscv_vadc_tu(vuint16m1_t maskedoff,vuint16m1_t op1,vuint16m1_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vuint16m2_t test____riscv_vadc_tu(vuint16m2_t maskedoff,vuint16m2_t op1,vuint16m2_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vuint16m4_t test____riscv_vadc_tu(vuint16m4_t maskedoff,vuint16m4_t op1,vuint16m4_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vuint16m8_t test____riscv_vadc_tu(vuint16m8_t maskedoff,vuint16m8_t op1,vuint16m8_t op2,vbool2_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vuint32mf2_t test____riscv_vadc_tu(vuint32mf2_t maskedoff,vuint32mf2_t op1,vuint32mf2_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vuint32m1_t test____riscv_vadc_tu(vuint32m1_t maskedoff,vuint32m1_t op1,vuint32m1_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vuint32m2_t test____riscv_vadc_tu(vuint32m2_t maskedoff,vuint32m2_t op1,vuint32m2_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vuint32m4_t test____riscv_vadc_tu(vuint32m4_t maskedoff,vuint32m4_t op1,vuint32m4_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vuint32m8_t test____riscv_vadc_tu(vuint32m8_t maskedoff,vuint32m8_t op1,vuint32m8_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vuint64m1_t test____riscv_vadc_tu(vuint64m1_t maskedoff,vuint64m1_t op1,vuint64m1_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vuint64m2_t test____riscv_vadc_tu(vuint64m2_t maskedoff,vuint64m2_t op1,vuint64m2_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vuint64m4_t test____riscv_vadc_tu(vuint64m4_t maskedoff,vuint64m4_t op1,vuint64m4_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vuint64m8_t test____riscv_vadc_tu(vuint64m8_t maskedoff,vuint64m8_t op1,vuint64m8_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_rv32-1.C new file mode 100644 index 00000000000..dda88d2322b --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_rv32-1.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadc(vint8mf8_t op1,int8_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vint8mf4_t test___riscv_vadc(vint8mf4_t op1,int8_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vint8mf2_t test___riscv_vadc(vint8mf2_t op1,int8_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vint8m1_t test___riscv_vadc(vint8m1_t op1,int8_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vint8m2_t test___riscv_vadc(vint8m2_t op1,int8_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vint8m4_t test___riscv_vadc(vint8m4_t op1,int8_t op2,vbool2_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vint8m8_t test___riscv_vadc(vint8m8_t op1,int8_t op2,vbool1_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vint16mf4_t test___riscv_vadc(vint16mf4_t op1,int16_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vint16mf2_t test___riscv_vadc(vint16mf2_t op1,int16_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vint16m1_t test___riscv_vadc(vint16m1_t op1,int16_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vint16m2_t test___riscv_vadc(vint16m2_t op1,int16_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vint16m4_t test___riscv_vadc(vint16m4_t op1,int16_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vint16m8_t test___riscv_vadc(vint16m8_t op1,int16_t op2,vbool2_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vint32mf2_t test___riscv_vadc(vint32mf2_t op1,int32_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vint32m1_t test___riscv_vadc(vint32m1_t op1,int32_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vint32m2_t test___riscv_vadc(vint32m2_t op1,int32_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vint32m4_t test___riscv_vadc(vint32m4_t op1,int32_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vint32m8_t test___riscv_vadc(vint32m8_t op1,int32_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vint64m1_t test___riscv_vadc(vint64m1_t op1,int64_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vint64m2_t test___riscv_vadc(vint64m2_t op1,int64_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vint64m4_t test___riscv_vadc(vint64m4_t op1,int64_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vint64m8_t test___riscv_vadc(vint64m8_t op1,int64_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vuint8mf8_t test___riscv_vadc(vuint8mf8_t op1,uint8_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vuint8mf4_t test___riscv_vadc(vuint8mf4_t op1,uint8_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vuint8mf2_t test___riscv_vadc(vuint8mf2_t op1,uint8_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vuint8m1_t test___riscv_vadc(vuint8m1_t op1,uint8_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vuint8m2_t test___riscv_vadc(vuint8m2_t op1,uint8_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vuint8m4_t test___riscv_vadc(vuint8m4_t op1,uint8_t op2,vbool2_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vuint8m8_t test___riscv_vadc(vuint8m8_t op1,uint8_t op2,vbool1_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vuint16mf4_t test___riscv_vadc(vuint16mf4_t op1,uint16_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vuint16mf2_t test___riscv_vadc(vuint16mf2_t op1,uint16_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vuint16m1_t test___riscv_vadc(vuint16m1_t op1,uint16_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vuint16m2_t test___riscv_vadc(vuint16m2_t op1,uint16_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vuint16m4_t test___riscv_vadc(vuint16m4_t op1,uint16_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vuint16m8_t test___riscv_vadc(vuint16m8_t op1,uint16_t op2,vbool2_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vuint32mf2_t test___riscv_vadc(vuint32mf2_t op1,uint32_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vuint32m1_t test___riscv_vadc(vuint32m1_t op1,uint32_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vuint32m2_t test___riscv_vadc(vuint32m2_t op1,uint32_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vuint32m4_t test___riscv_vadc(vuint32m4_t op1,uint32_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vuint32m8_t test___riscv_vadc(vuint32m8_t op1,uint32_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vuint64m1_t test___riscv_vadc(vuint64m1_t op1,uint64_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vuint64m2_t test___riscv_vadc(vuint64m2_t op1,uint64_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vuint64m4_t test___riscv_vadc(vuint64m4_t op1,uint64_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vuint64m8_t test___riscv_vadc(vuint64m8_t op1,uint64_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_rv32-2.C new file mode 100644 index 00000000000..f15dbdd1f53 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_rv32-2.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadc(vint8mf8_t op1,int8_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vint8mf4_t test___riscv_vadc(vint8mf4_t op1,int8_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vint8mf2_t test___riscv_vadc(vint8mf2_t op1,int8_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vint8m1_t test___riscv_vadc(vint8m1_t op1,int8_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vint8m2_t test___riscv_vadc(vint8m2_t op1,int8_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vint8m4_t test___riscv_vadc(vint8m4_t op1,int8_t op2,vbool2_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vint8m8_t test___riscv_vadc(vint8m8_t op1,int8_t op2,vbool1_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vint16mf4_t test___riscv_vadc(vint16mf4_t op1,int16_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vint16mf2_t test___riscv_vadc(vint16mf2_t op1,int16_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vint16m1_t test___riscv_vadc(vint16m1_t op1,int16_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vint16m2_t test___riscv_vadc(vint16m2_t op1,int16_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vint16m4_t test___riscv_vadc(vint16m4_t op1,int16_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vint16m8_t test___riscv_vadc(vint16m8_t op1,int16_t op2,vbool2_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vint32mf2_t test___riscv_vadc(vint32mf2_t op1,int32_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vint32m1_t test___riscv_vadc(vint32m1_t op1,int32_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vint32m2_t test___riscv_vadc(vint32m2_t op1,int32_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vint32m4_t test___riscv_vadc(vint32m4_t op1,int32_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vint32m8_t test___riscv_vadc(vint32m8_t op1,int32_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vint64m1_t test___riscv_vadc(vint64m1_t op1,int64_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vint64m2_t test___riscv_vadc(vint64m2_t op1,int64_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vint64m4_t test___riscv_vadc(vint64m4_t op1,int64_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vint64m8_t test___riscv_vadc(vint64m8_t op1,int64_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vuint8mf8_t test___riscv_vadc(vuint8mf8_t op1,uint8_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vuint8mf4_t test___riscv_vadc(vuint8mf4_t op1,uint8_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vuint8mf2_t test___riscv_vadc(vuint8mf2_t op1,uint8_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vuint8m1_t test___riscv_vadc(vuint8m1_t op1,uint8_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vuint8m2_t test___riscv_vadc(vuint8m2_t op1,uint8_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vuint8m4_t test___riscv_vadc(vuint8m4_t op1,uint8_t op2,vbool2_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vuint8m8_t test___riscv_vadc(vuint8m8_t op1,uint8_t op2,vbool1_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vuint16mf4_t test___riscv_vadc(vuint16mf4_t op1,uint16_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vuint16mf2_t test___riscv_vadc(vuint16mf2_t op1,uint16_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vuint16m1_t test___riscv_vadc(vuint16m1_t op1,uint16_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vuint16m2_t test___riscv_vadc(vuint16m2_t op1,uint16_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vuint16m4_t test___riscv_vadc(vuint16m4_t op1,uint16_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vuint16m8_t test___riscv_vadc(vuint16m8_t op1,uint16_t op2,vbool2_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vuint32mf2_t test___riscv_vadc(vuint32mf2_t op1,uint32_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vuint32m1_t test___riscv_vadc(vuint32m1_t op1,uint32_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vuint32m2_t test___riscv_vadc(vuint32m2_t op1,uint32_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vuint32m4_t test___riscv_vadc(vuint32m4_t op1,uint32_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vuint32m8_t test___riscv_vadc(vuint32m8_t op1,uint32_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vuint64m1_t test___riscv_vadc(vuint64m1_t op1,uint64_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vuint64m2_t test___riscv_vadc(vuint64m2_t op1,uint64_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vuint64m4_t test___riscv_vadc(vuint64m4_t op1,uint64_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vuint64m8_t test___riscv_vadc(vuint64m8_t op1,uint64_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_rv32-3.C new file mode 100644 index 00000000000..6671f0cb19e --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_rv32-3.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadc(vint8mf8_t op1,int8_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vint8mf4_t test___riscv_vadc(vint8mf4_t op1,int8_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vint8mf2_t test___riscv_vadc(vint8mf2_t op1,int8_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vint8m1_t test___riscv_vadc(vint8m1_t op1,int8_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vint8m2_t test___riscv_vadc(vint8m2_t op1,int8_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vint8m4_t test___riscv_vadc(vint8m4_t op1,int8_t op2,vbool2_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vint8m8_t test___riscv_vadc(vint8m8_t op1,int8_t op2,vbool1_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vint16mf4_t test___riscv_vadc(vint16mf4_t op1,int16_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vint16mf2_t test___riscv_vadc(vint16mf2_t op1,int16_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vint16m1_t test___riscv_vadc(vint16m1_t op1,int16_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vint16m2_t test___riscv_vadc(vint16m2_t op1,int16_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vint16m4_t test___riscv_vadc(vint16m4_t op1,int16_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vint16m8_t test___riscv_vadc(vint16m8_t op1,int16_t op2,vbool2_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vint32mf2_t test___riscv_vadc(vint32mf2_t op1,int32_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vint32m1_t test___riscv_vadc(vint32m1_t op1,int32_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vint32m2_t test___riscv_vadc(vint32m2_t op1,int32_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vint32m4_t test___riscv_vadc(vint32m4_t op1,int32_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vint32m8_t test___riscv_vadc(vint32m8_t op1,int32_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vint64m1_t test___riscv_vadc(vint64m1_t op1,int64_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vint64m2_t test___riscv_vadc(vint64m2_t op1,int64_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vint64m4_t test___riscv_vadc(vint64m4_t op1,int64_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vint64m8_t test___riscv_vadc(vint64m8_t op1,int64_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vuint8mf8_t test___riscv_vadc(vuint8mf8_t op1,uint8_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vuint8mf4_t test___riscv_vadc(vuint8mf4_t op1,uint8_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vuint8mf2_t test___riscv_vadc(vuint8mf2_t op1,uint8_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vuint8m1_t test___riscv_vadc(vuint8m1_t op1,uint8_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vuint8m2_t test___riscv_vadc(vuint8m2_t op1,uint8_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vuint8m4_t test___riscv_vadc(vuint8m4_t op1,uint8_t op2,vbool2_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vuint8m8_t test___riscv_vadc(vuint8m8_t op1,uint8_t op2,vbool1_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vuint16mf4_t test___riscv_vadc(vuint16mf4_t op1,uint16_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vuint16mf2_t test___riscv_vadc(vuint16mf2_t op1,uint16_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vuint16m1_t test___riscv_vadc(vuint16m1_t op1,uint16_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vuint16m2_t test___riscv_vadc(vuint16m2_t op1,uint16_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vuint16m4_t test___riscv_vadc(vuint16m4_t op1,uint16_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vuint16m8_t test___riscv_vadc(vuint16m8_t op1,uint16_t op2,vbool2_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vuint32mf2_t test___riscv_vadc(vuint32mf2_t op1,uint32_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vuint32m1_t test___riscv_vadc(vuint32m1_t op1,uint32_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vuint32m2_t test___riscv_vadc(vuint32m2_t op1,uint32_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vuint32m4_t test___riscv_vadc(vuint32m4_t op1,uint32_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vuint32m8_t test___riscv_vadc(vuint32m8_t op1,uint32_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vuint64m1_t test___riscv_vadc(vuint64m1_t op1,uint64_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vuint64m2_t test___riscv_vadc(vuint64m2_t op1,uint64_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vuint64m4_t test___riscv_vadc(vuint64m4_t op1,uint64_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vuint64m8_t test___riscv_vadc(vuint64m8_t op1,uint64_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_rv64-1.C new file mode 100644 index 00000000000..e44ab9428c3 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_rv64-1.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadc(vint8mf8_t op1,int8_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vint8mf4_t test___riscv_vadc(vint8mf4_t op1,int8_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vint8mf2_t test___riscv_vadc(vint8mf2_t op1,int8_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vint8m1_t test___riscv_vadc(vint8m1_t op1,int8_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vint8m2_t test___riscv_vadc(vint8m2_t op1,int8_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vint8m4_t test___riscv_vadc(vint8m4_t op1,int8_t op2,vbool2_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vint8m8_t test___riscv_vadc(vint8m8_t op1,int8_t op2,vbool1_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vint16mf4_t test___riscv_vadc(vint16mf4_t op1,int16_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vint16mf2_t test___riscv_vadc(vint16mf2_t op1,int16_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vint16m1_t test___riscv_vadc(vint16m1_t op1,int16_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vint16m2_t test___riscv_vadc(vint16m2_t op1,int16_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vint16m4_t test___riscv_vadc(vint16m4_t op1,int16_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vint16m8_t test___riscv_vadc(vint16m8_t op1,int16_t op2,vbool2_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vint32mf2_t test___riscv_vadc(vint32mf2_t op1,int32_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vint32m1_t test___riscv_vadc(vint32m1_t op1,int32_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vint32m2_t test___riscv_vadc(vint32m2_t op1,int32_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vint32m4_t test___riscv_vadc(vint32m4_t op1,int32_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vint32m8_t test___riscv_vadc(vint32m8_t op1,int32_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vint64m1_t test___riscv_vadc(vint64m1_t op1,int64_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vint64m2_t test___riscv_vadc(vint64m2_t op1,int64_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vint64m4_t test___riscv_vadc(vint64m4_t op1,int64_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vint64m8_t test___riscv_vadc(vint64m8_t op1,int64_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vuint8mf8_t test___riscv_vadc(vuint8mf8_t op1,uint8_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vuint8mf4_t test___riscv_vadc(vuint8mf4_t op1,uint8_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vuint8mf2_t test___riscv_vadc(vuint8mf2_t op1,uint8_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vuint8m1_t test___riscv_vadc(vuint8m1_t op1,uint8_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vuint8m2_t test___riscv_vadc(vuint8m2_t op1,uint8_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vuint8m4_t test___riscv_vadc(vuint8m4_t op1,uint8_t op2,vbool2_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vuint8m8_t test___riscv_vadc(vuint8m8_t op1,uint8_t op2,vbool1_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vuint16mf4_t test___riscv_vadc(vuint16mf4_t op1,uint16_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vuint16mf2_t test___riscv_vadc(vuint16mf2_t op1,uint16_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vuint16m1_t test___riscv_vadc(vuint16m1_t op1,uint16_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vuint16m2_t test___riscv_vadc(vuint16m2_t op1,uint16_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vuint16m4_t test___riscv_vadc(vuint16m4_t op1,uint16_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vuint16m8_t test___riscv_vadc(vuint16m8_t op1,uint16_t op2,vbool2_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vuint32mf2_t test___riscv_vadc(vuint32mf2_t op1,uint32_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vuint32m1_t test___riscv_vadc(vuint32m1_t op1,uint32_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vuint32m2_t test___riscv_vadc(vuint32m2_t op1,uint32_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vuint32m4_t test___riscv_vadc(vuint32m4_t op1,uint32_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vuint32m8_t test___riscv_vadc(vuint32m8_t op1,uint32_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vuint64m1_t test___riscv_vadc(vuint64m1_t op1,uint64_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vuint64m2_t test___riscv_vadc(vuint64m2_t op1,uint64_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vuint64m4_t test___riscv_vadc(vuint64m4_t op1,uint64_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + +vuint64m8_t test___riscv_vadc(vuint64m8_t op1,uint64_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_rv64-2.C new file mode 100644 index 00000000000..304a70922ba --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_rv64-2.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadc(vint8mf8_t op1,int8_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vint8mf4_t test___riscv_vadc(vint8mf4_t op1,int8_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vint8mf2_t test___riscv_vadc(vint8mf2_t op1,int8_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vint8m1_t test___riscv_vadc(vint8m1_t op1,int8_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vint8m2_t test___riscv_vadc(vint8m2_t op1,int8_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vint8m4_t test___riscv_vadc(vint8m4_t op1,int8_t op2,vbool2_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vint8m8_t test___riscv_vadc(vint8m8_t op1,int8_t op2,vbool1_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vint16mf4_t test___riscv_vadc(vint16mf4_t op1,int16_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vint16mf2_t test___riscv_vadc(vint16mf2_t op1,int16_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vint16m1_t test___riscv_vadc(vint16m1_t op1,int16_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vint16m2_t test___riscv_vadc(vint16m2_t op1,int16_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vint16m4_t test___riscv_vadc(vint16m4_t op1,int16_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vint16m8_t test___riscv_vadc(vint16m8_t op1,int16_t op2,vbool2_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vint32mf2_t test___riscv_vadc(vint32mf2_t op1,int32_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vint32m1_t test___riscv_vadc(vint32m1_t op1,int32_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vint32m2_t test___riscv_vadc(vint32m2_t op1,int32_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vint32m4_t test___riscv_vadc(vint32m4_t op1,int32_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vint32m8_t test___riscv_vadc(vint32m8_t op1,int32_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vint64m1_t test___riscv_vadc(vint64m1_t op1,int64_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vint64m2_t test___riscv_vadc(vint64m2_t op1,int64_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vint64m4_t test___riscv_vadc(vint64m4_t op1,int64_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vint64m8_t test___riscv_vadc(vint64m8_t op1,int64_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vuint8mf8_t test___riscv_vadc(vuint8mf8_t op1,uint8_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vuint8mf4_t test___riscv_vadc(vuint8mf4_t op1,uint8_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vuint8mf2_t test___riscv_vadc(vuint8mf2_t op1,uint8_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vuint8m1_t test___riscv_vadc(vuint8m1_t op1,uint8_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vuint8m2_t test___riscv_vadc(vuint8m2_t op1,uint8_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vuint8m4_t test___riscv_vadc(vuint8m4_t op1,uint8_t op2,vbool2_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vuint8m8_t test___riscv_vadc(vuint8m8_t op1,uint8_t op2,vbool1_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vuint16mf4_t test___riscv_vadc(vuint16mf4_t op1,uint16_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vuint16mf2_t test___riscv_vadc(vuint16mf2_t op1,uint16_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vuint16m1_t test___riscv_vadc(vuint16m1_t op1,uint16_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vuint16m2_t test___riscv_vadc(vuint16m2_t op1,uint16_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vuint16m4_t test___riscv_vadc(vuint16m4_t op1,uint16_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vuint16m8_t test___riscv_vadc(vuint16m8_t op1,uint16_t op2,vbool2_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vuint32mf2_t test___riscv_vadc(vuint32mf2_t op1,uint32_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vuint32m1_t test___riscv_vadc(vuint32m1_t op1,uint32_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vuint32m2_t test___riscv_vadc(vuint32m2_t op1,uint32_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vuint32m4_t test___riscv_vadc(vuint32m4_t op1,uint32_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vuint32m8_t test___riscv_vadc(vuint32m8_t op1,uint32_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vuint64m1_t test___riscv_vadc(vuint64m1_t op1,uint64_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vuint64m2_t test___riscv_vadc(vuint64m2_t op1,uint64_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vuint64m4_t test___riscv_vadc(vuint64m4_t op1,uint64_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + +vuint64m8_t test___riscv_vadc(vuint64m8_t op1,uint64_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_rv64-3.C new file mode 100644 index 00000000000..60618b5e49b --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_rv64-3.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test___riscv_vadc(vint8mf8_t op1,int8_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vint8mf4_t test___riscv_vadc(vint8mf4_t op1,int8_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vint8mf2_t test___riscv_vadc(vint8mf2_t op1,int8_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vint8m1_t test___riscv_vadc(vint8m1_t op1,int8_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vint8m2_t test___riscv_vadc(vint8m2_t op1,int8_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vint8m4_t test___riscv_vadc(vint8m4_t op1,int8_t op2,vbool2_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vint8m8_t test___riscv_vadc(vint8m8_t op1,int8_t op2,vbool1_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vint16mf4_t test___riscv_vadc(vint16mf4_t op1,int16_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vint16mf2_t test___riscv_vadc(vint16mf2_t op1,int16_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vint16m1_t test___riscv_vadc(vint16m1_t op1,int16_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vint16m2_t test___riscv_vadc(vint16m2_t op1,int16_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vint16m4_t test___riscv_vadc(vint16m4_t op1,int16_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vint16m8_t test___riscv_vadc(vint16m8_t op1,int16_t op2,vbool2_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vint32mf2_t test___riscv_vadc(vint32mf2_t op1,int32_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vint32m1_t test___riscv_vadc(vint32m1_t op1,int32_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vint32m2_t test___riscv_vadc(vint32m2_t op1,int32_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vint32m4_t test___riscv_vadc(vint32m4_t op1,int32_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vint32m8_t test___riscv_vadc(vint32m8_t op1,int32_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vint64m1_t test___riscv_vadc(vint64m1_t op1,int64_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vint64m2_t test___riscv_vadc(vint64m2_t op1,int64_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vint64m4_t test___riscv_vadc(vint64m4_t op1,int64_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vint64m8_t test___riscv_vadc(vint64m8_t op1,int64_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vuint8mf8_t test___riscv_vadc(vuint8mf8_t op1,uint8_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vuint8mf4_t test___riscv_vadc(vuint8mf4_t op1,uint8_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vuint8mf2_t test___riscv_vadc(vuint8mf2_t op1,uint8_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vuint8m1_t test___riscv_vadc(vuint8m1_t op1,uint8_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vuint8m2_t test___riscv_vadc(vuint8m2_t op1,uint8_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vuint8m4_t test___riscv_vadc(vuint8m4_t op1,uint8_t op2,vbool2_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vuint8m8_t test___riscv_vadc(vuint8m8_t op1,uint8_t op2,vbool1_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vuint16mf4_t test___riscv_vadc(vuint16mf4_t op1,uint16_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vuint16mf2_t test___riscv_vadc(vuint16mf2_t op1,uint16_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vuint16m1_t test___riscv_vadc(vuint16m1_t op1,uint16_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vuint16m2_t test___riscv_vadc(vuint16m2_t op1,uint16_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vuint16m4_t test___riscv_vadc(vuint16m4_t op1,uint16_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vuint16m8_t test___riscv_vadc(vuint16m8_t op1,uint16_t op2,vbool2_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vuint32mf2_t test___riscv_vadc(vuint32mf2_t op1,uint32_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vuint32m1_t test___riscv_vadc(vuint32m1_t op1,uint32_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vuint32m2_t test___riscv_vadc(vuint32m2_t op1,uint32_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vuint32m4_t test___riscv_vadc(vuint32m4_t op1,uint32_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vuint32m8_t test___riscv_vadc(vuint32m8_t op1,uint32_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vuint64m1_t test___riscv_vadc(vuint64m1_t op1,uint64_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vuint64m2_t test___riscv_vadc(vuint64m2_t op1,uint64_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vuint64m4_t test___riscv_vadc(vuint64m4_t op1,uint64_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + +vuint64m8_t test___riscv_vadc(vuint64m8_t op1,uint64_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc(op1,op2,carryin,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_tu_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_tu_rv32-1.C new file mode 100644 index 00000000000..f290720169a --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_tu_rv32-1.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test____riscv_vadc_tu(vint8mf8_t maskedoff,vint8mf8_t op1,int8_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vint8mf4_t test____riscv_vadc_tu(vint8mf4_t maskedoff,vint8mf4_t op1,int8_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vint8mf2_t test____riscv_vadc_tu(vint8mf2_t maskedoff,vint8mf2_t op1,int8_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vint8m1_t test____riscv_vadc_tu(vint8m1_t maskedoff,vint8m1_t op1,int8_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vint8m2_t test____riscv_vadc_tu(vint8m2_t maskedoff,vint8m2_t op1,int8_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vint8m4_t test____riscv_vadc_tu(vint8m4_t maskedoff,vint8m4_t op1,int8_t op2,vbool2_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vint8m8_t test____riscv_vadc_tu(vint8m8_t maskedoff,vint8m8_t op1,int8_t op2,vbool1_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vint16mf4_t test____riscv_vadc_tu(vint16mf4_t maskedoff,vint16mf4_t op1,int16_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vint16mf2_t test____riscv_vadc_tu(vint16mf2_t maskedoff,vint16mf2_t op1,int16_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vint16m1_t test____riscv_vadc_tu(vint16m1_t maskedoff,vint16m1_t op1,int16_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vint16m2_t test____riscv_vadc_tu(vint16m2_t maskedoff,vint16m2_t op1,int16_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vint16m4_t test____riscv_vadc_tu(vint16m4_t maskedoff,vint16m4_t op1,int16_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vint16m8_t test____riscv_vadc_tu(vint16m8_t maskedoff,vint16m8_t op1,int16_t op2,vbool2_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vint32mf2_t test____riscv_vadc_tu(vint32mf2_t maskedoff,vint32mf2_t op1,int32_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vint32m1_t test____riscv_vadc_tu(vint32m1_t maskedoff,vint32m1_t op1,int32_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vint32m2_t test____riscv_vadc_tu(vint32m2_t maskedoff,vint32m2_t op1,int32_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vint32m4_t test____riscv_vadc_tu(vint32m4_t maskedoff,vint32m4_t op1,int32_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vint32m8_t test____riscv_vadc_tu(vint32m8_t maskedoff,vint32m8_t op1,int32_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vint64m1_t test____riscv_vadc_tu(vint64m1_t maskedoff,vint64m1_t op1,int64_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vint64m2_t test____riscv_vadc_tu(vint64m2_t maskedoff,vint64m2_t op1,int64_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vint64m4_t test____riscv_vadc_tu(vint64m4_t maskedoff,vint64m4_t op1,int64_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vint64m8_t test____riscv_vadc_tu(vint64m8_t maskedoff,vint64m8_t op1,int64_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vuint8mf8_t test____riscv_vadc_tu(vuint8mf8_t maskedoff,vuint8mf8_t op1,uint8_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vuint8mf4_t test____riscv_vadc_tu(vuint8mf4_t maskedoff,vuint8mf4_t op1,uint8_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vuint8mf2_t test____riscv_vadc_tu(vuint8mf2_t maskedoff,vuint8mf2_t op1,uint8_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vuint8m1_t test____riscv_vadc_tu(vuint8m1_t maskedoff,vuint8m1_t op1,uint8_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vuint8m2_t test____riscv_vadc_tu(vuint8m2_t maskedoff,vuint8m2_t op1,uint8_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vuint8m4_t test____riscv_vadc_tu(vuint8m4_t maskedoff,vuint8m4_t op1,uint8_t op2,vbool2_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vuint8m8_t test____riscv_vadc_tu(vuint8m8_t maskedoff,vuint8m8_t op1,uint8_t op2,vbool1_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vuint16mf4_t test____riscv_vadc_tu(vuint16mf4_t maskedoff,vuint16mf4_t op1,uint16_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vuint16mf2_t test____riscv_vadc_tu(vuint16mf2_t maskedoff,vuint16mf2_t op1,uint16_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vuint16m1_t test____riscv_vadc_tu(vuint16m1_t maskedoff,vuint16m1_t op1,uint16_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vuint16m2_t test____riscv_vadc_tu(vuint16m2_t maskedoff,vuint16m2_t op1,uint16_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vuint16m4_t test____riscv_vadc_tu(vuint16m4_t maskedoff,vuint16m4_t op1,uint16_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vuint16m8_t test____riscv_vadc_tu(vuint16m8_t maskedoff,vuint16m8_t op1,uint16_t op2,vbool2_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vuint32mf2_t test____riscv_vadc_tu(vuint32mf2_t maskedoff,vuint32mf2_t op1,uint32_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vuint32m1_t test____riscv_vadc_tu(vuint32m1_t maskedoff,vuint32m1_t op1,uint32_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vuint32m2_t test____riscv_vadc_tu(vuint32m2_t maskedoff,vuint32m2_t op1,uint32_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vuint32m4_t test____riscv_vadc_tu(vuint32m4_t maskedoff,vuint32m4_t op1,uint32_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vuint32m8_t test____riscv_vadc_tu(vuint32m8_t maskedoff,vuint32m8_t op1,uint32_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vuint64m1_t test____riscv_vadc_tu(vuint64m1_t maskedoff,vuint64m1_t op1,uint64_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vuint64m2_t test____riscv_vadc_tu(vuint64m2_t maskedoff,vuint64m2_t op1,uint64_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vuint64m4_t test____riscv_vadc_tu(vuint64m4_t maskedoff,vuint64m4_t op1,uint64_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vuint64m8_t test____riscv_vadc_tu(vuint64m8_t maskedoff,vuint64m8_t op1,uint64_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_tu_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_tu_rv32-2.C new file mode 100644 index 00000000000..b04fc74e2a6 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_tu_rv32-2.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test____riscv_vadc_tu(vint8mf8_t maskedoff,vint8mf8_t op1,int8_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vint8mf4_t test____riscv_vadc_tu(vint8mf4_t maskedoff,vint8mf4_t op1,int8_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vint8mf2_t test____riscv_vadc_tu(vint8mf2_t maskedoff,vint8mf2_t op1,int8_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vint8m1_t test____riscv_vadc_tu(vint8m1_t maskedoff,vint8m1_t op1,int8_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vint8m2_t test____riscv_vadc_tu(vint8m2_t maskedoff,vint8m2_t op1,int8_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vint8m4_t test____riscv_vadc_tu(vint8m4_t maskedoff,vint8m4_t op1,int8_t op2,vbool2_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vint8m8_t test____riscv_vadc_tu(vint8m8_t maskedoff,vint8m8_t op1,int8_t op2,vbool1_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vint16mf4_t test____riscv_vadc_tu(vint16mf4_t maskedoff,vint16mf4_t op1,int16_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vint16mf2_t test____riscv_vadc_tu(vint16mf2_t maskedoff,vint16mf2_t op1,int16_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vint16m1_t test____riscv_vadc_tu(vint16m1_t maskedoff,vint16m1_t op1,int16_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vint16m2_t test____riscv_vadc_tu(vint16m2_t maskedoff,vint16m2_t op1,int16_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vint16m4_t test____riscv_vadc_tu(vint16m4_t maskedoff,vint16m4_t op1,int16_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vint16m8_t test____riscv_vadc_tu(vint16m8_t maskedoff,vint16m8_t op1,int16_t op2,vbool2_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vint32mf2_t test____riscv_vadc_tu(vint32mf2_t maskedoff,vint32mf2_t op1,int32_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vint32m1_t test____riscv_vadc_tu(vint32m1_t maskedoff,vint32m1_t op1,int32_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vint32m2_t test____riscv_vadc_tu(vint32m2_t maskedoff,vint32m2_t op1,int32_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vint32m4_t test____riscv_vadc_tu(vint32m4_t maskedoff,vint32m4_t op1,int32_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vint32m8_t test____riscv_vadc_tu(vint32m8_t maskedoff,vint32m8_t op1,int32_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vint64m1_t test____riscv_vadc_tu(vint64m1_t maskedoff,vint64m1_t op1,int64_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vint64m2_t test____riscv_vadc_tu(vint64m2_t maskedoff,vint64m2_t op1,int64_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vint64m4_t test____riscv_vadc_tu(vint64m4_t maskedoff,vint64m4_t op1,int64_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vint64m8_t test____riscv_vadc_tu(vint64m8_t maskedoff,vint64m8_t op1,int64_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vuint8mf8_t test____riscv_vadc_tu(vuint8mf8_t maskedoff,vuint8mf8_t op1,uint8_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vuint8mf4_t test____riscv_vadc_tu(vuint8mf4_t maskedoff,vuint8mf4_t op1,uint8_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vuint8mf2_t test____riscv_vadc_tu(vuint8mf2_t maskedoff,vuint8mf2_t op1,uint8_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vuint8m1_t test____riscv_vadc_tu(vuint8m1_t maskedoff,vuint8m1_t op1,uint8_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vuint8m2_t test____riscv_vadc_tu(vuint8m2_t maskedoff,vuint8m2_t op1,uint8_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vuint8m4_t test____riscv_vadc_tu(vuint8m4_t maskedoff,vuint8m4_t op1,uint8_t op2,vbool2_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vuint8m8_t test____riscv_vadc_tu(vuint8m8_t maskedoff,vuint8m8_t op1,uint8_t op2,vbool1_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vuint16mf4_t test____riscv_vadc_tu(vuint16mf4_t maskedoff,vuint16mf4_t op1,uint16_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vuint16mf2_t test____riscv_vadc_tu(vuint16mf2_t maskedoff,vuint16mf2_t op1,uint16_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vuint16m1_t test____riscv_vadc_tu(vuint16m1_t maskedoff,vuint16m1_t op1,uint16_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vuint16m2_t test____riscv_vadc_tu(vuint16m2_t maskedoff,vuint16m2_t op1,uint16_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vuint16m4_t test____riscv_vadc_tu(vuint16m4_t maskedoff,vuint16m4_t op1,uint16_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vuint16m8_t test____riscv_vadc_tu(vuint16m8_t maskedoff,vuint16m8_t op1,uint16_t op2,vbool2_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vuint32mf2_t test____riscv_vadc_tu(vuint32mf2_t maskedoff,vuint32mf2_t op1,uint32_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vuint32m1_t test____riscv_vadc_tu(vuint32m1_t maskedoff,vuint32m1_t op1,uint32_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vuint32m2_t test____riscv_vadc_tu(vuint32m2_t maskedoff,vuint32m2_t op1,uint32_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vuint32m4_t test____riscv_vadc_tu(vuint32m4_t maskedoff,vuint32m4_t op1,uint32_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vuint32m8_t test____riscv_vadc_tu(vuint32m8_t maskedoff,vuint32m8_t op1,uint32_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vuint64m1_t test____riscv_vadc_tu(vuint64m1_t maskedoff,vuint64m1_t op1,uint64_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vuint64m2_t test____riscv_vadc_tu(vuint64m2_t maskedoff,vuint64m2_t op1,uint64_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vuint64m4_t test____riscv_vadc_tu(vuint64m4_t maskedoff,vuint64m4_t op1,uint64_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vuint64m8_t test____riscv_vadc_tu(vuint64m8_t maskedoff,vuint64m8_t op1,uint64_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_tu_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_tu_rv32-3.C new file mode 100644 index 00000000000..ce0fc4d43c3 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_tu_rv32-3.C @@ -0,0 +1,289 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test____riscv_vadc_tu(vint8mf8_t maskedoff,vint8mf8_t op1,int8_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vint8mf4_t test____riscv_vadc_tu(vint8mf4_t maskedoff,vint8mf4_t op1,int8_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vint8mf2_t test____riscv_vadc_tu(vint8mf2_t maskedoff,vint8mf2_t op1,int8_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vint8m1_t test____riscv_vadc_tu(vint8m1_t maskedoff,vint8m1_t op1,int8_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vint8m2_t test____riscv_vadc_tu(vint8m2_t maskedoff,vint8m2_t op1,int8_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vint8m4_t test____riscv_vadc_tu(vint8m4_t maskedoff,vint8m4_t op1,int8_t op2,vbool2_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vint8m8_t test____riscv_vadc_tu(vint8m8_t maskedoff,vint8m8_t op1,int8_t op2,vbool1_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vint16mf4_t test____riscv_vadc_tu(vint16mf4_t maskedoff,vint16mf4_t op1,int16_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vint16mf2_t test____riscv_vadc_tu(vint16mf2_t maskedoff,vint16mf2_t op1,int16_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vint16m1_t test____riscv_vadc_tu(vint16m1_t maskedoff,vint16m1_t op1,int16_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vint16m2_t test____riscv_vadc_tu(vint16m2_t maskedoff,vint16m2_t op1,int16_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vint16m4_t test____riscv_vadc_tu(vint16m4_t maskedoff,vint16m4_t op1,int16_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vint16m8_t test____riscv_vadc_tu(vint16m8_t maskedoff,vint16m8_t op1,int16_t op2,vbool2_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vint32mf2_t test____riscv_vadc_tu(vint32mf2_t maskedoff,vint32mf2_t op1,int32_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vint32m1_t test____riscv_vadc_tu(vint32m1_t maskedoff,vint32m1_t op1,int32_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vint32m2_t test____riscv_vadc_tu(vint32m2_t maskedoff,vint32m2_t op1,int32_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vint32m4_t test____riscv_vadc_tu(vint32m4_t maskedoff,vint32m4_t op1,int32_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vint32m8_t test____riscv_vadc_tu(vint32m8_t maskedoff,vint32m8_t op1,int32_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vint64m1_t test____riscv_vadc_tu(vint64m1_t maskedoff,vint64m1_t op1,int64_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vint64m2_t test____riscv_vadc_tu(vint64m2_t maskedoff,vint64m2_t op1,int64_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vint64m4_t test____riscv_vadc_tu(vint64m4_t maskedoff,vint64m4_t op1,int64_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vint64m8_t test____riscv_vadc_tu(vint64m8_t maskedoff,vint64m8_t op1,int64_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vuint8mf8_t test____riscv_vadc_tu(vuint8mf8_t maskedoff,vuint8mf8_t op1,uint8_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vuint8mf4_t test____riscv_vadc_tu(vuint8mf4_t maskedoff,vuint8mf4_t op1,uint8_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vuint8mf2_t test____riscv_vadc_tu(vuint8mf2_t maskedoff,vuint8mf2_t op1,uint8_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vuint8m1_t test____riscv_vadc_tu(vuint8m1_t maskedoff,vuint8m1_t op1,uint8_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vuint8m2_t test____riscv_vadc_tu(vuint8m2_t maskedoff,vuint8m2_t op1,uint8_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vuint8m4_t test____riscv_vadc_tu(vuint8m4_t maskedoff,vuint8m4_t op1,uint8_t op2,vbool2_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vuint8m8_t test____riscv_vadc_tu(vuint8m8_t maskedoff,vuint8m8_t op1,uint8_t op2,vbool1_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vuint16mf4_t test____riscv_vadc_tu(vuint16mf4_t maskedoff,vuint16mf4_t op1,uint16_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vuint16mf2_t test____riscv_vadc_tu(vuint16mf2_t maskedoff,vuint16mf2_t op1,uint16_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vuint16m1_t test____riscv_vadc_tu(vuint16m1_t maskedoff,vuint16m1_t op1,uint16_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vuint16m2_t test____riscv_vadc_tu(vuint16m2_t maskedoff,vuint16m2_t op1,uint16_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vuint16m4_t test____riscv_vadc_tu(vuint16m4_t maskedoff,vuint16m4_t op1,uint16_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vuint16m8_t test____riscv_vadc_tu(vuint16m8_t maskedoff,vuint16m8_t op1,uint16_t op2,vbool2_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vuint32mf2_t test____riscv_vadc_tu(vuint32mf2_t maskedoff,vuint32mf2_t op1,uint32_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vuint32m1_t test____riscv_vadc_tu(vuint32m1_t maskedoff,vuint32m1_t op1,uint32_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vuint32m2_t test____riscv_vadc_tu(vuint32m2_t maskedoff,vuint32m2_t op1,uint32_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vuint32m4_t test____riscv_vadc_tu(vuint32m4_t maskedoff,vuint32m4_t op1,uint32_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vuint32m8_t test____riscv_vadc_tu(vuint32m8_t maskedoff,vuint32m8_t op1,uint32_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vuint64m1_t test____riscv_vadc_tu(vuint64m1_t maskedoff,vuint64m1_t op1,uint64_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vuint64m2_t test____riscv_vadc_tu(vuint64m2_t maskedoff,vuint64m2_t op1,uint64_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vuint64m4_t test____riscv_vadc_tu(vuint64m4_t maskedoff,vuint64m4_t op1,uint64_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vuint64m8_t test____riscv_vadc_tu(vuint64m8_t maskedoff,vuint64m8_t op1,uint64_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vadc\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 8 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_tu_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_tu_rv64-1.C new file mode 100644 index 00000000000..59f5a81b9b0 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_tu_rv64-1.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test____riscv_vadc_tu(vint8mf8_t maskedoff,vint8mf8_t op1,int8_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vint8mf4_t test____riscv_vadc_tu(vint8mf4_t maskedoff,vint8mf4_t op1,int8_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vint8mf2_t test____riscv_vadc_tu(vint8mf2_t maskedoff,vint8mf2_t op1,int8_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vint8m1_t test____riscv_vadc_tu(vint8m1_t maskedoff,vint8m1_t op1,int8_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vint8m2_t test____riscv_vadc_tu(vint8m2_t maskedoff,vint8m2_t op1,int8_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vint8m4_t test____riscv_vadc_tu(vint8m4_t maskedoff,vint8m4_t op1,int8_t op2,vbool2_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vint8m8_t test____riscv_vadc_tu(vint8m8_t maskedoff,vint8m8_t op1,int8_t op2,vbool1_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vint16mf4_t test____riscv_vadc_tu(vint16mf4_t maskedoff,vint16mf4_t op1,int16_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vint16mf2_t test____riscv_vadc_tu(vint16mf2_t maskedoff,vint16mf2_t op1,int16_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vint16m1_t test____riscv_vadc_tu(vint16m1_t maskedoff,vint16m1_t op1,int16_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vint16m2_t test____riscv_vadc_tu(vint16m2_t maskedoff,vint16m2_t op1,int16_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vint16m4_t test____riscv_vadc_tu(vint16m4_t maskedoff,vint16m4_t op1,int16_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vint16m8_t test____riscv_vadc_tu(vint16m8_t maskedoff,vint16m8_t op1,int16_t op2,vbool2_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vint32mf2_t test____riscv_vadc_tu(vint32mf2_t maskedoff,vint32mf2_t op1,int32_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vint32m1_t test____riscv_vadc_tu(vint32m1_t maskedoff,vint32m1_t op1,int32_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vint32m2_t test____riscv_vadc_tu(vint32m2_t maskedoff,vint32m2_t op1,int32_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vint32m4_t test____riscv_vadc_tu(vint32m4_t maskedoff,vint32m4_t op1,int32_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vint32m8_t test____riscv_vadc_tu(vint32m8_t maskedoff,vint32m8_t op1,int32_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vint64m1_t test____riscv_vadc_tu(vint64m1_t maskedoff,vint64m1_t op1,int64_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vint64m2_t test____riscv_vadc_tu(vint64m2_t maskedoff,vint64m2_t op1,int64_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vint64m4_t test____riscv_vadc_tu(vint64m4_t maskedoff,vint64m4_t op1,int64_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vint64m8_t test____riscv_vadc_tu(vint64m8_t maskedoff,vint64m8_t op1,int64_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vuint8mf8_t test____riscv_vadc_tu(vuint8mf8_t maskedoff,vuint8mf8_t op1,uint8_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vuint8mf4_t test____riscv_vadc_tu(vuint8mf4_t maskedoff,vuint8mf4_t op1,uint8_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vuint8mf2_t test____riscv_vadc_tu(vuint8mf2_t maskedoff,vuint8mf2_t op1,uint8_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vuint8m1_t test____riscv_vadc_tu(vuint8m1_t maskedoff,vuint8m1_t op1,uint8_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vuint8m2_t test____riscv_vadc_tu(vuint8m2_t maskedoff,vuint8m2_t op1,uint8_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vuint8m4_t test____riscv_vadc_tu(vuint8m4_t maskedoff,vuint8m4_t op1,uint8_t op2,vbool2_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vuint8m8_t test____riscv_vadc_tu(vuint8m8_t maskedoff,vuint8m8_t op1,uint8_t op2,vbool1_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vuint16mf4_t test____riscv_vadc_tu(vuint16mf4_t maskedoff,vuint16mf4_t op1,uint16_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vuint16mf2_t test____riscv_vadc_tu(vuint16mf2_t maskedoff,vuint16mf2_t op1,uint16_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vuint16m1_t test____riscv_vadc_tu(vuint16m1_t maskedoff,vuint16m1_t op1,uint16_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vuint16m2_t test____riscv_vadc_tu(vuint16m2_t maskedoff,vuint16m2_t op1,uint16_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vuint16m4_t test____riscv_vadc_tu(vuint16m4_t maskedoff,vuint16m4_t op1,uint16_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vuint16m8_t test____riscv_vadc_tu(vuint16m8_t maskedoff,vuint16m8_t op1,uint16_t op2,vbool2_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vuint32mf2_t test____riscv_vadc_tu(vuint32mf2_t maskedoff,vuint32mf2_t op1,uint32_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vuint32m1_t test____riscv_vadc_tu(vuint32m1_t maskedoff,vuint32m1_t op1,uint32_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vuint32m2_t test____riscv_vadc_tu(vuint32m2_t maskedoff,vuint32m2_t op1,uint32_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vuint32m4_t test____riscv_vadc_tu(vuint32m4_t maskedoff,vuint32m4_t op1,uint32_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vuint32m8_t test____riscv_vadc_tu(vuint32m8_t maskedoff,vuint32m8_t op1,uint32_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vuint64m1_t test____riscv_vadc_tu(vuint64m1_t maskedoff,vuint64m1_t op1,uint64_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vuint64m2_t test____riscv_vadc_tu(vuint64m2_t maskedoff,vuint64m2_t op1,uint64_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vuint64m4_t test____riscv_vadc_tu(vuint64m4_t maskedoff,vuint64m4_t op1,uint64_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + +vuint64m8_t test____riscv_vadc_tu(vuint64m8_t maskedoff,vuint64m8_t op1,uint64_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_tu_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_tu_rv64-2.C new file mode 100644 index 00000000000..b44e2195599 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_tu_rv64-2.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test____riscv_vadc_tu(vint8mf8_t maskedoff,vint8mf8_t op1,int8_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vint8mf4_t test____riscv_vadc_tu(vint8mf4_t maskedoff,vint8mf4_t op1,int8_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vint8mf2_t test____riscv_vadc_tu(vint8mf2_t maskedoff,vint8mf2_t op1,int8_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vint8m1_t test____riscv_vadc_tu(vint8m1_t maskedoff,vint8m1_t op1,int8_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vint8m2_t test____riscv_vadc_tu(vint8m2_t maskedoff,vint8m2_t op1,int8_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vint8m4_t test____riscv_vadc_tu(vint8m4_t maskedoff,vint8m4_t op1,int8_t op2,vbool2_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vint8m8_t test____riscv_vadc_tu(vint8m8_t maskedoff,vint8m8_t op1,int8_t op2,vbool1_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vint16mf4_t test____riscv_vadc_tu(vint16mf4_t maskedoff,vint16mf4_t op1,int16_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vint16mf2_t test____riscv_vadc_tu(vint16mf2_t maskedoff,vint16mf2_t op1,int16_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vint16m1_t test____riscv_vadc_tu(vint16m1_t maskedoff,vint16m1_t op1,int16_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vint16m2_t test____riscv_vadc_tu(vint16m2_t maskedoff,vint16m2_t op1,int16_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vint16m4_t test____riscv_vadc_tu(vint16m4_t maskedoff,vint16m4_t op1,int16_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vint16m8_t test____riscv_vadc_tu(vint16m8_t maskedoff,vint16m8_t op1,int16_t op2,vbool2_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vint32mf2_t test____riscv_vadc_tu(vint32mf2_t maskedoff,vint32mf2_t op1,int32_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vint32m1_t test____riscv_vadc_tu(vint32m1_t maskedoff,vint32m1_t op1,int32_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vint32m2_t test____riscv_vadc_tu(vint32m2_t maskedoff,vint32m2_t op1,int32_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vint32m4_t test____riscv_vadc_tu(vint32m4_t maskedoff,vint32m4_t op1,int32_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vint32m8_t test____riscv_vadc_tu(vint32m8_t maskedoff,vint32m8_t op1,int32_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vint64m1_t test____riscv_vadc_tu(vint64m1_t maskedoff,vint64m1_t op1,int64_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vint64m2_t test____riscv_vadc_tu(vint64m2_t maskedoff,vint64m2_t op1,int64_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vint64m4_t test____riscv_vadc_tu(vint64m4_t maskedoff,vint64m4_t op1,int64_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vint64m8_t test____riscv_vadc_tu(vint64m8_t maskedoff,vint64m8_t op1,int64_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vuint8mf8_t test____riscv_vadc_tu(vuint8mf8_t maskedoff,vuint8mf8_t op1,uint8_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vuint8mf4_t test____riscv_vadc_tu(vuint8mf4_t maskedoff,vuint8mf4_t op1,uint8_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vuint8mf2_t test____riscv_vadc_tu(vuint8mf2_t maskedoff,vuint8mf2_t op1,uint8_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vuint8m1_t test____riscv_vadc_tu(vuint8m1_t maskedoff,vuint8m1_t op1,uint8_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vuint8m2_t test____riscv_vadc_tu(vuint8m2_t maskedoff,vuint8m2_t op1,uint8_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vuint8m4_t test____riscv_vadc_tu(vuint8m4_t maskedoff,vuint8m4_t op1,uint8_t op2,vbool2_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vuint8m8_t test____riscv_vadc_tu(vuint8m8_t maskedoff,vuint8m8_t op1,uint8_t op2,vbool1_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vuint16mf4_t test____riscv_vadc_tu(vuint16mf4_t maskedoff,vuint16mf4_t op1,uint16_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vuint16mf2_t test____riscv_vadc_tu(vuint16mf2_t maskedoff,vuint16mf2_t op1,uint16_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vuint16m1_t test____riscv_vadc_tu(vuint16m1_t maskedoff,vuint16m1_t op1,uint16_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vuint16m2_t test____riscv_vadc_tu(vuint16m2_t maskedoff,vuint16m2_t op1,uint16_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vuint16m4_t test____riscv_vadc_tu(vuint16m4_t maskedoff,vuint16m4_t op1,uint16_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vuint16m8_t test____riscv_vadc_tu(vuint16m8_t maskedoff,vuint16m8_t op1,uint16_t op2,vbool2_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vuint32mf2_t test____riscv_vadc_tu(vuint32mf2_t maskedoff,vuint32mf2_t op1,uint32_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vuint32m1_t test____riscv_vadc_tu(vuint32m1_t maskedoff,vuint32m1_t op1,uint32_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vuint32m2_t test____riscv_vadc_tu(vuint32m2_t maskedoff,vuint32m2_t op1,uint32_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vuint32m4_t test____riscv_vadc_tu(vuint32m4_t maskedoff,vuint32m4_t op1,uint32_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vuint32m8_t test____riscv_vadc_tu(vuint32m8_t maskedoff,vuint32m8_t op1,uint32_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vuint64m1_t test____riscv_vadc_tu(vuint64m1_t maskedoff,vuint64m1_t op1,uint64_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vuint64m2_t test____riscv_vadc_tu(vuint64m2_t maskedoff,vuint64m2_t op1,uint64_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vuint64m4_t test____riscv_vadc_tu(vuint64m4_t maskedoff,vuint64m4_t op1,uint64_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + +vuint64m8_t test____riscv_vadc_tu(vuint64m8_t maskedoff,vuint64m8_t op1,uint64_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_tu_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_tu_rv64-3.C new file mode 100644 index 00000000000..ed58ccf439d --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vadc_vxm_tu_rv64-3.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint8mf8_t test____riscv_vadc_tu(vint8mf8_t maskedoff,vint8mf8_t op1,int8_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vint8mf4_t test____riscv_vadc_tu(vint8mf4_t maskedoff,vint8mf4_t op1,int8_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vint8mf2_t test____riscv_vadc_tu(vint8mf2_t maskedoff,vint8mf2_t op1,int8_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vint8m1_t test____riscv_vadc_tu(vint8m1_t maskedoff,vint8m1_t op1,int8_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vint8m2_t test____riscv_vadc_tu(vint8m2_t maskedoff,vint8m2_t op1,int8_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vint8m4_t test____riscv_vadc_tu(vint8m4_t maskedoff,vint8m4_t op1,int8_t op2,vbool2_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vint8m8_t test____riscv_vadc_tu(vint8m8_t maskedoff,vint8m8_t op1,int8_t op2,vbool1_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vint16mf4_t test____riscv_vadc_tu(vint16mf4_t maskedoff,vint16mf4_t op1,int16_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vint16mf2_t test____riscv_vadc_tu(vint16mf2_t maskedoff,vint16mf2_t op1,int16_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vint16m1_t test____riscv_vadc_tu(vint16m1_t maskedoff,vint16m1_t op1,int16_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vint16m2_t test____riscv_vadc_tu(vint16m2_t maskedoff,vint16m2_t op1,int16_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vint16m4_t test____riscv_vadc_tu(vint16m4_t maskedoff,vint16m4_t op1,int16_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vint16m8_t test____riscv_vadc_tu(vint16m8_t maskedoff,vint16m8_t op1,int16_t op2,vbool2_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vint32mf2_t test____riscv_vadc_tu(vint32mf2_t maskedoff,vint32mf2_t op1,int32_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vint32m1_t test____riscv_vadc_tu(vint32m1_t maskedoff,vint32m1_t op1,int32_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vint32m2_t test____riscv_vadc_tu(vint32m2_t maskedoff,vint32m2_t op1,int32_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vint32m4_t test____riscv_vadc_tu(vint32m4_t maskedoff,vint32m4_t op1,int32_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vint32m8_t test____riscv_vadc_tu(vint32m8_t maskedoff,vint32m8_t op1,int32_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vint64m1_t test____riscv_vadc_tu(vint64m1_t maskedoff,vint64m1_t op1,int64_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vint64m2_t test____riscv_vadc_tu(vint64m2_t maskedoff,vint64m2_t op1,int64_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vint64m4_t test____riscv_vadc_tu(vint64m4_t maskedoff,vint64m4_t op1,int64_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vint64m8_t test____riscv_vadc_tu(vint64m8_t maskedoff,vint64m8_t op1,int64_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vuint8mf8_t test____riscv_vadc_tu(vuint8mf8_t maskedoff,vuint8mf8_t op1,uint8_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vuint8mf4_t test____riscv_vadc_tu(vuint8mf4_t maskedoff,vuint8mf4_t op1,uint8_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vuint8mf2_t test____riscv_vadc_tu(vuint8mf2_t maskedoff,vuint8mf2_t op1,uint8_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vuint8m1_t test____riscv_vadc_tu(vuint8m1_t maskedoff,vuint8m1_t op1,uint8_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vuint8m2_t test____riscv_vadc_tu(vuint8m2_t maskedoff,vuint8m2_t op1,uint8_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vuint8m4_t test____riscv_vadc_tu(vuint8m4_t maskedoff,vuint8m4_t op1,uint8_t op2,vbool2_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vuint8m8_t test____riscv_vadc_tu(vuint8m8_t maskedoff,vuint8m8_t op1,uint8_t op2,vbool1_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vuint16mf4_t test____riscv_vadc_tu(vuint16mf4_t maskedoff,vuint16mf4_t op1,uint16_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vuint16mf2_t test____riscv_vadc_tu(vuint16mf2_t maskedoff,vuint16mf2_t op1,uint16_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vuint16m1_t test____riscv_vadc_tu(vuint16m1_t maskedoff,vuint16m1_t op1,uint16_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vuint16m2_t test____riscv_vadc_tu(vuint16m2_t maskedoff,vuint16m2_t op1,uint16_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vuint16m4_t test____riscv_vadc_tu(vuint16m4_t maskedoff,vuint16m4_t op1,uint16_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vuint16m8_t test____riscv_vadc_tu(vuint16m8_t maskedoff,vuint16m8_t op1,uint16_t op2,vbool2_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vuint32mf2_t test____riscv_vadc_tu(vuint32mf2_t maskedoff,vuint32mf2_t op1,uint32_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vuint32m1_t test____riscv_vadc_tu(vuint32m1_t maskedoff,vuint32m1_t op1,uint32_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vuint32m2_t test____riscv_vadc_tu(vuint32m2_t maskedoff,vuint32m2_t op1,uint32_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vuint32m4_t test____riscv_vadc_tu(vuint32m4_t maskedoff,vuint32m4_t op1,uint32_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vuint32m8_t test____riscv_vadc_tu(vuint32m8_t maskedoff,vuint32m8_t op1,uint32_t op2,vbool4_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vuint64m1_t test____riscv_vadc_tu(vuint64m1_t maskedoff,vuint64m1_t op1,uint64_t op2,vbool64_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vuint64m2_t test____riscv_vadc_tu(vuint64m2_t maskedoff,vuint64m2_t op1,uint64_t op2,vbool32_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vuint64m4_t test____riscv_vadc_tu(vuint64m4_t maskedoff,vuint64m4_t op1,uint64_t op2,vbool16_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + +vuint64m8_t test____riscv_vadc_tu(vuint64m8_t maskedoff,vuint64m8_t op1,uint64_t op2,vbool8_t carryin,size_t vl) +{ + return __riscv_vadc_tu(maskedoff,op1,op2,carryin,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vadc\.vxm\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v[0-9]+\s+} 2 } } */ -- 2.36.1