From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtpbgjp3.qq.com (smtpbgjp3.qq.com [54.92.39.34]) by sourceware.org (Postfix) with ESMTPS id 5D2B83858C5E for ; Wed, 8 Feb 2023 10:51:55 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 5D2B83858C5E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp69t1675853510t3mfv834 Received: from rios-cad5.localdomain ( [58.60.1.11]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 08 Feb 2023 18:51:49 +0800 (CST) X-QQ-SSF: 01400000000000E0L000000A0000000 X-QQ-FEAT: RrZlkntZBfnVwxeatzFnF+vaoxdzPnE42bfsg06FfMWIQUAoj38oIKZGd67PB o5WZjOqiVZknPN+We4jz1VI5SJVTfe5ZrzCYfVMbyuvlqzbsaol8ie3T7dJQBo+/S3I/NXP 4LRvZx/jTbdJwXdD3ZAEd23OuunOD2Fkf4BDmsfOs4y+/cXNagZwbKU2dWlLVfluG/HOJf+ GLWydS1aeS5BDhtj3Lk7qusZ/NFKQq8VuzBdE4FyHmGKqOLSSgbdHYgcq7gDkSkyxSghcw5 4ooGDu4kNP/hoiuLf+AhQ72vOvgW++socFAJgUG3b6yKYAq62tbcPWJnQE+W9HFdJpXU1wy TGJ1x4elLerzpbLIkfS5ypCOKEi/rR2ETyuitjaSQ5wbAefUU4Dzb/ApWAFSkm6kxONrKbE X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: Fix indent Date: Wed, 8 Feb 2023 18:51:47 +0800 Message-Id: <20230208105147.214712-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-12.8 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,RCVD_IN_DNSWL_NONE,SPF_HELO_PASS,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Ju-Zhe Zhong gcc/ChangeLog: * config/riscv/vector.md: Fix indent. --- gcc/config/riscv/vector.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index aaac32efcce..7da95013156 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -765,7 +765,7 @@ "@ vlm.v\t%0,%3 vsm.v\t%3,%0 -# + # vmclr.m\t%0 vmset.m\t%0" "&& register_operand (operands[0], mode) -- 2.36.3