From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtpbgeu1.qq.com (smtpbgeu1.qq.com [52.59.177.22]) by sourceware.org (Postfix) with ESMTPS id 5CFBF38582B0 for ; Fri, 10 Feb 2023 06:55:13 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 5CFBF38582B0 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp72t1676012103taaonhul Received: from rios-cad5.localdomain ( [58.60.1.11]) by bizesmtp.qq.com (ESMTP) with id ; Fri, 10 Feb 2023 14:55:02 +0800 (CST) X-QQ-SSF: 01400000000000E0L000000A0000000 X-QQ-FEAT: jXjag1m6xl7i39VW2fNlDzJI4W9TJTj3B6R1huJMz9LPD3TK7/cACrl6+9cbQ KARqoqXYOeykUUWCy2UC9IudwI04bVV/nKxff1VcoDWxXVt5OKwjwWWCdQtHCuuJuO2sMJE 8zyRkspAA8X9BV05JpmuLZ+uEJ9Uz72uJzzEyJ/QhcxBI3kDZ78iNdUE7Val7yTfBtYOk1B Qmw7QXob4U0K02Slreg6qXBwmRqAxuLhpBKdZTI9NPvW5GU9kUDFmSuqL66DNfJ0QsA1iTq r9mUnlQBh0CaXX4ROuFoRE1Wd6Y+UqtE86Fi2e12Tu8+/FygoKFs1KAyP3CENeWhRmm26CG +P4yBbaoVW0ucIt93+UmcLgrVvAIzWim796FUG8EYRmFVuYvhl8E48/0fBjEw== X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: Add vasubu.vx C++ API tests Date: Fri, 10 Feb 2023 14:55:02 +0800 Message-Id: <20230210065502.223635-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-12.9 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_PASS,TXREP,T_SPF_HELO_TEMPERROR autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Ju-Zhe Zhong gcc/testsuite/ChangeLog: * g++.target/riscv/rvv/base/vasubu_vx_mu_rv32-1.C: New test. * g++.target/riscv/rvv/base/vasubu_vx_mu_rv32-2.C: New test. * g++.target/riscv/rvv/base/vasubu_vx_mu_rv32-3.C: New test. * g++.target/riscv/rvv/base/vasubu_vx_mu_rv64-1.C: New test. * g++.target/riscv/rvv/base/vasubu_vx_mu_rv64-2.C: New test. * g++.target/riscv/rvv/base/vasubu_vx_mu_rv64-3.C: New test. * g++.target/riscv/rvv/base/vasubu_vx_rv32-1.C: New test. * g++.target/riscv/rvv/base/vasubu_vx_rv32-2.C: New test. * g++.target/riscv/rvv/base/vasubu_vx_rv32-3.C: New test. * g++.target/riscv/rvv/base/vasubu_vx_rv64-1.C: New test. * g++.target/riscv/rvv/base/vasubu_vx_rv64-2.C: New test. * g++.target/riscv/rvv/base/vasubu_vx_rv64-3.C: New test. * g++.target/riscv/rvv/base/vasubu_vx_tu_rv32-1.C: New test. * g++.target/riscv/rvv/base/vasubu_vx_tu_rv32-2.C: New test. * g++.target/riscv/rvv/base/vasubu_vx_tu_rv32-3.C: New test. * g++.target/riscv/rvv/base/vasubu_vx_tu_rv64-1.C: New test. * g++.target/riscv/rvv/base/vasubu_vx_tu_rv64-2.C: New test. * g++.target/riscv/rvv/base/vasubu_vx_tu_rv64-3.C: New test. * g++.target/riscv/rvv/base/vasubu_vx_tum_rv32-1.C: New test. * g++.target/riscv/rvv/base/vasubu_vx_tum_rv32-2.C: New test. * g++.target/riscv/rvv/base/vasubu_vx_tum_rv32-3.C: New test. * g++.target/riscv/rvv/base/vasubu_vx_tum_rv64-1.C: New test. * g++.target/riscv/rvv/base/vasubu_vx_tum_rv64-2.C: New test. * g++.target/riscv/rvv/base/vasubu_vx_tum_rv64-3.C: New test. * g++.target/riscv/rvv/base/vasubu_vx_tumu_rv32-1.C: New test. * g++.target/riscv/rvv/base/vasubu_vx_tumu_rv32-2.C: New test. * g++.target/riscv/rvv/base/vasubu_vx_tumu_rv32-3.C: New test. * g++.target/riscv/rvv/base/vasubu_vx_tumu_rv64-1.C: New test. * g++.target/riscv/rvv/base/vasubu_vx_tumu_rv64-2.C: New test. * g++.target/riscv/rvv/base/vasubu_vx_tumu_rv64-3.C: New test. --- .../riscv/rvv/base/vasubu_vx_mu_rv32-1.C | 157 +++++++++ .../riscv/rvv/base/vasubu_vx_mu_rv32-2.C | 157 +++++++++ .../riscv/rvv/base/vasubu_vx_mu_rv32-3.C | 157 +++++++++ .../riscv/rvv/base/vasubu_vx_mu_rv64-1.C | 160 +++++++++ .../riscv/rvv/base/vasubu_vx_mu_rv64-2.C | 160 +++++++++ .../riscv/rvv/base/vasubu_vx_mu_rv64-3.C | 160 +++++++++ .../riscv/rvv/base/vasubu_vx_rv32-1.C | 308 +++++++++++++++++ .../riscv/rvv/base/vasubu_vx_rv32-2.C | 308 +++++++++++++++++ .../riscv/rvv/base/vasubu_vx_rv32-3.C | 308 +++++++++++++++++ .../riscv/rvv/base/vasubu_vx_rv64-1.C | 314 ++++++++++++++++++ .../riscv/rvv/base/vasubu_vx_rv64-2.C | 314 ++++++++++++++++++ .../riscv/rvv/base/vasubu_vx_rv64-3.C | 314 ++++++++++++++++++ .../riscv/rvv/base/vasubu_vx_tu_rv32-1.C | 157 +++++++++ .../riscv/rvv/base/vasubu_vx_tu_rv32-2.C | 157 +++++++++ .../riscv/rvv/base/vasubu_vx_tu_rv32-3.C | 157 +++++++++ .../riscv/rvv/base/vasubu_vx_tu_rv64-1.C | 160 +++++++++ .../riscv/rvv/base/vasubu_vx_tu_rv64-2.C | 160 +++++++++ .../riscv/rvv/base/vasubu_vx_tu_rv64-3.C | 160 +++++++++ .../riscv/rvv/base/vasubu_vx_tum_rv32-1.C | 157 +++++++++ .../riscv/rvv/base/vasubu_vx_tum_rv32-2.C | 157 +++++++++ .../riscv/rvv/base/vasubu_vx_tum_rv32-3.C | 157 +++++++++ .../riscv/rvv/base/vasubu_vx_tum_rv64-1.C | 160 +++++++++ .../riscv/rvv/base/vasubu_vx_tum_rv64-2.C | 160 +++++++++ .../riscv/rvv/base/vasubu_vx_tum_rv64-3.C | 160 +++++++++ .../riscv/rvv/base/vasubu_vx_tumu_rv32-1.C | 157 +++++++++ .../riscv/rvv/base/vasubu_vx_tumu_rv32-2.C | 157 +++++++++ .../riscv/rvv/base/vasubu_vx_tumu_rv32-3.C | 157 +++++++++ .../riscv/rvv/base/vasubu_vx_tumu_rv64-1.C | 160 +++++++++ .../riscv/rvv/base/vasubu_vx_tumu_rv64-2.C | 160 +++++++++ .../riscv/rvv/base/vasubu_vx_tumu_rv64-3.C | 160 +++++++++ 30 files changed, 5670 insertions(+) create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_mu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_mu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_mu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_mu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_mu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_mu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tum_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tum_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tum_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tum_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tum_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tum_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tumu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tumu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tumu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tumu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tumu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tumu_rv64-3.C diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_mu_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_mu_rv32-1.C new file mode 100644 index 00000000000..8436c7dc49b --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_mu_rv32-1.C @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vasubu_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vasubu_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vasubu_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vasubu_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vasubu_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vasubu_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vasubu_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vasubu_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vasubu_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vasubu_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vasubu_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vasubu_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vasubu_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vasubu_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vasubu_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vasubu_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vasubu_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vasubu_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vasubu_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vasubu_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vasubu_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vasubu_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vasubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_mu_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_mu_rv32-2.C new file mode 100644 index 00000000000..4dd4e5a16c1 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_mu_rv32-2.C @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vasubu_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vasubu_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vasubu_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vasubu_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vasubu_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vasubu_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vasubu_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vasubu_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vasubu_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vasubu_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vasubu_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vasubu_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vasubu_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vasubu_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vasubu_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vasubu_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vasubu_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vasubu_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vasubu_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vasubu_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vasubu_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vasubu_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vasubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_mu_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_mu_rv32-3.C new file mode 100644 index 00000000000..80a8a6af095 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_mu_rv32-3.C @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vasubu_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vasubu_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vasubu_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vasubu_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vasubu_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vasubu_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vasubu_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vasubu_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vasubu_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vasubu_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vasubu_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vasubu_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vasubu_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vasubu_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vasubu_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vasubu_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vasubu_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vasubu_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vasubu_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vasubu_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vasubu_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vasubu_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vasubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_mu_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_mu_rv64-1.C new file mode 100644 index 00000000000..6f9b7a61756 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_mu_rv64-1.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vasubu_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vasubu_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vasubu_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vasubu_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vasubu_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vasubu_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vasubu_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vasubu_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vasubu_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vasubu_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vasubu_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vasubu_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vasubu_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vasubu_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vasubu_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vasubu_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vasubu_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vasubu_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vasubu_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vasubu_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vasubu_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vasubu_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_mu_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_mu_rv64-2.C new file mode 100644 index 00000000000..e13ae7afde0 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_mu_rv64-2.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vasubu_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vasubu_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vasubu_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vasubu_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vasubu_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vasubu_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vasubu_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vasubu_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vasubu_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vasubu_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vasubu_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vasubu_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vasubu_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vasubu_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vasubu_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vasubu_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vasubu_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vasubu_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vasubu_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vasubu_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vasubu_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vasubu_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_mu_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_mu_rv64-3.C new file mode 100644 index 00000000000..fd7df2589c3 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_mu_rv64-3.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vasubu_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vasubu_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vasubu_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vasubu_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vasubu_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vasubu_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vasubu_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vasubu_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vasubu_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vasubu_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vasubu_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vasubu_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vasubu_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vasubu_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vasubu_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vasubu_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vasubu_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vasubu_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vasubu_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vasubu_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vasubu_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vasubu_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_mu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_rv32-1.C new file mode 100644 index 00000000000..d7e28d32e8f --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_rv32-1.C @@ -0,0 +1,308 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vasubu(vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vasubu(vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vasubu(vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,vl); +} + + +vuint8m1_t test___riscv_vasubu(vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,vl); +} + + +vuint8m2_t test___riscv_vasubu(vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,vl); +} + + +vuint8m4_t test___riscv_vasubu(vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,vl); +} + + +vuint8m8_t test___riscv_vasubu(vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vasubu(vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vasubu(vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,vl); +} + + +vuint16m1_t test___riscv_vasubu(vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,vl); +} + + +vuint16m2_t test___riscv_vasubu(vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,vl); +} + + +vuint16m4_t test___riscv_vasubu(vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,vl); +} + + +vuint16m8_t test___riscv_vasubu(vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vasubu(vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,vl); +} + + +vuint32m1_t test___riscv_vasubu(vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,vl); +} + + +vuint32m2_t test___riscv_vasubu(vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,vl); +} + + +vuint32m4_t test___riscv_vasubu(vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,vl); +} + + +vuint32m8_t test___riscv_vasubu(vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,vl); +} + + +vuint64m1_t test___riscv_vasubu(vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,vl); +} + + +vuint64m2_t test___riscv_vasubu(vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,vl); +} + + +vuint64m4_t test___riscv_vasubu(vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,vl); +} + + +vuint64m8_t test___riscv_vasubu(vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vasubu(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vasubu(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vasubu(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vasubu(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vasubu(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vasubu(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vasubu(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vasubu(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vasubu(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vasubu(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vasubu(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vasubu(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vasubu(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vasubu(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vasubu(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vasubu(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vasubu(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vasubu(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vasubu(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vasubu(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vasubu(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vasubu(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vasubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vasubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_rv32-2.C new file mode 100644 index 00000000000..9f9aa8f0941 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_rv32-2.C @@ -0,0 +1,308 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vasubu(vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,31); +} + + +vuint8mf4_t test___riscv_vasubu(vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,31); +} + + +vuint8mf2_t test___riscv_vasubu(vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,31); +} + + +vuint8m1_t test___riscv_vasubu(vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,31); +} + + +vuint8m2_t test___riscv_vasubu(vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,31); +} + + +vuint8m4_t test___riscv_vasubu(vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,31); +} + + +vuint8m8_t test___riscv_vasubu(vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,31); +} + + +vuint16mf4_t test___riscv_vasubu(vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,31); +} + + +vuint16mf2_t test___riscv_vasubu(vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,31); +} + + +vuint16m1_t test___riscv_vasubu(vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,31); +} + + +vuint16m2_t test___riscv_vasubu(vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,31); +} + + +vuint16m4_t test___riscv_vasubu(vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,31); +} + + +vuint16m8_t test___riscv_vasubu(vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,31); +} + + +vuint32mf2_t test___riscv_vasubu(vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,31); +} + + +vuint32m1_t test___riscv_vasubu(vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,31); +} + + +vuint32m2_t test___riscv_vasubu(vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,31); +} + + +vuint32m4_t test___riscv_vasubu(vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,31); +} + + +vuint32m8_t test___riscv_vasubu(vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,31); +} + + +vuint64m1_t test___riscv_vasubu(vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,31); +} + + +vuint64m2_t test___riscv_vasubu(vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,31); +} + + +vuint64m4_t test___riscv_vasubu(vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,31); +} + + +vuint64m8_t test___riscv_vasubu(vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,31); +} + + +vuint8mf8_t test___riscv_vasubu(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vasubu(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vasubu(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,31); +} + + +vuint8m1_t test___riscv_vasubu(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,31); +} + + +vuint8m2_t test___riscv_vasubu(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,31); +} + + +vuint8m4_t test___riscv_vasubu(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,31); +} + + +vuint8m8_t test___riscv_vasubu(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vasubu(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vasubu(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,31); +} + + +vuint16m1_t test___riscv_vasubu(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,31); +} + + +vuint16m2_t test___riscv_vasubu(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,31); +} + + +vuint16m4_t test___riscv_vasubu(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,31); +} + + +vuint16m8_t test___riscv_vasubu(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vasubu(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,31); +} + + +vuint32m1_t test___riscv_vasubu(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,31); +} + + +vuint32m2_t test___riscv_vasubu(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,31); +} + + +vuint32m4_t test___riscv_vasubu(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,31); +} + + +vuint32m8_t test___riscv_vasubu(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,31); +} + + +vuint64m1_t test___riscv_vasubu(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,31); +} + + +vuint64m2_t test___riscv_vasubu(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,31); +} + + +vuint64m4_t test___riscv_vasubu(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,31); +} + + +vuint64m8_t test___riscv_vasubu(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vasubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vasubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_rv32-3.C new file mode 100644 index 00000000000..a9ef8ef5f88 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_rv32-3.C @@ -0,0 +1,308 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vasubu(vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,32); +} + + +vuint8mf4_t test___riscv_vasubu(vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,32); +} + + +vuint8mf2_t test___riscv_vasubu(vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,32); +} + + +vuint8m1_t test___riscv_vasubu(vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,32); +} + + +vuint8m2_t test___riscv_vasubu(vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,32); +} + + +vuint8m4_t test___riscv_vasubu(vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,32); +} + + +vuint8m8_t test___riscv_vasubu(vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,32); +} + + +vuint16mf4_t test___riscv_vasubu(vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,32); +} + + +vuint16mf2_t test___riscv_vasubu(vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,32); +} + + +vuint16m1_t test___riscv_vasubu(vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,32); +} + + +vuint16m2_t test___riscv_vasubu(vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,32); +} + + +vuint16m4_t test___riscv_vasubu(vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,32); +} + + +vuint16m8_t test___riscv_vasubu(vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,32); +} + + +vuint32mf2_t test___riscv_vasubu(vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,32); +} + + +vuint32m1_t test___riscv_vasubu(vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,32); +} + + +vuint32m2_t test___riscv_vasubu(vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,32); +} + + +vuint32m4_t test___riscv_vasubu(vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,32); +} + + +vuint32m8_t test___riscv_vasubu(vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,32); +} + + +vuint64m1_t test___riscv_vasubu(vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,32); +} + + +vuint64m2_t test___riscv_vasubu(vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,32); +} + + +vuint64m4_t test___riscv_vasubu(vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,32); +} + + +vuint64m8_t test___riscv_vasubu(vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,32); +} + + +vuint8mf8_t test___riscv_vasubu(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vasubu(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vasubu(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,32); +} + + +vuint8m1_t test___riscv_vasubu(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,32); +} + + +vuint8m2_t test___riscv_vasubu(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,32); +} + + +vuint8m4_t test___riscv_vasubu(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,32); +} + + +vuint8m8_t test___riscv_vasubu(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vasubu(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vasubu(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,32); +} + + +vuint16m1_t test___riscv_vasubu(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,32); +} + + +vuint16m2_t test___riscv_vasubu(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,32); +} + + +vuint16m4_t test___riscv_vasubu(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,32); +} + + +vuint16m8_t test___riscv_vasubu(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vasubu(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,32); +} + + +vuint32m1_t test___riscv_vasubu(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,32); +} + + +vuint32m2_t test___riscv_vasubu(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,32); +} + + +vuint32m4_t test___riscv_vasubu(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,32); +} + + +vuint32m8_t test___riscv_vasubu(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,32); +} + + +vuint64m1_t test___riscv_vasubu(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,32); +} + + +vuint64m2_t test___riscv_vasubu(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,32); +} + + +vuint64m4_t test___riscv_vasubu(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,32); +} + + +vuint64m8_t test___riscv_vasubu(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vasubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vasubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_rv64-1.C new file mode 100644 index 00000000000..f14f9092cec --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_rv64-1.C @@ -0,0 +1,314 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vasubu(vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vasubu(vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vasubu(vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,vl); +} + + +vuint8m1_t test___riscv_vasubu(vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,vl); +} + + +vuint8m2_t test___riscv_vasubu(vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,vl); +} + + +vuint8m4_t test___riscv_vasubu(vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,vl); +} + + +vuint8m8_t test___riscv_vasubu(vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vasubu(vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vasubu(vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,vl); +} + + +vuint16m1_t test___riscv_vasubu(vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,vl); +} + + +vuint16m2_t test___riscv_vasubu(vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,vl); +} + + +vuint16m4_t test___riscv_vasubu(vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,vl); +} + + +vuint16m8_t test___riscv_vasubu(vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vasubu(vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,vl); +} + + +vuint32m1_t test___riscv_vasubu(vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,vl); +} + + +vuint32m2_t test___riscv_vasubu(vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,vl); +} + + +vuint32m4_t test___riscv_vasubu(vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,vl); +} + + +vuint32m8_t test___riscv_vasubu(vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,vl); +} + + +vuint64m1_t test___riscv_vasubu(vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,vl); +} + + +vuint64m2_t test___riscv_vasubu(vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,vl); +} + + +vuint64m4_t test___riscv_vasubu(vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,vl); +} + + +vuint64m8_t test___riscv_vasubu(vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,vl); +} + + +vuint8mf8_t test___riscv_vasubu(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vasubu(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vasubu(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vasubu(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vasubu(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vasubu(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vasubu(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vasubu(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vasubu(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vasubu(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vasubu(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vasubu(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vasubu(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vasubu(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vasubu(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vasubu(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vasubu(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vasubu(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vasubu(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vasubu(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vasubu(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vasubu(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_rv64-2.C new file mode 100644 index 00000000000..f5973b745a8 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_rv64-2.C @@ -0,0 +1,314 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vasubu(vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,31); +} + + +vuint8mf4_t test___riscv_vasubu(vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,31); +} + + +vuint8mf2_t test___riscv_vasubu(vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,31); +} + + +vuint8m1_t test___riscv_vasubu(vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,31); +} + + +vuint8m2_t test___riscv_vasubu(vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,31); +} + + +vuint8m4_t test___riscv_vasubu(vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,31); +} + + +vuint8m8_t test___riscv_vasubu(vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,31); +} + + +vuint16mf4_t test___riscv_vasubu(vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,31); +} + + +vuint16mf2_t test___riscv_vasubu(vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,31); +} + + +vuint16m1_t test___riscv_vasubu(vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,31); +} + + +vuint16m2_t test___riscv_vasubu(vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,31); +} + + +vuint16m4_t test___riscv_vasubu(vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,31); +} + + +vuint16m8_t test___riscv_vasubu(vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,31); +} + + +vuint32mf2_t test___riscv_vasubu(vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,31); +} + + +vuint32m1_t test___riscv_vasubu(vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,31); +} + + +vuint32m2_t test___riscv_vasubu(vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,31); +} + + +vuint32m4_t test___riscv_vasubu(vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,31); +} + + +vuint32m8_t test___riscv_vasubu(vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,31); +} + + +vuint64m1_t test___riscv_vasubu(vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,31); +} + + +vuint64m2_t test___riscv_vasubu(vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,31); +} + + +vuint64m4_t test___riscv_vasubu(vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,31); +} + + +vuint64m8_t test___riscv_vasubu(vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,31); +} + + +vuint8mf8_t test___riscv_vasubu(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vasubu(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vasubu(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,31); +} + + +vuint8m1_t test___riscv_vasubu(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,31); +} + + +vuint8m2_t test___riscv_vasubu(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,31); +} + + +vuint8m4_t test___riscv_vasubu(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,31); +} + + +vuint8m8_t test___riscv_vasubu(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vasubu(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vasubu(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,31); +} + + +vuint16m1_t test___riscv_vasubu(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,31); +} + + +vuint16m2_t test___riscv_vasubu(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,31); +} + + +vuint16m4_t test___riscv_vasubu(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,31); +} + + +vuint16m8_t test___riscv_vasubu(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vasubu(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,31); +} + + +vuint32m1_t test___riscv_vasubu(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,31); +} + + +vuint32m2_t test___riscv_vasubu(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,31); +} + + +vuint32m4_t test___riscv_vasubu(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,31); +} + + +vuint32m8_t test___riscv_vasubu(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,31); +} + + +vuint64m1_t test___riscv_vasubu(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,31); +} + + +vuint64m2_t test___riscv_vasubu(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,31); +} + + +vuint64m4_t test___riscv_vasubu(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,31); +} + + +vuint64m8_t test___riscv_vasubu(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_rv64-3.C new file mode 100644 index 00000000000..8499474e0c6 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_rv64-3.C @@ -0,0 +1,314 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vasubu(vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,32); +} + + +vuint8mf4_t test___riscv_vasubu(vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,32); +} + + +vuint8mf2_t test___riscv_vasubu(vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,32); +} + + +vuint8m1_t test___riscv_vasubu(vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,32); +} + + +vuint8m2_t test___riscv_vasubu(vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,32); +} + + +vuint8m4_t test___riscv_vasubu(vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,32); +} + + +vuint8m8_t test___riscv_vasubu(vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,32); +} + + +vuint16mf4_t test___riscv_vasubu(vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,32); +} + + +vuint16mf2_t test___riscv_vasubu(vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,32); +} + + +vuint16m1_t test___riscv_vasubu(vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,32); +} + + +vuint16m2_t test___riscv_vasubu(vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,32); +} + + +vuint16m4_t test___riscv_vasubu(vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,32); +} + + +vuint16m8_t test___riscv_vasubu(vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,32); +} + + +vuint32mf2_t test___riscv_vasubu(vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,32); +} + + +vuint32m1_t test___riscv_vasubu(vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,32); +} + + +vuint32m2_t test___riscv_vasubu(vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,32); +} + + +vuint32m4_t test___riscv_vasubu(vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,32); +} + + +vuint32m8_t test___riscv_vasubu(vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,32); +} + + +vuint64m1_t test___riscv_vasubu(vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,32); +} + + +vuint64m2_t test___riscv_vasubu(vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,32); +} + + +vuint64m4_t test___riscv_vasubu(vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,32); +} + + +vuint64m8_t test___riscv_vasubu(vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu(op1,op2,32); +} + + +vuint8mf8_t test___riscv_vasubu(vbool64_t mask,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vasubu(vbool32_t mask,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vasubu(vbool16_t mask,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,32); +} + + +vuint8m1_t test___riscv_vasubu(vbool8_t mask,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,32); +} + + +vuint8m2_t test___riscv_vasubu(vbool4_t mask,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,32); +} + + +vuint8m4_t test___riscv_vasubu(vbool2_t mask,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,32); +} + + +vuint8m8_t test___riscv_vasubu(vbool1_t mask,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vasubu(vbool64_t mask,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vasubu(vbool32_t mask,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,32); +} + + +vuint16m1_t test___riscv_vasubu(vbool16_t mask,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,32); +} + + +vuint16m2_t test___riscv_vasubu(vbool8_t mask,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,32); +} + + +vuint16m4_t test___riscv_vasubu(vbool4_t mask,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,32); +} + + +vuint16m8_t test___riscv_vasubu(vbool2_t mask,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vasubu(vbool64_t mask,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,32); +} + + +vuint32m1_t test___riscv_vasubu(vbool32_t mask,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,32); +} + + +vuint32m2_t test___riscv_vasubu(vbool16_t mask,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,32); +} + + +vuint32m4_t test___riscv_vasubu(vbool8_t mask,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,32); +} + + +vuint32m8_t test___riscv_vasubu(vbool4_t mask,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,32); +} + + +vuint64m1_t test___riscv_vasubu(vbool64_t mask,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,32); +} + + +vuint64m2_t test___riscv_vasubu(vbool32_t mask,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,32); +} + + +vuint64m4_t test___riscv_vasubu(vbool16_t mask,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,32); +} + + +vuint64m8_t test___riscv_vasubu(vbool8_t mask,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu(mask,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tu_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tu_rv32-1.C new file mode 100644 index 00000000000..9792987f179 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tu_rv32-1.C @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vasubu_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vasubu_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vasubu_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vasubu_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vasubu_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vasubu_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vasubu_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vasubu_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vasubu_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vasubu_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vasubu_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vasubu_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vasubu_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vasubu_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vasubu_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vasubu_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vasubu_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vasubu_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vasubu_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vasubu_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vasubu_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vasubu_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vasubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tu_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tu_rv32-2.C new file mode 100644 index 00000000000..ce61a1b649c --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tu_rv32-2.C @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vasubu_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vasubu_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vasubu_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vasubu_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vasubu_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vasubu_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vasubu_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vasubu_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vasubu_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vasubu_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vasubu_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vasubu_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vasubu_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vasubu_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vasubu_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vasubu_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vasubu_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vasubu_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vasubu_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vasubu_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vasubu_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vasubu_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vasubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tu_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tu_rv32-3.C new file mode 100644 index 00000000000..10474108f95 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tu_rv32-3.C @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vasubu_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vasubu_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vasubu_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vasubu_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vasubu_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vasubu_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vasubu_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vasubu_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vasubu_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vasubu_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vasubu_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vasubu_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vasubu_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vasubu_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vasubu_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vasubu_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vasubu_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vasubu_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vasubu_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vasubu_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vasubu_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vasubu_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vasubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tu_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tu_rv64-1.C new file mode 100644 index 00000000000..82b8abaf104 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tu_rv64-1.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vasubu_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vasubu_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vasubu_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vasubu_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vasubu_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vasubu_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vasubu_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vasubu_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vasubu_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vasubu_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vasubu_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vasubu_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vasubu_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vasubu_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vasubu_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vasubu_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vasubu_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vasubu_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vasubu_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vasubu_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vasubu_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vasubu_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tu_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tu_rv64-2.C new file mode 100644 index 00000000000..5a04c4f9225 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tu_rv64-2.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vasubu_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vasubu_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vasubu_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vasubu_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vasubu_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vasubu_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vasubu_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vasubu_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vasubu_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vasubu_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vasubu_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vasubu_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vasubu_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vasubu_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vasubu_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vasubu_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vasubu_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vasubu_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vasubu_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vasubu_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vasubu_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vasubu_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tu_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tu_rv64-3.C new file mode 100644 index 00000000000..84fd6954280 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tu_rv64-3.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vasubu_tu(vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vasubu_tu(vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vasubu_tu(vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vasubu_tu(vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vasubu_tu(vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vasubu_tu(vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vasubu_tu(vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vasubu_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vasubu_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vasubu_tu(vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vasubu_tu(vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vasubu_tu(vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vasubu_tu(vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vasubu_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vasubu_tu(vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vasubu_tu(vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vasubu_tu(vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vasubu_tu(vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vasubu_tu(vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vasubu_tu(vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vasubu_tu(vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vasubu_tu(vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_tu(merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tum_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tum_rv32-1.C new file mode 100644 index 00000000000..c3a731c5d74 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tum_rv32-1.C @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vasubu_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vasubu_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vasubu_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vasubu_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vasubu_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vasubu_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vasubu_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vasubu_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vasubu_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vasubu_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vasubu_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vasubu_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vasubu_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vasubu_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vasubu_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vasubu_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vasubu_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vasubu_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vasubu_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vasubu_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vasubu_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vasubu_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vasubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tum_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tum_rv32-2.C new file mode 100644 index 00000000000..aeb278e2bbd --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tum_rv32-2.C @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vasubu_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vasubu_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vasubu_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vasubu_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vasubu_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vasubu_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vasubu_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vasubu_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vasubu_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vasubu_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vasubu_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vasubu_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vasubu_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vasubu_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vasubu_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vasubu_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vasubu_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vasubu_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vasubu_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vasubu_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vasubu_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vasubu_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vasubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tum_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tum_rv32-3.C new file mode 100644 index 00000000000..a6bb55e8f7d --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tum_rv32-3.C @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vasubu_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vasubu_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vasubu_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vasubu_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vasubu_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vasubu_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vasubu_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vasubu_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vasubu_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vasubu_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vasubu_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vasubu_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vasubu_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vasubu_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vasubu_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vasubu_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vasubu_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vasubu_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vasubu_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vasubu_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vasubu_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vasubu_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vasubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tum_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tum_rv64-1.C new file mode 100644 index 00000000000..2f9e84af963 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tum_rv64-1.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vasubu_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vasubu_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vasubu_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vasubu_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vasubu_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vasubu_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vasubu_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vasubu_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vasubu_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vasubu_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vasubu_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vasubu_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vasubu_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vasubu_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vasubu_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vasubu_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vasubu_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vasubu_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vasubu_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vasubu_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vasubu_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vasubu_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tum_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tum_rv64-2.C new file mode 100644 index 00000000000..8ffa6b33e06 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tum_rv64-2.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vasubu_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vasubu_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vasubu_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vasubu_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vasubu_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vasubu_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vasubu_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vasubu_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vasubu_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vasubu_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vasubu_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vasubu_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vasubu_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vasubu_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vasubu_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vasubu_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vasubu_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vasubu_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vasubu_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vasubu_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vasubu_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vasubu_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tum_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tum_rv64-3.C new file mode 100644 index 00000000000..998c5578a8c --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tum_rv64-3.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vasubu_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vasubu_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vasubu_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vasubu_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vasubu_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vasubu_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vasubu_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vasubu_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vasubu_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vasubu_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vasubu_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vasubu_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vasubu_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vasubu_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vasubu_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vasubu_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vasubu_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vasubu_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vasubu_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vasubu_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vasubu_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vasubu_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_tum(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tumu_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tumu_rv32-1.C new file mode 100644 index 00000000000..7f42c73421c --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tumu_rv32-1.C @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vasubu_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vasubu_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vasubu_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vasubu_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vasubu_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vasubu_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vasubu_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vasubu_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vasubu_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vasubu_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vasubu_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vasubu_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vasubu_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vasubu_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vasubu_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vasubu_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vasubu_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vasubu_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vasubu_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vasubu_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vasubu_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vasubu_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vasubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tumu_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tumu_rv32-2.C new file mode 100644 index 00000000000..2fff3e42aab --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tumu_rv32-2.C @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vasubu_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vasubu_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vasubu_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vasubu_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vasubu_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vasubu_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vasubu_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vasubu_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vasubu_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vasubu_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vasubu_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vasubu_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vasubu_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vasubu_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vasubu_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vasubu_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vasubu_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vasubu_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vasubu_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vasubu_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vasubu_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vasubu_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vasubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tumu_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tumu_rv32-3.C new file mode 100644 index 00000000000..93aeb82b3e2 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tumu_rv32-3.C @@ -0,0 +1,157 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vasubu_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vasubu_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vasubu_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vasubu_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vasubu_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vasubu_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vasubu_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vasubu_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vasubu_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vasubu_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vasubu_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vasubu_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vasubu_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vasubu_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vasubu_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vasubu_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vasubu_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vasubu_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vasubu_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vasubu_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vasubu_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vasubu_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vasubu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tumu_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tumu_rv64-1.C new file mode 100644 index 00000000000..816d519cfb8 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tumu_rv64-1.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vasubu_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,vl); +} + + +vuint8mf4_t test___riscv_vasubu_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,vl); +} + + +vuint8mf2_t test___riscv_vasubu_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m1_t test___riscv_vasubu_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m2_t test___riscv_vasubu_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m4_t test___riscv_vasubu_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,vl); +} + + +vuint8m8_t test___riscv_vasubu_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,vl); +} + + +vuint16mf4_t test___riscv_vasubu_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,vl); +} + + +vuint16mf2_t test___riscv_vasubu_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m1_t test___riscv_vasubu_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m2_t test___riscv_vasubu_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m4_t test___riscv_vasubu_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,vl); +} + + +vuint16m8_t test___riscv_vasubu_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,vl); +} + + +vuint32mf2_t test___riscv_vasubu_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m1_t test___riscv_vasubu_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m2_t test___riscv_vasubu_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m4_t test___riscv_vasubu_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,vl); +} + + +vuint32m8_t test___riscv_vasubu_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m1_t test___riscv_vasubu_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m2_t test___riscv_vasubu_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m4_t test___riscv_vasubu_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,vl); +} + + +vuint64m8_t test___riscv_vasubu_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tumu_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tumu_rv64-2.C new file mode 100644 index 00000000000..04ae7a4beb2 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tumu_rv64-2.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vasubu_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,31); +} + + +vuint8mf4_t test___riscv_vasubu_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,31); +} + + +vuint8mf2_t test___riscv_vasubu_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,31); +} + + +vuint8m1_t test___riscv_vasubu_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,31); +} + + +vuint8m2_t test___riscv_vasubu_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,31); +} + + +vuint8m4_t test___riscv_vasubu_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,31); +} + + +vuint8m8_t test___riscv_vasubu_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,31); +} + + +vuint16mf4_t test___riscv_vasubu_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,31); +} + + +vuint16mf2_t test___riscv_vasubu_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,31); +} + + +vuint16m1_t test___riscv_vasubu_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,31); +} + + +vuint16m2_t test___riscv_vasubu_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,31); +} + + +vuint16m4_t test___riscv_vasubu_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,31); +} + + +vuint16m8_t test___riscv_vasubu_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,31); +} + + +vuint32mf2_t test___riscv_vasubu_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,31); +} + + +vuint32m1_t test___riscv_vasubu_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,31); +} + + +vuint32m2_t test___riscv_vasubu_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,31); +} + + +vuint32m4_t test___riscv_vasubu_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,31); +} + + +vuint32m8_t test___riscv_vasubu_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,31); +} + + +vuint64m1_t test___riscv_vasubu_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,31); +} + + +vuint64m2_t test___riscv_vasubu_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,31); +} + + +vuint64m4_t test___riscv_vasubu_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,31); +} + + +vuint64m8_t test___riscv_vasubu_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tumu_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tumu_rv64-3.C new file mode 100644 index 00000000000..9d7576b18e4 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vasubu_vx_tumu_rv64-3.C @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vasubu_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,32); +} + + +vuint8mf4_t test___riscv_vasubu_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,32); +} + + +vuint8mf2_t test___riscv_vasubu_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,32); +} + + +vuint8m1_t test___riscv_vasubu_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,32); +} + + +vuint8m2_t test___riscv_vasubu_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,32); +} + + +vuint8m4_t test___riscv_vasubu_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,32); +} + + +vuint8m8_t test___riscv_vasubu_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,32); +} + + +vuint16mf4_t test___riscv_vasubu_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,32); +} + + +vuint16mf2_t test___riscv_vasubu_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,32); +} + + +vuint16m1_t test___riscv_vasubu_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,32); +} + + +vuint16m2_t test___riscv_vasubu_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,32); +} + + +vuint16m4_t test___riscv_vasubu_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,32); +} + + +vuint16m8_t test___riscv_vasubu_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,32); +} + + +vuint32mf2_t test___riscv_vasubu_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,32); +} + + +vuint32m1_t test___riscv_vasubu_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,32); +} + + +vuint32m2_t test___riscv_vasubu_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,32); +} + + +vuint32m4_t test___riscv_vasubu_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,32); +} + + +vuint32m8_t test___riscv_vasubu_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,32); +} + + +vuint64m1_t test___riscv_vasubu_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,32); +} + + +vuint64m2_t test___riscv_vasubu_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,32); +} + + +vuint64m4_t test___riscv_vasubu_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,32); +} + + +vuint64m8_t test___riscv_vasubu_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint64_t op2,size_t vl) +{ + return __riscv_vasubu_tumu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vasubu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ -- 2.36.3