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From: juzhe.zhong@rivai.ai
To: gcc-patches@gcc.gnu.org
Cc: kito.cheng@gmail.com,
	Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
Subject: [PATCH] RISC-V: Add vaadd.vx C++ API tests
Date: Fri, 10 Feb 2023 15:02:13 +0800
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From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>

gcc/testsuite/ChangeLog:

        * g++.target/riscv/rvv/base/vaadd_vx_mu_rv32-1.C: New test.
        * g++.target/riscv/rvv/base/vaadd_vx_mu_rv32-2.C: New test.
        * g++.target/riscv/rvv/base/vaadd_vx_mu_rv32-3.C: New test.
        * g++.target/riscv/rvv/base/vaadd_vx_mu_rv64-1.C: New test.
        * g++.target/riscv/rvv/base/vaadd_vx_mu_rv64-2.C: New test.
        * g++.target/riscv/rvv/base/vaadd_vx_mu_rv64-3.C: New test.
        * g++.target/riscv/rvv/base/vaadd_vx_rv32-1.C: New test.
        * g++.target/riscv/rvv/base/vaadd_vx_rv32-2.C: New test.
        * g++.target/riscv/rvv/base/vaadd_vx_rv32-3.C: New test.
        * g++.target/riscv/rvv/base/vaadd_vx_rv64-1.C: New test.
        * g++.target/riscv/rvv/base/vaadd_vx_rv64-2.C: New test.
        * g++.target/riscv/rvv/base/vaadd_vx_rv64-3.C: New test.
        * g++.target/riscv/rvv/base/vaadd_vx_tu_rv32-1.C: New test.
        * g++.target/riscv/rvv/base/vaadd_vx_tu_rv32-2.C: New test.
        * g++.target/riscv/rvv/base/vaadd_vx_tu_rv32-3.C: New test.
        * g++.target/riscv/rvv/base/vaadd_vx_tu_rv64-1.C: New test.
        * g++.target/riscv/rvv/base/vaadd_vx_tu_rv64-2.C: New test.
        * g++.target/riscv/rvv/base/vaadd_vx_tu_rv64-3.C: New test.
        * g++.target/riscv/rvv/base/vaadd_vx_tum_rv32-1.C: New test.
        * g++.target/riscv/rvv/base/vaadd_vx_tum_rv32-2.C: New test.
        * g++.target/riscv/rvv/base/vaadd_vx_tum_rv32-3.C: New test.
        * g++.target/riscv/rvv/base/vaadd_vx_tum_rv64-1.C: New test.
        * g++.target/riscv/rvv/base/vaadd_vx_tum_rv64-2.C: New test.
        * g++.target/riscv/rvv/base/vaadd_vx_tum_rv64-3.C: New test.
        * g++.target/riscv/rvv/base/vaadd_vx_tumu_rv32-1.C: New test.
        * g++.target/riscv/rvv/base/vaadd_vx_tumu_rv32-2.C: New test.
        * g++.target/riscv/rvv/base/vaadd_vx_tumu_rv32-3.C: New test.
        * g++.target/riscv/rvv/base/vaadd_vx_tumu_rv64-1.C: New test.
        * g++.target/riscv/rvv/base/vaadd_vx_tumu_rv64-2.C: New test.
        * g++.target/riscv/rvv/base/vaadd_vx_tumu_rv64-3.C: New test.

---
 .../riscv/rvv/base/vaadd_vx_mu_rv32-1.C       | 157 +++++++++
 .../riscv/rvv/base/vaadd_vx_mu_rv32-2.C       | 157 +++++++++
 .../riscv/rvv/base/vaadd_vx_mu_rv32-3.C       | 157 +++++++++
 .../riscv/rvv/base/vaadd_vx_mu_rv64-1.C       | 160 +++++++++
 .../riscv/rvv/base/vaadd_vx_mu_rv64-2.C       | 160 +++++++++
 .../riscv/rvv/base/vaadd_vx_mu_rv64-3.C       | 160 +++++++++
 .../riscv/rvv/base/vaadd_vx_rv32-1.C          | 308 +++++++++++++++++
 .../riscv/rvv/base/vaadd_vx_rv32-2.C          | 308 +++++++++++++++++
 .../riscv/rvv/base/vaadd_vx_rv32-3.C          | 308 +++++++++++++++++
 .../riscv/rvv/base/vaadd_vx_rv64-1.C          | 314 ++++++++++++++++++
 .../riscv/rvv/base/vaadd_vx_rv64-2.C          | 314 ++++++++++++++++++
 .../riscv/rvv/base/vaadd_vx_rv64-3.C          | 314 ++++++++++++++++++
 .../riscv/rvv/base/vaadd_vx_tu_rv32-1.C       | 157 +++++++++
 .../riscv/rvv/base/vaadd_vx_tu_rv32-2.C       | 157 +++++++++
 .../riscv/rvv/base/vaadd_vx_tu_rv32-3.C       | 157 +++++++++
 .../riscv/rvv/base/vaadd_vx_tu_rv64-1.C       | 160 +++++++++
 .../riscv/rvv/base/vaadd_vx_tu_rv64-2.C       | 160 +++++++++
 .../riscv/rvv/base/vaadd_vx_tu_rv64-3.C       | 160 +++++++++
 .../riscv/rvv/base/vaadd_vx_tum_rv32-1.C      | 157 +++++++++
 .../riscv/rvv/base/vaadd_vx_tum_rv32-2.C      | 157 +++++++++
 .../riscv/rvv/base/vaadd_vx_tum_rv32-3.C      | 157 +++++++++
 .../riscv/rvv/base/vaadd_vx_tum_rv64-1.C      | 160 +++++++++
 .../riscv/rvv/base/vaadd_vx_tum_rv64-2.C      | 160 +++++++++
 .../riscv/rvv/base/vaadd_vx_tum_rv64-3.C      | 160 +++++++++
 .../riscv/rvv/base/vaadd_vx_tumu_rv32-1.C     | 157 +++++++++
 .../riscv/rvv/base/vaadd_vx_tumu_rv32-2.C     | 157 +++++++++
 .../riscv/rvv/base/vaadd_vx_tumu_rv32-3.C     | 157 +++++++++
 .../riscv/rvv/base/vaadd_vx_tumu_rv64-1.C     | 160 +++++++++
 .../riscv/rvv/base/vaadd_vx_tumu_rv64-2.C     | 160 +++++++++
 .../riscv/rvv/base/vaadd_vx_tumu_rv64-3.C     | 160 +++++++++
 30 files changed, 5670 insertions(+)
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_mu_rv32-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_mu_rv32-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_mu_rv32-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_mu_rv64-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_mu_rv64-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_mu_rv64-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_rv32-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_rv32-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_rv32-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_rv64-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_rv64-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_rv64-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tu_rv32-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tu_rv32-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tu_rv32-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tu_rv64-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tu_rv64-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tu_rv64-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tum_rv32-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tum_rv32-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tum_rv32-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tum_rv64-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tum_rv64-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tum_rv64-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tumu_rv32-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tumu_rv32-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tumu_rv32-3.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tumu_rv64-1.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tumu_rv64-2.C
 create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tumu_rv64-3.C

diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_mu_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_mu_rv32-1.C
new file mode 100644
index 00000000000..388d76b9992
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_mu_rv32-1.C
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vaadd_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vaadd_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vaadd_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vaadd_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vaadd_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vaadd_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vaadd_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vaadd_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vaadd_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vaadd_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vaadd_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vaadd_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vaadd_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vaadd_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vaadd_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vaadd_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vaadd_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vaadd_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vaadd_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vaadd_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vaadd_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vaadd_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_mu_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_mu_rv32-2.C
new file mode 100644
index 00000000000..f175c03680a
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_mu_rv32-2.C
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vaadd_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vaadd_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vaadd_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vaadd_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vaadd_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vaadd_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vaadd_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vaadd_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vaadd_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vaadd_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vaadd_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vaadd_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vaadd_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vaadd_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vaadd_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vaadd_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vaadd_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vaadd_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vaadd_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vaadd_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vaadd_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vaadd_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_mu_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_mu_rv32-3.C
new file mode 100644
index 00000000000..de16b810126
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_mu_rv32-3.C
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vaadd_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vaadd_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vaadd_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vaadd_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vaadd_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vaadd_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vaadd_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vaadd_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vaadd_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vaadd_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vaadd_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vaadd_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vaadd_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vaadd_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vaadd_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vaadd_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vaadd_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vaadd_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vaadd_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vaadd_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vaadd_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vaadd_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_mu_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_mu_rv64-1.C
new file mode 100644
index 00000000000..b3d6fb6853b
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_mu_rv64-1.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vaadd_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vaadd_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vaadd_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vaadd_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vaadd_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vaadd_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vaadd_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vaadd_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vaadd_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vaadd_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vaadd_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vaadd_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vaadd_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vaadd_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vaadd_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vaadd_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vaadd_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vaadd_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vaadd_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vaadd_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vaadd_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vaadd_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_mu_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_mu_rv64-2.C
new file mode 100644
index 00000000000..dd799deeb9e
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_mu_rv64-2.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vaadd_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vaadd_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vaadd_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vaadd_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vaadd_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vaadd_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vaadd_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vaadd_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vaadd_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vaadd_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vaadd_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vaadd_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vaadd_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vaadd_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vaadd_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vaadd_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vaadd_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vaadd_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vaadd_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vaadd_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vaadd_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vaadd_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_mu_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_mu_rv64-3.C
new file mode 100644
index 00000000000..c2a7cdf6d54
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_mu_rv64-3.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vaadd_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vaadd_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vaadd_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vaadd_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vaadd_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vaadd_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vaadd_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vaadd_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vaadd_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vaadd_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vaadd_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vaadd_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vaadd_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vaadd_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vaadd_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vaadd_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vaadd_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vaadd_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vaadd_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vaadd_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vaadd_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vaadd_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_mu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_rv32-1.C
new file mode 100644
index 00000000000..4c25dd303ec
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_rv32-1.C
@@ -0,0 +1,308 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vaadd(vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vaadd(vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vaadd(vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vaadd(vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vaadd(vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vaadd(vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vaadd(vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vaadd(vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vaadd(vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vaadd(vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vaadd(vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vaadd(vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vaadd(vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vaadd(vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vaadd(vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vaadd(vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vaadd(vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vaadd(vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vaadd(vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vaadd(vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vaadd(vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vaadd(vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint8mf8_t test___riscv_vaadd(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vaadd(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vaadd(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vaadd(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vaadd(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vaadd(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vaadd(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vaadd(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vaadd(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vaadd(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vaadd(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vaadd(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vaadd(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vaadd(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vaadd(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vaadd(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vaadd(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vaadd(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vaadd(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vaadd(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vaadd(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vaadd(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_rv32-2.C
new file mode 100644
index 00000000000..31dbc2021ba
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_rv32-2.C
@@ -0,0 +1,308 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vaadd(vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vaadd(vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vaadd(vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vaadd(vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vaadd(vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vaadd(vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vaadd(vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vaadd(vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vaadd(vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vaadd(vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vaadd(vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vaadd(vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vaadd(vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vaadd(vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vaadd(vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vaadd(vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vaadd(vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vaadd(vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vaadd(vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vaadd(vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vaadd(vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vaadd(vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,31);
+}
+
+
+vint8mf8_t test___riscv_vaadd(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vaadd(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vaadd(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vaadd(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vaadd(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vaadd(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vaadd(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vaadd(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vaadd(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vaadd(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vaadd(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vaadd(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vaadd(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vaadd(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vaadd(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vaadd(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vaadd(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vaadd(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vaadd(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vaadd(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vaadd(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vaadd(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_rv32-3.C
new file mode 100644
index 00000000000..c7d40fd2413
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_rv32-3.C
@@ -0,0 +1,308 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vaadd(vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vaadd(vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vaadd(vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vaadd(vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vaadd(vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vaadd(vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vaadd(vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vaadd(vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vaadd(vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vaadd(vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vaadd(vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vaadd(vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vaadd(vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vaadd(vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vaadd(vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vaadd(vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vaadd(vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vaadd(vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vaadd(vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vaadd(vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vaadd(vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vaadd(vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,32);
+}
+
+
+vint8mf8_t test___riscv_vaadd(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vaadd(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vaadd(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vaadd(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vaadd(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vaadd(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vaadd(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vaadd(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vaadd(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vaadd(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vaadd(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vaadd(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vaadd(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vaadd(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vaadd(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vaadd(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vaadd(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vaadd(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vaadd(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vaadd(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vaadd(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vaadd(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_rv64-1.C
new file mode 100644
index 00000000000..d7563cc6689
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_rv64-1.C
@@ -0,0 +1,314 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vaadd(vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vaadd(vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vaadd(vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vaadd(vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vaadd(vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vaadd(vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vaadd(vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vaadd(vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vaadd(vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vaadd(vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vaadd(vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vaadd(vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vaadd(vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vaadd(vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vaadd(vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vaadd(vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vaadd(vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vaadd(vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vaadd(vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vaadd(vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vaadd(vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vaadd(vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,vl);
+}
+
+
+vint8mf8_t test___riscv_vaadd(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vaadd(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vaadd(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vaadd(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vaadd(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vaadd(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vaadd(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vaadd(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vaadd(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vaadd(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vaadd(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vaadd(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vaadd(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vaadd(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vaadd(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vaadd(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vaadd(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vaadd(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vaadd(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vaadd(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vaadd(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vaadd(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_rv64-2.C
new file mode 100644
index 00000000000..0b570d389aa
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_rv64-2.C
@@ -0,0 +1,314 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vaadd(vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vaadd(vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vaadd(vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vaadd(vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vaadd(vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vaadd(vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vaadd(vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vaadd(vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vaadd(vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vaadd(vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vaadd(vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vaadd(vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vaadd(vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vaadd(vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vaadd(vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vaadd(vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vaadd(vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vaadd(vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vaadd(vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vaadd(vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vaadd(vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vaadd(vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,31);
+}
+
+
+vint8mf8_t test___riscv_vaadd(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vaadd(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vaadd(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vaadd(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vaadd(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vaadd(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vaadd(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vaadd(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vaadd(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vaadd(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vaadd(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vaadd(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vaadd(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vaadd(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vaadd(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vaadd(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vaadd(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vaadd(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vaadd(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vaadd(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vaadd(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vaadd(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_rv64-3.C
new file mode 100644
index 00000000000..6a45b4a871c
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_rv64-3.C
@@ -0,0 +1,314 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vaadd(vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vaadd(vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vaadd(vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vaadd(vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vaadd(vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vaadd(vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vaadd(vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vaadd(vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vaadd(vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vaadd(vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vaadd(vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vaadd(vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vaadd(vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vaadd(vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vaadd(vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vaadd(vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vaadd(vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vaadd(vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vaadd(vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vaadd(vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vaadd(vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vaadd(vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd(op1,op2,32);
+}
+
+
+vint8mf8_t test___riscv_vaadd(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vaadd(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vaadd(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vaadd(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vaadd(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vaadd(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vaadd(vbool1_t mask,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vaadd(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vaadd(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vaadd(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vaadd(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vaadd(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vaadd(vbool2_t mask,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vaadd(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vaadd(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vaadd(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vaadd(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vaadd(vbool4_t mask,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vaadd(vbool64_t mask,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vaadd(vbool32_t mask,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vaadd(vbool16_t mask,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vaadd(vbool8_t mask,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd(mask,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tu_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tu_rv32-1.C
new file mode 100644
index 00000000000..9690378266f
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tu_rv32-1.C
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vaadd_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vaadd_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vaadd_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vaadd_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vaadd_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vaadd_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vaadd_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vaadd_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vaadd_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vaadd_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vaadd_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vaadd_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vaadd_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vaadd_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vaadd_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vaadd_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vaadd_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vaadd_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vaadd_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vaadd_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vaadd_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vaadd_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tu_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tu_rv32-2.C
new file mode 100644
index 00000000000..9a55587dc89
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tu_rv32-2.C
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vaadd_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vaadd_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vaadd_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vaadd_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vaadd_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vaadd_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vaadd_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vaadd_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vaadd_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vaadd_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vaadd_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vaadd_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vaadd_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vaadd_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vaadd_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vaadd_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vaadd_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vaadd_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vaadd_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vaadd_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vaadd_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vaadd_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tu_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tu_rv32-3.C
new file mode 100644
index 00000000000..35667cdc0bd
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tu_rv32-3.C
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vaadd_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vaadd_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vaadd_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vaadd_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vaadd_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vaadd_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vaadd_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vaadd_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vaadd_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vaadd_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vaadd_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vaadd_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vaadd_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vaadd_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vaadd_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vaadd_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vaadd_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vaadd_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vaadd_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vaadd_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vaadd_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vaadd_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tu_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tu_rv64-1.C
new file mode 100644
index 00000000000..5688a273da1
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tu_rv64-1.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vaadd_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vaadd_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vaadd_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vaadd_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vaadd_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vaadd_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vaadd_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vaadd_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vaadd_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vaadd_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vaadd_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vaadd_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vaadd_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vaadd_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vaadd_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vaadd_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vaadd_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vaadd_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vaadd_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vaadd_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vaadd_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vaadd_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tu_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tu_rv64-2.C
new file mode 100644
index 00000000000..a2c4618d56d
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tu_rv64-2.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vaadd_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vaadd_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vaadd_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vaadd_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vaadd_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vaadd_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vaadd_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vaadd_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vaadd_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vaadd_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vaadd_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vaadd_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vaadd_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vaadd_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vaadd_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vaadd_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vaadd_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vaadd_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vaadd_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vaadd_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vaadd_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vaadd_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tu_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tu_rv64-3.C
new file mode 100644
index 00000000000..0d69aee7878
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tu_rv64-3.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vaadd_tu(vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vaadd_tu(vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vaadd_tu(vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vaadd_tu(vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vaadd_tu(vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vaadd_tu(vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vaadd_tu(vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vaadd_tu(vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vaadd_tu(vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vaadd_tu(vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vaadd_tu(vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vaadd_tu(vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vaadd_tu(vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vaadd_tu(vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vaadd_tu(vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vaadd_tu(vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vaadd_tu(vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vaadd_tu(vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vaadd_tu(vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vaadd_tu(vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vaadd_tu(vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vaadd_tu(vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_tu(merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tum_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tum_rv32-1.C
new file mode 100644
index 00000000000..f5a3ee73a58
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tum_rv32-1.C
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vaadd_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vaadd_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vaadd_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vaadd_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vaadd_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vaadd_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vaadd_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vaadd_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vaadd_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vaadd_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vaadd_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vaadd_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vaadd_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vaadd_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vaadd_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vaadd_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vaadd_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vaadd_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vaadd_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vaadd_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vaadd_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vaadd_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tum_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tum_rv32-2.C
new file mode 100644
index 00000000000..94e4912c602
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tum_rv32-2.C
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vaadd_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vaadd_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vaadd_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vaadd_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vaadd_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vaadd_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vaadd_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vaadd_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vaadd_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vaadd_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vaadd_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vaadd_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vaadd_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vaadd_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vaadd_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vaadd_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vaadd_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vaadd_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vaadd_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vaadd_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vaadd_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vaadd_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tum_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tum_rv32-3.C
new file mode 100644
index 00000000000..11db3a8ab57
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tum_rv32-3.C
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vaadd_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vaadd_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vaadd_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vaadd_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vaadd_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vaadd_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vaadd_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vaadd_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vaadd_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vaadd_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vaadd_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vaadd_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vaadd_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vaadd_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vaadd_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vaadd_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vaadd_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vaadd_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vaadd_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vaadd_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vaadd_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vaadd_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tum_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tum_rv64-1.C
new file mode 100644
index 00000000000..7613259525c
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tum_rv64-1.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vaadd_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vaadd_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vaadd_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vaadd_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vaadd_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vaadd_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vaadd_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vaadd_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vaadd_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vaadd_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vaadd_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vaadd_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vaadd_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vaadd_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vaadd_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vaadd_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vaadd_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vaadd_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vaadd_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vaadd_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vaadd_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vaadd_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tum_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tum_rv64-2.C
new file mode 100644
index 00000000000..005e790f84c
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tum_rv64-2.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vaadd_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vaadd_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vaadd_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vaadd_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vaadd_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vaadd_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vaadd_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vaadd_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vaadd_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vaadd_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vaadd_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vaadd_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vaadd_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vaadd_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vaadd_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vaadd_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vaadd_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vaadd_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vaadd_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vaadd_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vaadd_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vaadd_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tum_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tum_rv64-3.C
new file mode 100644
index 00000000000..2b97d49c5ba
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tum_rv64-3.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vaadd_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vaadd_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vaadd_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vaadd_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vaadd_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vaadd_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vaadd_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vaadd_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vaadd_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vaadd_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vaadd_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vaadd_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vaadd_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vaadd_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vaadd_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vaadd_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vaadd_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vaadd_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vaadd_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vaadd_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vaadd_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vaadd_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_tum(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tumu_rv32-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tumu_rv32-1.C
new file mode 100644
index 00000000000..3f9e1596d9d
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tumu_rv32-1.C
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vaadd_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vaadd_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vaadd_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vaadd_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vaadd_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vaadd_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vaadd_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vaadd_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vaadd_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vaadd_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vaadd_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vaadd_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vaadd_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vaadd_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vaadd_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vaadd_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vaadd_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vaadd_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vaadd_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vaadd_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vaadd_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vaadd_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tumu_rv32-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tumu_rv32-2.C
new file mode 100644
index 00000000000..0bcbb47b5a2
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tumu_rv32-2.C
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vaadd_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vaadd_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vaadd_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vaadd_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vaadd_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vaadd_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vaadd_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vaadd_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vaadd_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vaadd_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vaadd_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vaadd_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vaadd_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vaadd_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vaadd_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vaadd_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vaadd_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vaadd_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vaadd_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vaadd_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vaadd_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vaadd_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tumu_rv32-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tumu_rv32-3.C
new file mode 100644
index 00000000000..abb7abe6751
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tumu_rv32-3.C
@@ -0,0 +1,157 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vaadd_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vaadd_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vaadd_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vaadd_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vaadd_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vaadd_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vaadd_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vaadd_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vaadd_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vaadd_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vaadd_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vaadd_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vaadd_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vaadd_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vaadd_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vaadd_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vaadd_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vaadd_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vaadd_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vaadd_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vaadd_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vaadd_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vaadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 4 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tumu_rv64-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tumu_rv64-1.C
new file mode 100644
index 00000000000..f4935c4c249
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tumu_rv64-1.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vaadd_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf4_t test___riscv_vaadd_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8mf2_t test___riscv_vaadd_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m1_t test___riscv_vaadd_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m2_t test___riscv_vaadd_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m4_t test___riscv_vaadd_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint8m8_t test___riscv_vaadd_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf4_t test___riscv_vaadd_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16mf2_t test___riscv_vaadd_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m1_t test___riscv_vaadd_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m2_t test___riscv_vaadd_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m4_t test___riscv_vaadd_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint16m8_t test___riscv_vaadd_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32mf2_t test___riscv_vaadd_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m1_t test___riscv_vaadd_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m2_t test___riscv_vaadd_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m4_t test___riscv_vaadd_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint32m8_t test___riscv_vaadd_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m1_t test___riscv_vaadd_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m2_t test___riscv_vaadd_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m4_t test___riscv_vaadd_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,vl);
+}
+
+
+vint64m8_t test___riscv_vaadd_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tumu_rv64-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tumu_rv64-2.C
new file mode 100644
index 00000000000..9efea57754b
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tumu_rv64-2.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vaadd_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf4_t test___riscv_vaadd_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8mf2_t test___riscv_vaadd_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m1_t test___riscv_vaadd_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m2_t test___riscv_vaadd_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m4_t test___riscv_vaadd_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint8m8_t test___riscv_vaadd_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf4_t test___riscv_vaadd_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16mf2_t test___riscv_vaadd_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m1_t test___riscv_vaadd_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m2_t test___riscv_vaadd_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m4_t test___riscv_vaadd_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint16m8_t test___riscv_vaadd_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32mf2_t test___riscv_vaadd_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m1_t test___riscv_vaadd_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m2_t test___riscv_vaadd_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m4_t test___riscv_vaadd_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint32m8_t test___riscv_vaadd_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m1_t test___riscv_vaadd_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m2_t test___riscv_vaadd_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m4_t test___riscv_vaadd_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,31);
+}
+
+
+vint64m8_t test___riscv_vaadd_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tumu_rv64-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tumu_rv64-3.C
new file mode 100644
index 00000000000..0ec73931b4f
--- /dev/null
+++ b/gcc/testsuite/g++.target/riscv/rvv/base/vaadd_vx_tumu_rv64-3.C
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vint8mf8_t test___riscv_vaadd_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf4_t test___riscv_vaadd_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8mf2_t test___riscv_vaadd_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m1_t test___riscv_vaadd_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m2_t test___riscv_vaadd_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m4_t test___riscv_vaadd_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint8m8_t test___riscv_vaadd_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t op1,int8_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf4_t test___riscv_vaadd_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16mf2_t test___riscv_vaadd_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m1_t test___riscv_vaadd_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m2_t test___riscv_vaadd_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m4_t test___riscv_vaadd_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint16m8_t test___riscv_vaadd_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t op1,int16_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32mf2_t test___riscv_vaadd_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m1_t test___riscv_vaadd_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m2_t test___riscv_vaadd_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m4_t test___riscv_vaadd_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint32m8_t test___riscv_vaadd_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t op1,int32_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m1_t test___riscv_vaadd_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m2_t test___riscv_vaadd_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m4_t test___riscv_vaadd_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,32);
+}
+
+
+vint64m8_t test___riscv_vaadd_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t op1,int64_t op2,size_t vl)
+{
+    return __riscv_vaadd_tumu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vaadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
-- 
2.36.3