From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtpbg156.qq.com (smtpbg156.qq.com [15.184.82.18]) by sourceware.org (Postfix) with ESMTPS id 9F0CF3858D28 for ; Fri, 10 Feb 2023 10:19:47 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 9F0CF3858D28 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp73t1676024380tpi6j0qv Received: from rios-cad5.localdomain ( [58.60.1.11]) by bizesmtp.qq.com (ESMTP) with id ; Fri, 10 Feb 2023 18:19:39 +0800 (CST) X-QQ-SSF: 01400000000000E0L000000A0000000 X-QQ-FEAT: CR3LFp2JE4lb6C0tD25ByJbQMMy8AGrKSY2tWPiqAeByDkvaMCWHimdIWgpgf h7ryz/tNq2NoPWRDxeFKHUOVu+eSwLVM4xLqTHogyA364SGkYndWy5+NheFOOOwxmHbt2m6 nGhM5ifIAOhChTkmyTLGr5F3UC4tGeFfKDLscQkZcVWmi97bNuoubbLMgBuNBoywnetFbar +amnVZlPg75p6ndop+ycjQAY1GI7xno6l4nXq0XrEzSjCQgV8InJRtcuOUZRhh3yQ+bM4ww a014fMCCZqCQ6oMxCacGWadr3ZH5GbuE7aq7ZmhaC0ticH9IVooahTFbZkrnEN3D13rOyQV NQfOE55SHmlwLtGub7p9SuSF3FJ4Fv0ZyLdwIvl2VpABOwhEbCGBwvYTmhRDNKl3eN39b5o ZKtphyNuEI8= X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: Add Full 'v' extension predicate to vsmul intrinsic Date: Fri, 10 Feb 2023 18:19:37 +0800 Message-Id: <20230210101937.137591-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-12.9 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Ju-Zhe Zhong According to RVV ISA, vsmul are not supported for EEW=64 in Zve64*, so add Full 'V' extension required into predicate of vsmul intrinsics. gcc/ChangeLog: * config/riscv/riscv-vector-builtins-functions.def (vsmul): Change iterators. --- gcc/config/riscv/riscv-vector-builtins-functions.def | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def index cea44c8fb20..66fa63530f3 100644 --- a/gcc/config/riscv/riscv-vector-builtins-functions.def +++ b/gcc/config/riscv/riscv-vector-builtins-functions.def @@ -170,14 +170,14 @@ DEF_RVV_FUNCTION (vaadd, alu, full_preds, i_vvv_ops) DEF_RVV_FUNCTION (vasub, alu, full_preds, i_vvv_ops) DEF_RVV_FUNCTION (vaaddu, alu, full_preds, u_vvv_ops) DEF_RVV_FUNCTION (vasubu, alu, full_preds, u_vvv_ops) -DEF_RVV_FUNCTION (vsmul, alu, full_preds, i_vvv_ops) +DEF_RVV_FUNCTION (vsmul, alu, full_preds, full_v_i_vvv_ops) DEF_RVV_FUNCTION (vssra, alu, full_preds, i_shift_vvv_ops) DEF_RVV_FUNCTION (vssrl, alu, full_preds, u_shift_vvv_ops) DEF_RVV_FUNCTION (vaadd, alu, full_preds, i_vvx_ops) DEF_RVV_FUNCTION (vasub, alu, full_preds, i_vvx_ops) DEF_RVV_FUNCTION (vaaddu, alu, full_preds, u_vvx_ops) DEF_RVV_FUNCTION (vasubu, alu, full_preds, u_vvx_ops) -DEF_RVV_FUNCTION (vsmul, alu, full_preds, i_vvx_ops) +DEF_RVV_FUNCTION (vsmul, alu, full_preds, full_v_i_vvx_ops) DEF_RVV_FUNCTION (vssra, alu, full_preds, i_shift_vvx_ops) DEF_RVV_FUNCTION (vssrl, alu, full_preds, u_shift_vvx_ops) DEF_RVV_FUNCTION (vnclipu, narrow_alu, full_preds, u_narrow_shift_vwv_ops) -- 2.36.3