[PATCH] RISC-V: Add vmsle vv C api tests

[juzhe.zhong@rivai.ai]

From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/rvv/base/vmsle_vv-1.c: New test.
        * gcc.target/riscv/rvv/base/vmsle_vv-2.c: New test.
        * gcc.target/riscv/rvv/base/vmsle_vv-3.c: New test.
        * gcc.target/riscv/rvv/base/vmsle_vv_m-1.c: New test.
        * gcc.target/riscv/rvv/base/vmsle_vv_m-2.c: New test.
        * gcc.target/riscv/rvv/base/vmsle_vv_m-3.c: New test.
        * gcc.target/riscv/rvv/base/vmsle_vv_mu-1.c: New test.
        * gcc.target/riscv/rvv/base/vmsle_vv_mu-2.c: New test.
        * gcc.target/riscv/rvv/base/vmsle_vv_mu-3.c: New test.
        * gcc.target/riscv/rvv/base/vmsleu_vv-1.c: New test.
        * gcc.target/riscv/rvv/base/vmsleu_vv-2.c: New test.
        * gcc.target/riscv/rvv/base/vmsleu_vv-3.c: New test.
        * gcc.target/riscv/rvv/base/vmsleu_vv_m-1.c: New test.
        * gcc.target/riscv/rvv/base/vmsleu_vv_m-2.c: New test.
        * gcc.target/riscv/rvv/base/vmsleu_vv_m-3.c: New test.
        * gcc.target/riscv/rvv/base/vmsleu_vv_mu-1.c: New test.
        * gcc.target/riscv/rvv/base/vmsleu_vv_mu-2.c: New test.
        * gcc.target/riscv/rvv/base/vmsleu_vv_mu-3.c: New test.

---
 .../gcc.target/riscv/rvv/base/vmsle_vv-1.c    | 160 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vmsle_vv-2.c    | 160 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vmsle_vv-3.c    | 160 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vmsle_vv_m-1.c  | 160 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vmsle_vv_m-2.c  | 160 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vmsle_vv_m-3.c  | 160 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vmsle_vv_mu-1.c | 160 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vmsle_vv_mu-2.c | 160 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vmsle_vv_mu-3.c | 160 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vmsleu_vv-1.c   | 160 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vmsleu_vv-2.c   | 160 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vmsleu_vv-3.c   | 160 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vmsleu_vv_m-1.c | 160 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vmsleu_vv_m-2.c | 160 ++++++++++++++++++
 .../gcc.target/riscv/rvv/base/vmsleu_vv_m-3.c | 160 ++++++++++++++++++
 .../riscv/rvv/base/vmsleu_vv_mu-1.c           | 160 ++++++++++++++++++
 .../riscv/rvv/base/vmsleu_vv_mu-2.c           | 160 ++++++++++++++++++
 .../riscv/rvv/base/vmsleu_vv_mu-3.c           | 160 ++++++++++++++++++
 18 files changed, 2880 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsle_vv-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsle_vv-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsle_vv-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsle_vv_m-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsle_vv_m-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsle_vv_m-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsle_vv_mu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsle_vv_mu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsle_vv_mu-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsleu_vv-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsleu_vv-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsleu_vv-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsleu_vv_m-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsleu_vv_m-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsleu_vv_m-3.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsleu_vv_mu-1.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsleu_vv_mu-2.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmsleu_vv_mu-3.c

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsle_vv-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsle_vv-1.c
new file mode 100644
index 00000000000..dd770a6d0c1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsle_vv-1.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsle_vv_i8mf8_b64(vbool64_t mask,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i8mf8_b64(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsle_vv_i8mf4_b32(vbool32_t mask,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i8mf4_b32(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsle_vv_i8mf2_b16(vbool16_t mask,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i8mf2_b16(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsle_vv_i8m1_b8(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i8m1_b8(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsle_vv_i8m2_b4(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i8m2_b4(op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsle_vv_i8m4_b2(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i8m4_b2(op1,op2,vl);
+}
+
+
+vbool1_t test___riscv_vmsle_vv_i8m8_b1(vbool1_t mask,vint8m8_t op1,vint8m8_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i8m8_b1(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsle_vv_i16mf4_b64(vbool64_t mask,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i16mf4_b64(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsle_vv_i16mf2_b32(vbool32_t mask,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i16mf2_b32(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsle_vv_i16m1_b16(vbool16_t mask,vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i16m1_b16(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsle_vv_i16m2_b8(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i16m2_b8(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsle_vv_i16m4_b4(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i16m4_b4(op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsle_vv_i16m8_b2(vbool2_t mask,vint16m8_t op1,vint16m8_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i16m8_b2(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsle_vv_i32mf2_b64(vbool64_t mask,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i32mf2_b64(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsle_vv_i32m1_b32(vbool32_t mask,vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i32m1_b32(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsle_vv_i32m2_b16(vbool16_t mask,vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i32m2_b16(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsle_vv_i32m4_b8(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i32m4_b8(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsle_vv_i32m8_b4(vbool4_t mask,vint32m8_t op1,vint32m8_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i32m8_b4(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsle_vv_i64m1_b64(vbool64_t mask,vint64m1_t op1,vint64m1_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i64m1_b64(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsle_vv_i64m2_b32(vbool32_t mask,vint64m2_t op1,vint64m2_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i64m2_b32(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsle_vv_i64m4_b16(vbool16_t mask,vint64m4_t op1,vint64m4_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i64m4_b16(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsle_vv_i64m8_b8(vbool8_t mask,vint64m8_t op1,vint64m8_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i64m8_b8(op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsle_vv-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsle_vv-2.c
new file mode 100644
index 00000000000..c347c38214e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsle_vv-2.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsle_vv_i8mf8_b64(vbool64_t mask,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i8mf8_b64(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsle_vv_i8mf4_b32(vbool32_t mask,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i8mf4_b32(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsle_vv_i8mf2_b16(vbool16_t mask,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i8mf2_b16(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsle_vv_i8m1_b8(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i8m1_b8(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsle_vv_i8m2_b4(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i8m2_b4(op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsle_vv_i8m4_b2(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i8m4_b2(op1,op2,31);
+}
+
+
+vbool1_t test___riscv_vmsle_vv_i8m8_b1(vbool1_t mask,vint8m8_t op1,vint8m8_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i8m8_b1(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsle_vv_i16mf4_b64(vbool64_t mask,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i16mf4_b64(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsle_vv_i16mf2_b32(vbool32_t mask,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i16mf2_b32(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsle_vv_i16m1_b16(vbool16_t mask,vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i16m1_b16(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsle_vv_i16m2_b8(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i16m2_b8(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsle_vv_i16m4_b4(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i16m4_b4(op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsle_vv_i16m8_b2(vbool2_t mask,vint16m8_t op1,vint16m8_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i16m8_b2(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsle_vv_i32mf2_b64(vbool64_t mask,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i32mf2_b64(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsle_vv_i32m1_b32(vbool32_t mask,vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i32m1_b32(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsle_vv_i32m2_b16(vbool16_t mask,vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i32m2_b16(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsle_vv_i32m4_b8(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i32m4_b8(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsle_vv_i32m8_b4(vbool4_t mask,vint32m8_t op1,vint32m8_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i32m8_b4(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsle_vv_i64m1_b64(vbool64_t mask,vint64m1_t op1,vint64m1_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i64m1_b64(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsle_vv_i64m2_b32(vbool32_t mask,vint64m2_t op1,vint64m2_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i64m2_b32(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsle_vv_i64m4_b16(vbool16_t mask,vint64m4_t op1,vint64m4_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i64m4_b16(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsle_vv_i64m8_b8(vbool8_t mask,vint64m8_t op1,vint64m8_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i64m8_b8(op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsle_vv-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsle_vv-3.c
new file mode 100644
index 00000000000..e341ce2fdd7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsle_vv-3.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsle_vv_i8mf8_b64(vbool64_t mask,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i8mf8_b64(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsle_vv_i8mf4_b32(vbool32_t mask,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i8mf4_b32(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsle_vv_i8mf2_b16(vbool16_t mask,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i8mf2_b16(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsle_vv_i8m1_b8(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i8m1_b8(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsle_vv_i8m2_b4(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i8m2_b4(op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsle_vv_i8m4_b2(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i8m4_b2(op1,op2,32);
+}
+
+
+vbool1_t test___riscv_vmsle_vv_i8m8_b1(vbool1_t mask,vint8m8_t op1,vint8m8_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i8m8_b1(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsle_vv_i16mf4_b64(vbool64_t mask,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i16mf4_b64(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsle_vv_i16mf2_b32(vbool32_t mask,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i16mf2_b32(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsle_vv_i16m1_b16(vbool16_t mask,vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i16m1_b16(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsle_vv_i16m2_b8(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i16m2_b8(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsle_vv_i16m4_b4(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i16m4_b4(op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsle_vv_i16m8_b2(vbool2_t mask,vint16m8_t op1,vint16m8_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i16m8_b2(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsle_vv_i32mf2_b64(vbool64_t mask,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i32mf2_b64(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsle_vv_i32m1_b32(vbool32_t mask,vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i32m1_b32(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsle_vv_i32m2_b16(vbool16_t mask,vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i32m2_b16(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsle_vv_i32m4_b8(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i32m4_b8(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsle_vv_i32m8_b4(vbool4_t mask,vint32m8_t op1,vint32m8_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i32m8_b4(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsle_vv_i64m1_b64(vbool64_t mask,vint64m1_t op1,vint64m1_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i64m1_b64(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsle_vv_i64m2_b32(vbool32_t mask,vint64m2_t op1,vint64m2_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i64m2_b32(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsle_vv_i64m4_b16(vbool16_t mask,vint64m4_t op1,vint64m4_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i64m4_b16(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsle_vv_i64m8_b8(vbool8_t mask,vint64m8_t op1,vint64m8_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i64m8_b8(op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsle_vv_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsle_vv_m-1.c
new file mode 100644
index 00000000000..c856a4def26
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsle_vv_m-1.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsle_vv_i8mf8_b64_m(vbool64_t mask,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i8mf8_b64_m(mask,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsle_vv_i8mf4_b32_m(vbool32_t mask,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i8mf4_b32_m(mask,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsle_vv_i8mf2_b16_m(vbool16_t mask,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i8mf2_b16_m(mask,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsle_vv_i8m1_b8_m(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i8m1_b8_m(mask,op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsle_vv_i8m2_b4_m(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i8m2_b4_m(mask,op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsle_vv_i8m4_b2_m(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i8m4_b2_m(mask,op1,op2,vl);
+}
+
+
+vbool1_t test___riscv_vmsle_vv_i8m8_b1_m(vbool1_t mask,vint8m8_t op1,vint8m8_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i8m8_b1_m(mask,op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsle_vv_i16mf4_b64_m(vbool64_t mask,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i16mf4_b64_m(mask,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsle_vv_i16mf2_b32_m(vbool32_t mask,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i16mf2_b32_m(mask,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsle_vv_i16m1_b16_m(vbool16_t mask,vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i16m1_b16_m(mask,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsle_vv_i16m2_b8_m(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i16m2_b8_m(mask,op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsle_vv_i16m4_b4_m(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i16m4_b4_m(mask,op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsle_vv_i16m8_b2_m(vbool2_t mask,vint16m8_t op1,vint16m8_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i16m8_b2_m(mask,op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsle_vv_i32mf2_b64_m(vbool64_t mask,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i32mf2_b64_m(mask,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsle_vv_i32m1_b32_m(vbool32_t mask,vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i32m1_b32_m(mask,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsle_vv_i32m2_b16_m(vbool16_t mask,vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i32m2_b16_m(mask,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsle_vv_i32m4_b8_m(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i32m4_b8_m(mask,op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsle_vv_i32m8_b4_m(vbool4_t mask,vint32m8_t op1,vint32m8_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i32m8_b4_m(mask,op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsle_vv_i64m1_b64_m(vbool64_t mask,vint64m1_t op1,vint64m1_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i64m1_b64_m(mask,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsle_vv_i64m2_b32_m(vbool32_t mask,vint64m2_t op1,vint64m2_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i64m2_b32_m(mask,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsle_vv_i64m4_b16_m(vbool16_t mask,vint64m4_t op1,vint64m4_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i64m4_b16_m(mask,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsle_vv_i64m8_b8_m(vbool8_t mask,vint64m8_t op1,vint64m8_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i64m8_b8_m(mask,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsle_vv_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsle_vv_m-2.c
new file mode 100644
index 00000000000..dcc72c3171d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsle_vv_m-2.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsle_vv_i8mf8_b64_m(vbool64_t mask,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i8mf8_b64_m(mask,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsle_vv_i8mf4_b32_m(vbool32_t mask,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i8mf4_b32_m(mask,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsle_vv_i8mf2_b16_m(vbool16_t mask,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i8mf2_b16_m(mask,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsle_vv_i8m1_b8_m(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i8m1_b8_m(mask,op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsle_vv_i8m2_b4_m(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i8m2_b4_m(mask,op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsle_vv_i8m4_b2_m(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i8m4_b2_m(mask,op1,op2,31);
+}
+
+
+vbool1_t test___riscv_vmsle_vv_i8m8_b1_m(vbool1_t mask,vint8m8_t op1,vint8m8_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i8m8_b1_m(mask,op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsle_vv_i16mf4_b64_m(vbool64_t mask,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i16mf4_b64_m(mask,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsle_vv_i16mf2_b32_m(vbool32_t mask,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i16mf2_b32_m(mask,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsle_vv_i16m1_b16_m(vbool16_t mask,vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i16m1_b16_m(mask,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsle_vv_i16m2_b8_m(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i16m2_b8_m(mask,op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsle_vv_i16m4_b4_m(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i16m4_b4_m(mask,op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsle_vv_i16m8_b2_m(vbool2_t mask,vint16m8_t op1,vint16m8_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i16m8_b2_m(mask,op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsle_vv_i32mf2_b64_m(vbool64_t mask,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i32mf2_b64_m(mask,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsle_vv_i32m1_b32_m(vbool32_t mask,vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i32m1_b32_m(mask,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsle_vv_i32m2_b16_m(vbool16_t mask,vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i32m2_b16_m(mask,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsle_vv_i32m4_b8_m(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i32m4_b8_m(mask,op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsle_vv_i32m8_b4_m(vbool4_t mask,vint32m8_t op1,vint32m8_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i32m8_b4_m(mask,op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsle_vv_i64m1_b64_m(vbool64_t mask,vint64m1_t op1,vint64m1_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i64m1_b64_m(mask,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsle_vv_i64m2_b32_m(vbool32_t mask,vint64m2_t op1,vint64m2_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i64m2_b32_m(mask,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsle_vv_i64m4_b16_m(vbool16_t mask,vint64m4_t op1,vint64m4_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i64m4_b16_m(mask,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsle_vv_i64m8_b8_m(vbool8_t mask,vint64m8_t op1,vint64m8_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i64m8_b8_m(mask,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsle_vv_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsle_vv_m-3.c
new file mode 100644
index 00000000000..b112d5d5cf3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsle_vv_m-3.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsle_vv_i8mf8_b64_m(vbool64_t mask,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i8mf8_b64_m(mask,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsle_vv_i8mf4_b32_m(vbool32_t mask,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i8mf4_b32_m(mask,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsle_vv_i8mf2_b16_m(vbool16_t mask,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i8mf2_b16_m(mask,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsle_vv_i8m1_b8_m(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i8m1_b8_m(mask,op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsle_vv_i8m2_b4_m(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i8m2_b4_m(mask,op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsle_vv_i8m4_b2_m(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i8m4_b2_m(mask,op1,op2,32);
+}
+
+
+vbool1_t test___riscv_vmsle_vv_i8m8_b1_m(vbool1_t mask,vint8m8_t op1,vint8m8_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i8m8_b1_m(mask,op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsle_vv_i16mf4_b64_m(vbool64_t mask,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i16mf4_b64_m(mask,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsle_vv_i16mf2_b32_m(vbool32_t mask,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i16mf2_b32_m(mask,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsle_vv_i16m1_b16_m(vbool16_t mask,vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i16m1_b16_m(mask,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsle_vv_i16m2_b8_m(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i16m2_b8_m(mask,op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsle_vv_i16m4_b4_m(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i16m4_b4_m(mask,op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsle_vv_i16m8_b2_m(vbool2_t mask,vint16m8_t op1,vint16m8_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i16m8_b2_m(mask,op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsle_vv_i32mf2_b64_m(vbool64_t mask,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i32mf2_b64_m(mask,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsle_vv_i32m1_b32_m(vbool32_t mask,vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i32m1_b32_m(mask,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsle_vv_i32m2_b16_m(vbool16_t mask,vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i32m2_b16_m(mask,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsle_vv_i32m4_b8_m(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i32m4_b8_m(mask,op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsle_vv_i32m8_b4_m(vbool4_t mask,vint32m8_t op1,vint32m8_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i32m8_b4_m(mask,op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsle_vv_i64m1_b64_m(vbool64_t mask,vint64m1_t op1,vint64m1_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i64m1_b64_m(mask,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsle_vv_i64m2_b32_m(vbool32_t mask,vint64m2_t op1,vint64m2_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i64m2_b32_m(mask,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsle_vv_i64m4_b16_m(vbool16_t mask,vint64m4_t op1,vint64m4_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i64m4_b16_m(mask,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsle_vv_i64m8_b8_m(vbool8_t mask,vint64m8_t op1,vint64m8_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i64m8_b8_m(mask,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsle_vv_mu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsle_vv_mu-1.c
new file mode 100644
index 00000000000..8e3ea589406
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsle_vv_mu-1.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsle_vv_i8mf8_b64_mu(vbool64_t mask,vbool64_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i8mf8_b64_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsle_vv_i8mf4_b32_mu(vbool32_t mask,vbool32_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i8mf4_b32_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsle_vv_i8mf2_b16_mu(vbool16_t mask,vbool16_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i8mf2_b16_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsle_vv_i8m1_b8_mu(vbool8_t mask,vbool8_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i8m1_b8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsle_vv_i8m2_b4_mu(vbool4_t mask,vbool4_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i8m2_b4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsle_vv_i8m4_b2_mu(vbool2_t mask,vbool2_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i8m4_b2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool1_t test___riscv_vmsle_vv_i8m8_b1_mu(vbool1_t mask,vbool1_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i8m8_b1_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsle_vv_i16mf4_b64_mu(vbool64_t mask,vbool64_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i16mf4_b64_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsle_vv_i16mf2_b32_mu(vbool32_t mask,vbool32_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i16mf2_b32_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsle_vv_i16m1_b16_mu(vbool16_t mask,vbool16_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i16m1_b16_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsle_vv_i16m2_b8_mu(vbool8_t mask,vbool8_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i16m2_b8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsle_vv_i16m4_b4_mu(vbool4_t mask,vbool4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i16m4_b4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsle_vv_i16m8_b2_mu(vbool2_t mask,vbool2_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i16m8_b2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsle_vv_i32mf2_b64_mu(vbool64_t mask,vbool64_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i32mf2_b64_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsle_vv_i32m1_b32_mu(vbool32_t mask,vbool32_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i32m1_b32_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsle_vv_i32m2_b16_mu(vbool16_t mask,vbool16_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i32m2_b16_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsle_vv_i32m4_b8_mu(vbool8_t mask,vbool8_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i32m4_b8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsle_vv_i32m8_b4_mu(vbool4_t mask,vbool4_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i32m8_b4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsle_vv_i64m1_b64_mu(vbool64_t mask,vbool64_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i64m1_b64_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsle_vv_i64m2_b32_mu(vbool32_t mask,vbool32_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i64m2_b32_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsle_vv_i64m4_b16_mu(vbool16_t mask,vbool16_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i64m4_b16_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsle_vv_i64m8_b8_mu(vbool8_t mask,vbool8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i64m8_b8_mu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsle_vv_mu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsle_vv_mu-2.c
new file mode 100644
index 00000000000..0bb6b8c3117
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsle_vv_mu-2.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsle_vv_i8mf8_b64_mu(vbool64_t mask,vbool64_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i8mf8_b64_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsle_vv_i8mf4_b32_mu(vbool32_t mask,vbool32_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i8mf4_b32_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsle_vv_i8mf2_b16_mu(vbool16_t mask,vbool16_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i8mf2_b16_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsle_vv_i8m1_b8_mu(vbool8_t mask,vbool8_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i8m1_b8_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsle_vv_i8m2_b4_mu(vbool4_t mask,vbool4_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i8m2_b4_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsle_vv_i8m4_b2_mu(vbool2_t mask,vbool2_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i8m4_b2_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool1_t test___riscv_vmsle_vv_i8m8_b1_mu(vbool1_t mask,vbool1_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i8m8_b1_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsle_vv_i16mf4_b64_mu(vbool64_t mask,vbool64_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i16mf4_b64_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsle_vv_i16mf2_b32_mu(vbool32_t mask,vbool32_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i16mf2_b32_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsle_vv_i16m1_b16_mu(vbool16_t mask,vbool16_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i16m1_b16_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsle_vv_i16m2_b8_mu(vbool8_t mask,vbool8_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i16m2_b8_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsle_vv_i16m4_b4_mu(vbool4_t mask,vbool4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i16m4_b4_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsle_vv_i16m8_b2_mu(vbool2_t mask,vbool2_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i16m8_b2_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsle_vv_i32mf2_b64_mu(vbool64_t mask,vbool64_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i32mf2_b64_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsle_vv_i32m1_b32_mu(vbool32_t mask,vbool32_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i32m1_b32_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsle_vv_i32m2_b16_mu(vbool16_t mask,vbool16_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i32m2_b16_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsle_vv_i32m4_b8_mu(vbool8_t mask,vbool8_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i32m4_b8_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsle_vv_i32m8_b4_mu(vbool4_t mask,vbool4_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i32m8_b4_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsle_vv_i64m1_b64_mu(vbool64_t mask,vbool64_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i64m1_b64_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsle_vv_i64m2_b32_mu(vbool32_t mask,vbool32_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i64m2_b32_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsle_vv_i64m4_b16_mu(vbool16_t mask,vbool16_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i64m4_b16_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsle_vv_i64m8_b8_mu(vbool8_t mask,vbool8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i64m8_b8_mu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsle_vv_mu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsle_vv_mu-3.c
new file mode 100644
index 00000000000..e81dc108286
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsle_vv_mu-3.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsle_vv_i8mf8_b64_mu(vbool64_t mask,vbool64_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i8mf8_b64_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsle_vv_i8mf4_b32_mu(vbool32_t mask,vbool32_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i8mf4_b32_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsle_vv_i8mf2_b16_mu(vbool16_t mask,vbool16_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i8mf2_b16_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsle_vv_i8m1_b8_mu(vbool8_t mask,vbool8_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i8m1_b8_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsle_vv_i8m2_b4_mu(vbool4_t mask,vbool4_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i8m2_b4_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsle_vv_i8m4_b2_mu(vbool2_t mask,vbool2_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i8m4_b2_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool1_t test___riscv_vmsle_vv_i8m8_b1_mu(vbool1_t mask,vbool1_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i8m8_b1_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsle_vv_i16mf4_b64_mu(vbool64_t mask,vbool64_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i16mf4_b64_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsle_vv_i16mf2_b32_mu(vbool32_t mask,vbool32_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i16mf2_b32_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsle_vv_i16m1_b16_mu(vbool16_t mask,vbool16_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i16m1_b16_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsle_vv_i16m2_b8_mu(vbool8_t mask,vbool8_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i16m2_b8_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsle_vv_i16m4_b4_mu(vbool4_t mask,vbool4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i16m4_b4_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsle_vv_i16m8_b2_mu(vbool2_t mask,vbool2_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i16m8_b2_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsle_vv_i32mf2_b64_mu(vbool64_t mask,vbool64_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i32mf2_b64_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsle_vv_i32m1_b32_mu(vbool32_t mask,vbool32_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i32m1_b32_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsle_vv_i32m2_b16_mu(vbool16_t mask,vbool16_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i32m2_b16_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsle_vv_i32m4_b8_mu(vbool8_t mask,vbool8_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i32m4_b8_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsle_vv_i32m8_b4_mu(vbool4_t mask,vbool4_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i32m8_b4_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsle_vv_i64m1_b64_mu(vbool64_t mask,vbool64_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i64m1_b64_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsle_vv_i64m2_b32_mu(vbool32_t mask,vbool32_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i64m2_b32_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsle_vv_i64m4_b16_mu(vbool16_t mask,vbool16_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i64m4_b16_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsle_vv_i64m8_b8_mu(vbool8_t mask,vbool8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl)
+{
+    return __riscv_vmsle_vv_i64m8_b8_mu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vmsle\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsleu_vv-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsleu_vv-1.c
new file mode 100644
index 00000000000..98ce5cedfaa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsleu_vv-1.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsleu_vv_u8mf8_b64(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u8mf8_b64(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsleu_vv_u8mf4_b32(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u8mf4_b32(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsleu_vv_u8mf2_b16(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u8mf2_b16(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsleu_vv_u8m1_b8(vbool8_t mask,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u8m1_b8(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsleu_vv_u8m2_b4(vbool4_t mask,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u8m2_b4(op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsleu_vv_u8m4_b2(vbool2_t mask,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u8m4_b2(op1,op2,vl);
+}
+
+
+vbool1_t test___riscv_vmsleu_vv_u8m8_b1(vbool1_t mask,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u8m8_b1(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsleu_vv_u16mf4_b64(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u16mf4_b64(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsleu_vv_u16mf2_b32(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u16mf2_b32(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsleu_vv_u16m1_b16(vbool16_t mask,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u16m1_b16(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsleu_vv_u16m2_b8(vbool8_t mask,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u16m2_b8(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsleu_vv_u16m4_b4(vbool4_t mask,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u16m4_b4(op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsleu_vv_u16m8_b2(vbool2_t mask,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u16m8_b2(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsleu_vv_u32mf2_b64(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u32mf2_b64(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsleu_vv_u32m1_b32(vbool32_t mask,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u32m1_b32(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsleu_vv_u32m2_b16(vbool16_t mask,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u32m2_b16(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsleu_vv_u32m4_b8(vbool8_t mask,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u32m4_b8(op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsleu_vv_u32m8_b4(vbool4_t mask,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u32m8_b4(op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsleu_vv_u64m1_b64(vbool64_t mask,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u64m1_b64(op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsleu_vv_u64m2_b32(vbool32_t mask,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u64m2_b32(op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsleu_vv_u64m4_b16(vbool16_t mask,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u64m4_b16(op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsleu_vv_u64m8_b8(vbool8_t mask,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u64m8_b8(op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsleu_vv-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsleu_vv-2.c
new file mode 100644
index 00000000000..3a461d47396
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsleu_vv-2.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsleu_vv_u8mf8_b64(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u8mf8_b64(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsleu_vv_u8mf4_b32(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u8mf4_b32(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsleu_vv_u8mf2_b16(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u8mf2_b16(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsleu_vv_u8m1_b8(vbool8_t mask,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u8m1_b8(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsleu_vv_u8m2_b4(vbool4_t mask,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u8m2_b4(op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsleu_vv_u8m4_b2(vbool2_t mask,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u8m4_b2(op1,op2,31);
+}
+
+
+vbool1_t test___riscv_vmsleu_vv_u8m8_b1(vbool1_t mask,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u8m8_b1(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsleu_vv_u16mf4_b64(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u16mf4_b64(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsleu_vv_u16mf2_b32(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u16mf2_b32(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsleu_vv_u16m1_b16(vbool16_t mask,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u16m1_b16(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsleu_vv_u16m2_b8(vbool8_t mask,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u16m2_b8(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsleu_vv_u16m4_b4(vbool4_t mask,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u16m4_b4(op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsleu_vv_u16m8_b2(vbool2_t mask,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u16m8_b2(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsleu_vv_u32mf2_b64(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u32mf2_b64(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsleu_vv_u32m1_b32(vbool32_t mask,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u32m1_b32(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsleu_vv_u32m2_b16(vbool16_t mask,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u32m2_b16(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsleu_vv_u32m4_b8(vbool8_t mask,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u32m4_b8(op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsleu_vv_u32m8_b4(vbool4_t mask,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u32m8_b4(op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsleu_vv_u64m1_b64(vbool64_t mask,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u64m1_b64(op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsleu_vv_u64m2_b32(vbool32_t mask,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u64m2_b32(op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsleu_vv_u64m4_b16(vbool16_t mask,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u64m4_b16(op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsleu_vv_u64m8_b8(vbool8_t mask,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u64m8_b8(op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsleu_vv-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsleu_vv-3.c
new file mode 100644
index 00000000000..354c02c6ee4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsleu_vv-3.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsleu_vv_u8mf8_b64(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u8mf8_b64(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsleu_vv_u8mf4_b32(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u8mf4_b32(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsleu_vv_u8mf2_b16(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u8mf2_b16(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsleu_vv_u8m1_b8(vbool8_t mask,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u8m1_b8(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsleu_vv_u8m2_b4(vbool4_t mask,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u8m2_b4(op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsleu_vv_u8m4_b2(vbool2_t mask,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u8m4_b2(op1,op2,32);
+}
+
+
+vbool1_t test___riscv_vmsleu_vv_u8m8_b1(vbool1_t mask,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u8m8_b1(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsleu_vv_u16mf4_b64(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u16mf4_b64(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsleu_vv_u16mf2_b32(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u16mf2_b32(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsleu_vv_u16m1_b16(vbool16_t mask,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u16m1_b16(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsleu_vv_u16m2_b8(vbool8_t mask,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u16m2_b8(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsleu_vv_u16m4_b4(vbool4_t mask,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u16m4_b4(op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsleu_vv_u16m8_b2(vbool2_t mask,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u16m8_b2(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsleu_vv_u32mf2_b64(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u32mf2_b64(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsleu_vv_u32m1_b32(vbool32_t mask,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u32m1_b32(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsleu_vv_u32m2_b16(vbool16_t mask,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u32m2_b16(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsleu_vv_u32m4_b8(vbool8_t mask,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u32m4_b8(op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsleu_vv_u32m8_b4(vbool4_t mask,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u32m8_b4(op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsleu_vv_u64m1_b64(vbool64_t mask,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u64m1_b64(op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsleu_vv_u64m2_b32(vbool32_t mask,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u64m2_b32(op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsleu_vv_u64m4_b16(vbool16_t mask,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u64m4_b16(op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsleu_vv_u64m8_b8(vbool8_t mask,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u64m8_b8(op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsleu_vv_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsleu_vv_m-1.c
new file mode 100644
index 00000000000..9abffb1ac10
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsleu_vv_m-1.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsleu_vv_u8mf8_b64_m(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u8mf8_b64_m(mask,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsleu_vv_u8mf4_b32_m(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u8mf4_b32_m(mask,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsleu_vv_u8mf2_b16_m(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u8mf2_b16_m(mask,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsleu_vv_u8m1_b8_m(vbool8_t mask,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u8m1_b8_m(mask,op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsleu_vv_u8m2_b4_m(vbool4_t mask,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u8m2_b4_m(mask,op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsleu_vv_u8m4_b2_m(vbool2_t mask,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u8m4_b2_m(mask,op1,op2,vl);
+}
+
+
+vbool1_t test___riscv_vmsleu_vv_u8m8_b1_m(vbool1_t mask,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u8m8_b1_m(mask,op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsleu_vv_u16mf4_b64_m(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u16mf4_b64_m(mask,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsleu_vv_u16mf2_b32_m(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u16mf2_b32_m(mask,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsleu_vv_u16m1_b16_m(vbool16_t mask,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u16m1_b16_m(mask,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsleu_vv_u16m2_b8_m(vbool8_t mask,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u16m2_b8_m(mask,op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsleu_vv_u16m4_b4_m(vbool4_t mask,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u16m4_b4_m(mask,op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsleu_vv_u16m8_b2_m(vbool2_t mask,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u16m8_b2_m(mask,op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsleu_vv_u32mf2_b64_m(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u32mf2_b64_m(mask,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsleu_vv_u32m1_b32_m(vbool32_t mask,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u32m1_b32_m(mask,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsleu_vv_u32m2_b16_m(vbool16_t mask,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u32m2_b16_m(mask,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsleu_vv_u32m4_b8_m(vbool8_t mask,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u32m4_b8_m(mask,op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsleu_vv_u32m8_b4_m(vbool4_t mask,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u32m8_b4_m(mask,op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsleu_vv_u64m1_b64_m(vbool64_t mask,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u64m1_b64_m(mask,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsleu_vv_u64m2_b32_m(vbool32_t mask,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u64m2_b32_m(mask,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsleu_vv_u64m4_b16_m(vbool16_t mask,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u64m4_b16_m(mask,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsleu_vv_u64m8_b8_m(vbool8_t mask,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u64m8_b8_m(mask,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsleu_vv_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsleu_vv_m-2.c
new file mode 100644
index 00000000000..e9749597e0a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsleu_vv_m-2.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsleu_vv_u8mf8_b64_m(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u8mf8_b64_m(mask,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsleu_vv_u8mf4_b32_m(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u8mf4_b32_m(mask,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsleu_vv_u8mf2_b16_m(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u8mf2_b16_m(mask,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsleu_vv_u8m1_b8_m(vbool8_t mask,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u8m1_b8_m(mask,op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsleu_vv_u8m2_b4_m(vbool4_t mask,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u8m2_b4_m(mask,op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsleu_vv_u8m4_b2_m(vbool2_t mask,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u8m4_b2_m(mask,op1,op2,31);
+}
+
+
+vbool1_t test___riscv_vmsleu_vv_u8m8_b1_m(vbool1_t mask,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u8m8_b1_m(mask,op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsleu_vv_u16mf4_b64_m(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u16mf4_b64_m(mask,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsleu_vv_u16mf2_b32_m(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u16mf2_b32_m(mask,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsleu_vv_u16m1_b16_m(vbool16_t mask,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u16m1_b16_m(mask,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsleu_vv_u16m2_b8_m(vbool8_t mask,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u16m2_b8_m(mask,op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsleu_vv_u16m4_b4_m(vbool4_t mask,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u16m4_b4_m(mask,op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsleu_vv_u16m8_b2_m(vbool2_t mask,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u16m8_b2_m(mask,op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsleu_vv_u32mf2_b64_m(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u32mf2_b64_m(mask,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsleu_vv_u32m1_b32_m(vbool32_t mask,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u32m1_b32_m(mask,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsleu_vv_u32m2_b16_m(vbool16_t mask,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u32m2_b16_m(mask,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsleu_vv_u32m4_b8_m(vbool8_t mask,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u32m4_b8_m(mask,op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsleu_vv_u32m8_b4_m(vbool4_t mask,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u32m8_b4_m(mask,op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsleu_vv_u64m1_b64_m(vbool64_t mask,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u64m1_b64_m(mask,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsleu_vv_u64m2_b32_m(vbool32_t mask,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u64m2_b32_m(mask,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsleu_vv_u64m4_b16_m(vbool16_t mask,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u64m4_b16_m(mask,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsleu_vv_u64m8_b8_m(vbool8_t mask,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u64m8_b8_m(mask,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsleu_vv_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsleu_vv_m-3.c
new file mode 100644
index 00000000000..cc05ce6c44e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsleu_vv_m-3.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsleu_vv_u8mf8_b64_m(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u8mf8_b64_m(mask,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsleu_vv_u8mf4_b32_m(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u8mf4_b32_m(mask,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsleu_vv_u8mf2_b16_m(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u8mf2_b16_m(mask,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsleu_vv_u8m1_b8_m(vbool8_t mask,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u8m1_b8_m(mask,op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsleu_vv_u8m2_b4_m(vbool4_t mask,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u8m2_b4_m(mask,op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsleu_vv_u8m4_b2_m(vbool2_t mask,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u8m4_b2_m(mask,op1,op2,32);
+}
+
+
+vbool1_t test___riscv_vmsleu_vv_u8m8_b1_m(vbool1_t mask,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u8m8_b1_m(mask,op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsleu_vv_u16mf4_b64_m(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u16mf4_b64_m(mask,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsleu_vv_u16mf2_b32_m(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u16mf2_b32_m(mask,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsleu_vv_u16m1_b16_m(vbool16_t mask,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u16m1_b16_m(mask,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsleu_vv_u16m2_b8_m(vbool8_t mask,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u16m2_b8_m(mask,op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsleu_vv_u16m4_b4_m(vbool4_t mask,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u16m4_b4_m(mask,op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsleu_vv_u16m8_b2_m(vbool2_t mask,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u16m8_b2_m(mask,op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsleu_vv_u32mf2_b64_m(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u32mf2_b64_m(mask,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsleu_vv_u32m1_b32_m(vbool32_t mask,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u32m1_b32_m(mask,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsleu_vv_u32m2_b16_m(vbool16_t mask,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u32m2_b16_m(mask,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsleu_vv_u32m4_b8_m(vbool8_t mask,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u32m4_b8_m(mask,op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsleu_vv_u32m8_b4_m(vbool4_t mask,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u32m8_b4_m(mask,op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsleu_vv_u64m1_b64_m(vbool64_t mask,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u64m1_b64_m(mask,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsleu_vv_u64m2_b32_m(vbool32_t mask,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u64m2_b32_m(mask,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsleu_vv_u64m4_b16_m(vbool16_t mask,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u64m4_b16_m(mask,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsleu_vv_u64m8_b8_m(vbool8_t mask,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u64m8_b8_m(mask,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsleu_vv_mu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsleu_vv_mu-1.c
new file mode 100644
index 00000000000..6c68309b8cb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsleu_vv_mu-1.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsleu_vv_u8mf8_b64_mu(vbool64_t mask,vbool64_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u8mf8_b64_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsleu_vv_u8mf4_b32_mu(vbool32_t mask,vbool32_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u8mf4_b32_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsleu_vv_u8mf2_b16_mu(vbool16_t mask,vbool16_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u8mf2_b16_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsleu_vv_u8m1_b8_mu(vbool8_t mask,vbool8_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u8m1_b8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsleu_vv_u8m2_b4_mu(vbool4_t mask,vbool4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u8m2_b4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsleu_vv_u8m4_b2_mu(vbool2_t mask,vbool2_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u8m4_b2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool1_t test___riscv_vmsleu_vv_u8m8_b1_mu(vbool1_t mask,vbool1_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u8m8_b1_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsleu_vv_u16mf4_b64_mu(vbool64_t mask,vbool64_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u16mf4_b64_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsleu_vv_u16mf2_b32_mu(vbool32_t mask,vbool32_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u16mf2_b32_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsleu_vv_u16m1_b16_mu(vbool16_t mask,vbool16_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u16m1_b16_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsleu_vv_u16m2_b8_mu(vbool8_t mask,vbool8_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u16m2_b8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsleu_vv_u16m4_b4_mu(vbool4_t mask,vbool4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u16m4_b4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool2_t test___riscv_vmsleu_vv_u16m8_b2_mu(vbool2_t mask,vbool2_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u16m8_b2_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsleu_vv_u32mf2_b64_mu(vbool64_t mask,vbool64_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u32mf2_b64_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsleu_vv_u32m1_b32_mu(vbool32_t mask,vbool32_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u32m1_b32_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsleu_vv_u32m2_b16_mu(vbool16_t mask,vbool16_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u32m2_b16_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsleu_vv_u32m4_b8_mu(vbool8_t mask,vbool8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u32m4_b8_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool4_t test___riscv_vmsleu_vv_u32m8_b4_mu(vbool4_t mask,vbool4_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u32m8_b4_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool64_t test___riscv_vmsleu_vv_u64m1_b64_mu(vbool64_t mask,vbool64_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u64m1_b64_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool32_t test___riscv_vmsleu_vv_u64m2_b32_mu(vbool32_t mask,vbool32_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u64m2_b32_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool16_t test___riscv_vmsleu_vv_u64m4_b16_mu(vbool16_t mask,vbool16_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u64m4_b16_mu(mask,merge,op1,op2,vl);
+}
+
+
+vbool8_t test___riscv_vmsleu_vv_u64m8_b8_mu(vbool8_t mask,vbool8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u64m8_b8_mu(mask,merge,op1,op2,vl);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsleu_vv_mu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsleu_vv_mu-2.c
new file mode 100644
index 00000000000..bb1e9a85a46
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsleu_vv_mu-2.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsleu_vv_u8mf8_b64_mu(vbool64_t mask,vbool64_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u8mf8_b64_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsleu_vv_u8mf4_b32_mu(vbool32_t mask,vbool32_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u8mf4_b32_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsleu_vv_u8mf2_b16_mu(vbool16_t mask,vbool16_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u8mf2_b16_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsleu_vv_u8m1_b8_mu(vbool8_t mask,vbool8_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u8m1_b8_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsleu_vv_u8m2_b4_mu(vbool4_t mask,vbool4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u8m2_b4_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsleu_vv_u8m4_b2_mu(vbool2_t mask,vbool2_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u8m4_b2_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool1_t test___riscv_vmsleu_vv_u8m8_b1_mu(vbool1_t mask,vbool1_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u8m8_b1_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsleu_vv_u16mf4_b64_mu(vbool64_t mask,vbool64_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u16mf4_b64_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsleu_vv_u16mf2_b32_mu(vbool32_t mask,vbool32_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u16mf2_b32_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsleu_vv_u16m1_b16_mu(vbool16_t mask,vbool16_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u16m1_b16_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsleu_vv_u16m2_b8_mu(vbool8_t mask,vbool8_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u16m2_b8_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsleu_vv_u16m4_b4_mu(vbool4_t mask,vbool4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u16m4_b4_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool2_t test___riscv_vmsleu_vv_u16m8_b2_mu(vbool2_t mask,vbool2_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u16m8_b2_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsleu_vv_u32mf2_b64_mu(vbool64_t mask,vbool64_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u32mf2_b64_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsleu_vv_u32m1_b32_mu(vbool32_t mask,vbool32_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u32m1_b32_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsleu_vv_u32m2_b16_mu(vbool16_t mask,vbool16_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u32m2_b16_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsleu_vv_u32m4_b8_mu(vbool8_t mask,vbool8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u32m4_b8_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool4_t test___riscv_vmsleu_vv_u32m8_b4_mu(vbool4_t mask,vbool4_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u32m8_b4_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool64_t test___riscv_vmsleu_vv_u64m1_b64_mu(vbool64_t mask,vbool64_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u64m1_b64_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool32_t test___riscv_vmsleu_vv_u64m2_b32_mu(vbool32_t mask,vbool32_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u64m2_b32_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool16_t test___riscv_vmsleu_vv_u64m4_b16_mu(vbool16_t mask,vbool16_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u64m4_b16_mu(mask,merge,op1,op2,31);
+}
+
+
+vbool8_t test___riscv_vmsleu_vv_u64m8_b8_mu(vbool8_t mask,vbool8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u64m8_b8_mu(mask,merge,op1,op2,31);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmsleu_vv_mu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsleu_vv_mu-3.c
new file mode 100644
index 00000000000..68c819d7a3c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmsleu_vv_mu-3.c
@@ -0,0 +1,160 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
+
+#include "riscv_vector.h"
+
+vbool64_t test___riscv_vmsleu_vv_u8mf8_b64_mu(vbool64_t mask,vbool64_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u8mf8_b64_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsleu_vv_u8mf4_b32_mu(vbool32_t mask,vbool32_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u8mf4_b32_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsleu_vv_u8mf2_b16_mu(vbool16_t mask,vbool16_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u8mf2_b16_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsleu_vv_u8m1_b8_mu(vbool8_t mask,vbool8_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u8m1_b8_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsleu_vv_u8m2_b4_mu(vbool4_t mask,vbool4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u8m2_b4_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsleu_vv_u8m4_b2_mu(vbool2_t mask,vbool2_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u8m4_b2_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool1_t test___riscv_vmsleu_vv_u8m8_b1_mu(vbool1_t mask,vbool1_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u8m8_b1_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsleu_vv_u16mf4_b64_mu(vbool64_t mask,vbool64_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u16mf4_b64_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsleu_vv_u16mf2_b32_mu(vbool32_t mask,vbool32_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u16mf2_b32_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsleu_vv_u16m1_b16_mu(vbool16_t mask,vbool16_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u16m1_b16_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsleu_vv_u16m2_b8_mu(vbool8_t mask,vbool8_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u16m2_b8_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsleu_vv_u16m4_b4_mu(vbool4_t mask,vbool4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u16m4_b4_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool2_t test___riscv_vmsleu_vv_u16m8_b2_mu(vbool2_t mask,vbool2_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u16m8_b2_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsleu_vv_u32mf2_b64_mu(vbool64_t mask,vbool64_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u32mf2_b64_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsleu_vv_u32m1_b32_mu(vbool32_t mask,vbool32_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u32m1_b32_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsleu_vv_u32m2_b16_mu(vbool16_t mask,vbool16_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u32m2_b16_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsleu_vv_u32m4_b8_mu(vbool8_t mask,vbool8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u32m4_b8_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool4_t test___riscv_vmsleu_vv_u32m8_b4_mu(vbool4_t mask,vbool4_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u32m8_b4_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool64_t test___riscv_vmsleu_vv_u64m1_b64_mu(vbool64_t mask,vbool64_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u64m1_b64_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool32_t test___riscv_vmsleu_vv_u64m2_b32_mu(vbool32_t mask,vbool32_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u64m2_b32_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool16_t test___riscv_vmsleu_vv_u64m4_b16_mu(vbool16_t mask,vbool16_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u64m4_b16_mu(mask,merge,op1,op2,32);
+}
+
+
+vbool8_t test___riscv_vmsleu_vv_u64m8_b8_mu(vbool8_t mask,vbool8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl)
+{
+    return __riscv_vmsleu_vv_u64m8_b8_mu(mask,merge,op1,op2,32);
+}
+
+
+
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
+/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vmsleu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */
-- 
2.36.3