From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtpbgau2.qq.com (smtpbgau2.qq.com [54.206.34.216]) by sourceware.org (Postfix) with ESMTPS id AA053385559E for ; Mon, 13 Feb 2023 08:39:10 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org AA053385559E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp84t1676277545ta52aa0o Received: from rios-cad5.localdomain ( [58.60.1.11]) by bizesmtp.qq.com (ESMTP) with id ; Mon, 13 Feb 2023 16:39:04 +0800 (CST) X-QQ-SSF: 01400000000000E0L000000A0000000 X-QQ-FEAT: jXjag1m6xl6JcSvvMPhs/CZFGtbuyxEgHZp0oDGqj4kchg7G8BfmJjRFbvM9s RViYdlSD6wC2rCFEAN8ehM+5KeRCALHvnkDAwNdgAxtZL1sYfxqyt90LwuoMZGFUR0hOwzK AEtaaIX/DcaqqCwB8Odq3MDKerQBIkGxQaA16TR0TNUUO4jVcF4EGRGNeoTXac/JOcmHz03 Y0pF2TMAyBB6MrNvuAgwL73yNL52XXUWUOXFdVifWGqkf5mtiwti6+fsGretsfga1P909pt ASHNhCls8p+65NKcYp4+zSELLCmUjBI+bAwwLuOkKcBuJbwLz/vTnpU/Hb7Fve5zY4RPaoN SWcIU8MAEhc+3Rk13u2Gf3MQYLjes7QFHt6cEwUqER6+4DsNWsMNJqsWX6F8w== X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: Add vmseq vv C++ tests Date: Mon, 13 Feb 2023 16:39:03 +0800 Message-Id: <20230213083903.293123-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-12.9 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Ju-Zhe Zhong gcc/testsuite/ChangeLog: * g++.target/riscv/rvv/base/vmseq_vv-1.C: New test. * g++.target/riscv/rvv/base/vmseq_vv-2.C: New test. * g++.target/riscv/rvv/base/vmseq_vv-3.C: New test. * g++.target/riscv/rvv/base/vmseq_vv_m-1.C: New test. * g++.target/riscv/rvv/base/vmseq_vv_m-2.C: New test. * g++.target/riscv/rvv/base/vmseq_vv_m-3.C: New test. * g++.target/riscv/rvv/base/vmseq_vv_mu-1.C: New test. * g++.target/riscv/rvv/base/vmseq_vv_mu-2.C: New test. * g++.target/riscv/rvv/base/vmseq_vv_mu-3.C: New test. --- .../g++.target/riscv/rvv/base/vmseq_vv-1.C | 292 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vmseq_vv-2.C | 292 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vmseq_vv-3.C | 292 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vmseq_vv_m-1.C | 292 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vmseq_vv_m-2.C | 292 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vmseq_vv_m-3.C | 292 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vmseq_vv_mu-1.C | 292 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vmseq_vv_mu-2.C | 292 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vmseq_vv_mu-3.C | 292 ++++++++++++++++++ 9 files changed, 2628 insertions(+) create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vv_m-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vv_m-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vv_m-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vv_mu-3.C diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vv-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vv-1.C new file mode 100644 index 00000000000..15115ce5706 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vv-1.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool64_t test___riscv_vmseq(vbool64_t mask,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,vl); +} + + +vbool32_t test___riscv_vmseq(vbool32_t mask,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,vl); +} + + +vbool16_t test___riscv_vmseq(vbool16_t mask,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,vl); +} + + +vbool8_t test___riscv_vmseq(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,vl); +} + + +vbool4_t test___riscv_vmseq(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,vl); +} + + +vbool2_t test___riscv_vmseq(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,vl); +} + + +vbool1_t test___riscv_vmseq(vbool1_t mask,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,vl); +} + + +vbool64_t test___riscv_vmseq(vbool64_t mask,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,vl); +} + + +vbool32_t test___riscv_vmseq(vbool32_t mask,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,vl); +} + + +vbool16_t test___riscv_vmseq(vbool16_t mask,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,vl); +} + + +vbool8_t test___riscv_vmseq(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,vl); +} + + +vbool4_t test___riscv_vmseq(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,vl); +} + + +vbool2_t test___riscv_vmseq(vbool2_t mask,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,vl); +} + + +vbool64_t test___riscv_vmseq(vbool64_t mask,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,vl); +} + + +vbool32_t test___riscv_vmseq(vbool32_t mask,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,vl); +} + + +vbool16_t test___riscv_vmseq(vbool16_t mask,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,vl); +} + + +vbool8_t test___riscv_vmseq(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,vl); +} + + +vbool4_t test___riscv_vmseq(vbool4_t mask,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,vl); +} + + +vbool64_t test___riscv_vmseq(vbool64_t mask,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,vl); +} + + +vbool32_t test___riscv_vmseq(vbool32_t mask,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,vl); +} + + +vbool16_t test___riscv_vmseq(vbool16_t mask,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,vl); +} + + +vbool8_t test___riscv_vmseq(vbool8_t mask,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,vl); +} + + +vbool64_t test___riscv_vmseq(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,vl); +} + + +vbool32_t test___riscv_vmseq(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,vl); +} + + +vbool16_t test___riscv_vmseq(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,vl); +} + + +vbool8_t test___riscv_vmseq(vbool8_t mask,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,vl); +} + + +vbool4_t test___riscv_vmseq(vbool4_t mask,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,vl); +} + + +vbool2_t test___riscv_vmseq(vbool2_t mask,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,vl); +} + + +vbool1_t test___riscv_vmseq(vbool1_t mask,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,vl); +} + + +vbool64_t test___riscv_vmseq(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,vl); +} + + +vbool32_t test___riscv_vmseq(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,vl); +} + + +vbool16_t test___riscv_vmseq(vbool16_t mask,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,vl); +} + + +vbool8_t test___riscv_vmseq(vbool8_t mask,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,vl); +} + + +vbool4_t test___riscv_vmseq(vbool4_t mask,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,vl); +} + + +vbool2_t test___riscv_vmseq(vbool2_t mask,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,vl); +} + + +vbool64_t test___riscv_vmseq(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,vl); +} + + +vbool32_t test___riscv_vmseq(vbool32_t mask,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,vl); +} + + +vbool16_t test___riscv_vmseq(vbool16_t mask,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,vl); +} + + +vbool8_t test___riscv_vmseq(vbool8_t mask,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,vl); +} + + +vbool4_t test___riscv_vmseq(vbool4_t mask,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,vl); +} + + +vbool64_t test___riscv_vmseq(vbool64_t mask,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,vl); +} + + +vbool32_t test___riscv_vmseq(vbool32_t mask,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,vl); +} + + +vbool16_t test___riscv_vmseq(vbool16_t mask,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,vl); +} + + +vbool8_t test___riscv_vmseq(vbool8_t mask,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vv-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vv-2.C new file mode 100644 index 00000000000..5aba84096b2 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vv-2.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool64_t test___riscv_vmseq(vbool64_t mask,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,31); +} + + +vbool32_t test___riscv_vmseq(vbool32_t mask,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,31); +} + + +vbool16_t test___riscv_vmseq(vbool16_t mask,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,31); +} + + +vbool8_t test___riscv_vmseq(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,31); +} + + +vbool4_t test___riscv_vmseq(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,31); +} + + +vbool2_t test___riscv_vmseq(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,31); +} + + +vbool1_t test___riscv_vmseq(vbool1_t mask,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,31); +} + + +vbool64_t test___riscv_vmseq(vbool64_t mask,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,31); +} + + +vbool32_t test___riscv_vmseq(vbool32_t mask,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,31); +} + + +vbool16_t test___riscv_vmseq(vbool16_t mask,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,31); +} + + +vbool8_t test___riscv_vmseq(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,31); +} + + +vbool4_t test___riscv_vmseq(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,31); +} + + +vbool2_t test___riscv_vmseq(vbool2_t mask,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,31); +} + + +vbool64_t test___riscv_vmseq(vbool64_t mask,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,31); +} + + +vbool32_t test___riscv_vmseq(vbool32_t mask,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,31); +} + + +vbool16_t test___riscv_vmseq(vbool16_t mask,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,31); +} + + +vbool8_t test___riscv_vmseq(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,31); +} + + +vbool4_t test___riscv_vmseq(vbool4_t mask,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,31); +} + + +vbool64_t test___riscv_vmseq(vbool64_t mask,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,31); +} + + +vbool32_t test___riscv_vmseq(vbool32_t mask,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,31); +} + + +vbool16_t test___riscv_vmseq(vbool16_t mask,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,31); +} + + +vbool8_t test___riscv_vmseq(vbool8_t mask,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,31); +} + + +vbool64_t test___riscv_vmseq(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,31); +} + + +vbool32_t test___riscv_vmseq(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,31); +} + + +vbool16_t test___riscv_vmseq(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,31); +} + + +vbool8_t test___riscv_vmseq(vbool8_t mask,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,31); +} + + +vbool4_t test___riscv_vmseq(vbool4_t mask,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,31); +} + + +vbool2_t test___riscv_vmseq(vbool2_t mask,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,31); +} + + +vbool1_t test___riscv_vmseq(vbool1_t mask,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,31); +} + + +vbool64_t test___riscv_vmseq(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,31); +} + + +vbool32_t test___riscv_vmseq(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,31); +} + + +vbool16_t test___riscv_vmseq(vbool16_t mask,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,31); +} + + +vbool8_t test___riscv_vmseq(vbool8_t mask,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,31); +} + + +vbool4_t test___riscv_vmseq(vbool4_t mask,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,31); +} + + +vbool2_t test___riscv_vmseq(vbool2_t mask,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,31); +} + + +vbool64_t test___riscv_vmseq(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,31); +} + + +vbool32_t test___riscv_vmseq(vbool32_t mask,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,31); +} + + +vbool16_t test___riscv_vmseq(vbool16_t mask,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,31); +} + + +vbool8_t test___riscv_vmseq(vbool8_t mask,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,31); +} + + +vbool4_t test___riscv_vmseq(vbool4_t mask,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,31); +} + + +vbool64_t test___riscv_vmseq(vbool64_t mask,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,31); +} + + +vbool32_t test___riscv_vmseq(vbool32_t mask,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,31); +} + + +vbool16_t test___riscv_vmseq(vbool16_t mask,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,31); +} + + +vbool8_t test___riscv_vmseq(vbool8_t mask,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vv-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vv-3.C new file mode 100644 index 00000000000..2cb4c3458bc --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vv-3.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool64_t test___riscv_vmseq(vbool64_t mask,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,32); +} + + +vbool32_t test___riscv_vmseq(vbool32_t mask,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,32); +} + + +vbool16_t test___riscv_vmseq(vbool16_t mask,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,32); +} + + +vbool8_t test___riscv_vmseq(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,32); +} + + +vbool4_t test___riscv_vmseq(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,32); +} + + +vbool2_t test___riscv_vmseq(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,32); +} + + +vbool1_t test___riscv_vmseq(vbool1_t mask,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,32); +} + + +vbool64_t test___riscv_vmseq(vbool64_t mask,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,32); +} + + +vbool32_t test___riscv_vmseq(vbool32_t mask,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,32); +} + + +vbool16_t test___riscv_vmseq(vbool16_t mask,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,32); +} + + +vbool8_t test___riscv_vmseq(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,32); +} + + +vbool4_t test___riscv_vmseq(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,32); +} + + +vbool2_t test___riscv_vmseq(vbool2_t mask,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,32); +} + + +vbool64_t test___riscv_vmseq(vbool64_t mask,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,32); +} + + +vbool32_t test___riscv_vmseq(vbool32_t mask,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,32); +} + + +vbool16_t test___riscv_vmseq(vbool16_t mask,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,32); +} + + +vbool8_t test___riscv_vmseq(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,32); +} + + +vbool4_t test___riscv_vmseq(vbool4_t mask,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,32); +} + + +vbool64_t test___riscv_vmseq(vbool64_t mask,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,32); +} + + +vbool32_t test___riscv_vmseq(vbool32_t mask,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,32); +} + + +vbool16_t test___riscv_vmseq(vbool16_t mask,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,32); +} + + +vbool8_t test___riscv_vmseq(vbool8_t mask,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,32); +} + + +vbool64_t test___riscv_vmseq(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,32); +} + + +vbool32_t test___riscv_vmseq(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,32); +} + + +vbool16_t test___riscv_vmseq(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,32); +} + + +vbool8_t test___riscv_vmseq(vbool8_t mask,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,32); +} + + +vbool4_t test___riscv_vmseq(vbool4_t mask,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,32); +} + + +vbool2_t test___riscv_vmseq(vbool2_t mask,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,32); +} + + +vbool1_t test___riscv_vmseq(vbool1_t mask,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,32); +} + + +vbool64_t test___riscv_vmseq(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,32); +} + + +vbool32_t test___riscv_vmseq(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,32); +} + + +vbool16_t test___riscv_vmseq(vbool16_t mask,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,32); +} + + +vbool8_t test___riscv_vmseq(vbool8_t mask,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,32); +} + + +vbool4_t test___riscv_vmseq(vbool4_t mask,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,32); +} + + +vbool2_t test___riscv_vmseq(vbool2_t mask,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,32); +} + + +vbool64_t test___riscv_vmseq(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,32); +} + + +vbool32_t test___riscv_vmseq(vbool32_t mask,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,32); +} + + +vbool16_t test___riscv_vmseq(vbool16_t mask,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,32); +} + + +vbool8_t test___riscv_vmseq(vbool8_t mask,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,32); +} + + +vbool4_t test___riscv_vmseq(vbool4_t mask,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,32); +} + + +vbool64_t test___riscv_vmseq(vbool64_t mask,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,32); +} + + +vbool32_t test___riscv_vmseq(vbool32_t mask,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,32); +} + + +vbool16_t test___riscv_vmseq(vbool16_t mask,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,32); +} + + +vbool8_t test___riscv_vmseq(vbool8_t mask,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vmseq(op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vv_m-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vv_m-1.C new file mode 100644 index 00000000000..8aa2e79481e --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vv_m-1.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool64_t test___riscv_vmseq(vbool64_t mask,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,vl); +} + + +vbool32_t test___riscv_vmseq(vbool32_t mask,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,vl); +} + + +vbool16_t test___riscv_vmseq(vbool16_t mask,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,vl); +} + + +vbool8_t test___riscv_vmseq(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,vl); +} + + +vbool4_t test___riscv_vmseq(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,vl); +} + + +vbool2_t test___riscv_vmseq(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,vl); +} + + +vbool1_t test___riscv_vmseq(vbool1_t mask,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,vl); +} + + +vbool64_t test___riscv_vmseq(vbool64_t mask,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,vl); +} + + +vbool32_t test___riscv_vmseq(vbool32_t mask,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,vl); +} + + +vbool16_t test___riscv_vmseq(vbool16_t mask,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,vl); +} + + +vbool8_t test___riscv_vmseq(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,vl); +} + + +vbool4_t test___riscv_vmseq(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,vl); +} + + +vbool2_t test___riscv_vmseq(vbool2_t mask,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,vl); +} + + +vbool64_t test___riscv_vmseq(vbool64_t mask,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,vl); +} + + +vbool32_t test___riscv_vmseq(vbool32_t mask,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,vl); +} + + +vbool16_t test___riscv_vmseq(vbool16_t mask,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,vl); +} + + +vbool8_t test___riscv_vmseq(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,vl); +} + + +vbool4_t test___riscv_vmseq(vbool4_t mask,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,vl); +} + + +vbool64_t test___riscv_vmseq(vbool64_t mask,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,vl); +} + + +vbool32_t test___riscv_vmseq(vbool32_t mask,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,vl); +} + + +vbool16_t test___riscv_vmseq(vbool16_t mask,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,vl); +} + + +vbool8_t test___riscv_vmseq(vbool8_t mask,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,vl); +} + + +vbool64_t test___riscv_vmseq(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,vl); +} + + +vbool32_t test___riscv_vmseq(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,vl); +} + + +vbool16_t test___riscv_vmseq(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,vl); +} + + +vbool8_t test___riscv_vmseq(vbool8_t mask,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,vl); +} + + +vbool4_t test___riscv_vmseq(vbool4_t mask,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,vl); +} + + +vbool2_t test___riscv_vmseq(vbool2_t mask,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,vl); +} + + +vbool1_t test___riscv_vmseq(vbool1_t mask,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,vl); +} + + +vbool64_t test___riscv_vmseq(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,vl); +} + + +vbool32_t test___riscv_vmseq(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,vl); +} + + +vbool16_t test___riscv_vmseq(vbool16_t mask,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,vl); +} + + +vbool8_t test___riscv_vmseq(vbool8_t mask,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,vl); +} + + +vbool4_t test___riscv_vmseq(vbool4_t mask,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,vl); +} + + +vbool2_t test___riscv_vmseq(vbool2_t mask,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,vl); +} + + +vbool64_t test___riscv_vmseq(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,vl); +} + + +vbool32_t test___riscv_vmseq(vbool32_t mask,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,vl); +} + + +vbool16_t test___riscv_vmseq(vbool16_t mask,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,vl); +} + + +vbool8_t test___riscv_vmseq(vbool8_t mask,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,vl); +} + + +vbool4_t test___riscv_vmseq(vbool4_t mask,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,vl); +} + + +vbool64_t test___riscv_vmseq(vbool64_t mask,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,vl); +} + + +vbool32_t test___riscv_vmseq(vbool32_t mask,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,vl); +} + + +vbool16_t test___riscv_vmseq(vbool16_t mask,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,vl); +} + + +vbool8_t test___riscv_vmseq(vbool8_t mask,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vv_m-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vv_m-2.C new file mode 100644 index 00000000000..bbc1b7b3a06 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vv_m-2.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool64_t test___riscv_vmseq(vbool64_t mask,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,31); +} + + +vbool32_t test___riscv_vmseq(vbool32_t mask,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,31); +} + + +vbool16_t test___riscv_vmseq(vbool16_t mask,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,31); +} + + +vbool8_t test___riscv_vmseq(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,31); +} + + +vbool4_t test___riscv_vmseq(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,31); +} + + +vbool2_t test___riscv_vmseq(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,31); +} + + +vbool1_t test___riscv_vmseq(vbool1_t mask,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,31); +} + + +vbool64_t test___riscv_vmseq(vbool64_t mask,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,31); +} + + +vbool32_t test___riscv_vmseq(vbool32_t mask,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,31); +} + + +vbool16_t test___riscv_vmseq(vbool16_t mask,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,31); +} + + +vbool8_t test___riscv_vmseq(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,31); +} + + +vbool4_t test___riscv_vmseq(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,31); +} + + +vbool2_t test___riscv_vmseq(vbool2_t mask,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,31); +} + + +vbool64_t test___riscv_vmseq(vbool64_t mask,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,31); +} + + +vbool32_t test___riscv_vmseq(vbool32_t mask,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,31); +} + + +vbool16_t test___riscv_vmseq(vbool16_t mask,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,31); +} + + +vbool8_t test___riscv_vmseq(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,31); +} + + +vbool4_t test___riscv_vmseq(vbool4_t mask,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,31); +} + + +vbool64_t test___riscv_vmseq(vbool64_t mask,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,31); +} + + +vbool32_t test___riscv_vmseq(vbool32_t mask,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,31); +} + + +vbool16_t test___riscv_vmseq(vbool16_t mask,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,31); +} + + +vbool8_t test___riscv_vmseq(vbool8_t mask,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,31); +} + + +vbool64_t test___riscv_vmseq(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,31); +} + + +vbool32_t test___riscv_vmseq(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,31); +} + + +vbool16_t test___riscv_vmseq(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,31); +} + + +vbool8_t test___riscv_vmseq(vbool8_t mask,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,31); +} + + +vbool4_t test___riscv_vmseq(vbool4_t mask,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,31); +} + + +vbool2_t test___riscv_vmseq(vbool2_t mask,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,31); +} + + +vbool1_t test___riscv_vmseq(vbool1_t mask,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,31); +} + + +vbool64_t test___riscv_vmseq(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,31); +} + + +vbool32_t test___riscv_vmseq(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,31); +} + + +vbool16_t test___riscv_vmseq(vbool16_t mask,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,31); +} + + +vbool8_t test___riscv_vmseq(vbool8_t mask,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,31); +} + + +vbool4_t test___riscv_vmseq(vbool4_t mask,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,31); +} + + +vbool2_t test___riscv_vmseq(vbool2_t mask,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,31); +} + + +vbool64_t test___riscv_vmseq(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,31); +} + + +vbool32_t test___riscv_vmseq(vbool32_t mask,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,31); +} + + +vbool16_t test___riscv_vmseq(vbool16_t mask,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,31); +} + + +vbool8_t test___riscv_vmseq(vbool8_t mask,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,31); +} + + +vbool4_t test___riscv_vmseq(vbool4_t mask,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,31); +} + + +vbool64_t test___riscv_vmseq(vbool64_t mask,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,31); +} + + +vbool32_t test___riscv_vmseq(vbool32_t mask,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,31); +} + + +vbool16_t test___riscv_vmseq(vbool16_t mask,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,31); +} + + +vbool8_t test___riscv_vmseq(vbool8_t mask,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vv_m-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vv_m-3.C new file mode 100644 index 00000000000..0401358a3cf --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vv_m-3.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool64_t test___riscv_vmseq(vbool64_t mask,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,32); +} + + +vbool32_t test___riscv_vmseq(vbool32_t mask,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,32); +} + + +vbool16_t test___riscv_vmseq(vbool16_t mask,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,32); +} + + +vbool8_t test___riscv_vmseq(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,32); +} + + +vbool4_t test___riscv_vmseq(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,32); +} + + +vbool2_t test___riscv_vmseq(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,32); +} + + +vbool1_t test___riscv_vmseq(vbool1_t mask,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,32); +} + + +vbool64_t test___riscv_vmseq(vbool64_t mask,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,32); +} + + +vbool32_t test___riscv_vmseq(vbool32_t mask,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,32); +} + + +vbool16_t test___riscv_vmseq(vbool16_t mask,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,32); +} + + +vbool8_t test___riscv_vmseq(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,32); +} + + +vbool4_t test___riscv_vmseq(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,32); +} + + +vbool2_t test___riscv_vmseq(vbool2_t mask,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,32); +} + + +vbool64_t test___riscv_vmseq(vbool64_t mask,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,32); +} + + +vbool32_t test___riscv_vmseq(vbool32_t mask,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,32); +} + + +vbool16_t test___riscv_vmseq(vbool16_t mask,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,32); +} + + +vbool8_t test___riscv_vmseq(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,32); +} + + +vbool4_t test___riscv_vmseq(vbool4_t mask,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,32); +} + + +vbool64_t test___riscv_vmseq(vbool64_t mask,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,32); +} + + +vbool32_t test___riscv_vmseq(vbool32_t mask,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,32); +} + + +vbool16_t test___riscv_vmseq(vbool16_t mask,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,32); +} + + +vbool8_t test___riscv_vmseq(vbool8_t mask,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,32); +} + + +vbool64_t test___riscv_vmseq(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,32); +} + + +vbool32_t test___riscv_vmseq(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,32); +} + + +vbool16_t test___riscv_vmseq(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,32); +} + + +vbool8_t test___riscv_vmseq(vbool8_t mask,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,32); +} + + +vbool4_t test___riscv_vmseq(vbool4_t mask,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,32); +} + + +vbool2_t test___riscv_vmseq(vbool2_t mask,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,32); +} + + +vbool1_t test___riscv_vmseq(vbool1_t mask,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,32); +} + + +vbool64_t test___riscv_vmseq(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,32); +} + + +vbool32_t test___riscv_vmseq(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,32); +} + + +vbool16_t test___riscv_vmseq(vbool16_t mask,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,32); +} + + +vbool8_t test___riscv_vmseq(vbool8_t mask,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,32); +} + + +vbool4_t test___riscv_vmseq(vbool4_t mask,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,32); +} + + +vbool2_t test___riscv_vmseq(vbool2_t mask,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,32); +} + + +vbool64_t test___riscv_vmseq(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,32); +} + + +vbool32_t test___riscv_vmseq(vbool32_t mask,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,32); +} + + +vbool16_t test___riscv_vmseq(vbool16_t mask,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,32); +} + + +vbool8_t test___riscv_vmseq(vbool8_t mask,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,32); +} + + +vbool4_t test___riscv_vmseq(vbool4_t mask,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,32); +} + + +vbool64_t test___riscv_vmseq(vbool64_t mask,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,32); +} + + +vbool32_t test___riscv_vmseq(vbool32_t mask,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,32); +} + + +vbool16_t test___riscv_vmseq(vbool16_t mask,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,32); +} + + +vbool8_t test___riscv_vmseq(vbool8_t mask,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vmseq(mask,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vv_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vv_mu-1.C new file mode 100644 index 00000000000..b4604e72c8a --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vv_mu-1.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool64_t test___riscv_vmseq_mu(vbool64_t mask,vbool64_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,vl); +} + + +vbool32_t test___riscv_vmseq_mu(vbool32_t mask,vbool32_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,vl); +} + + +vbool16_t test___riscv_vmseq_mu(vbool16_t mask,vbool16_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,vl); +} + + +vbool8_t test___riscv_vmseq_mu(vbool8_t mask,vbool8_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,vl); +} + + +vbool4_t test___riscv_vmseq_mu(vbool4_t mask,vbool4_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,vl); +} + + +vbool2_t test___riscv_vmseq_mu(vbool2_t mask,vbool2_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,vl); +} + + +vbool1_t test___riscv_vmseq_mu(vbool1_t mask,vbool1_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,vl); +} + + +vbool64_t test___riscv_vmseq_mu(vbool64_t mask,vbool64_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,vl); +} + + +vbool32_t test___riscv_vmseq_mu(vbool32_t mask,vbool32_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,vl); +} + + +vbool16_t test___riscv_vmseq_mu(vbool16_t mask,vbool16_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,vl); +} + + +vbool8_t test___riscv_vmseq_mu(vbool8_t mask,vbool8_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,vl); +} + + +vbool4_t test___riscv_vmseq_mu(vbool4_t mask,vbool4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,vl); +} + + +vbool2_t test___riscv_vmseq_mu(vbool2_t mask,vbool2_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,vl); +} + + +vbool64_t test___riscv_vmseq_mu(vbool64_t mask,vbool64_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,vl); +} + + +vbool32_t test___riscv_vmseq_mu(vbool32_t mask,vbool32_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,vl); +} + + +vbool16_t test___riscv_vmseq_mu(vbool16_t mask,vbool16_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,vl); +} + + +vbool8_t test___riscv_vmseq_mu(vbool8_t mask,vbool8_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,vl); +} + + +vbool4_t test___riscv_vmseq_mu(vbool4_t mask,vbool4_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,vl); +} + + +vbool64_t test___riscv_vmseq_mu(vbool64_t mask,vbool64_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,vl); +} + + +vbool32_t test___riscv_vmseq_mu(vbool32_t mask,vbool32_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,vl); +} + + +vbool16_t test___riscv_vmseq_mu(vbool16_t mask,vbool16_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,vl); +} + + +vbool8_t test___riscv_vmseq_mu(vbool8_t mask,vbool8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,vl); +} + + +vbool64_t test___riscv_vmseq_mu(vbool64_t mask,vbool64_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,vl); +} + + +vbool32_t test___riscv_vmseq_mu(vbool32_t mask,vbool32_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,vl); +} + + +vbool16_t test___riscv_vmseq_mu(vbool16_t mask,vbool16_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,vl); +} + + +vbool8_t test___riscv_vmseq_mu(vbool8_t mask,vbool8_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,vl); +} + + +vbool4_t test___riscv_vmseq_mu(vbool4_t mask,vbool4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,vl); +} + + +vbool2_t test___riscv_vmseq_mu(vbool2_t mask,vbool2_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,vl); +} + + +vbool1_t test___riscv_vmseq_mu(vbool1_t mask,vbool1_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,vl); +} + + +vbool64_t test___riscv_vmseq_mu(vbool64_t mask,vbool64_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,vl); +} + + +vbool32_t test___riscv_vmseq_mu(vbool32_t mask,vbool32_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,vl); +} + + +vbool16_t test___riscv_vmseq_mu(vbool16_t mask,vbool16_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,vl); +} + + +vbool8_t test___riscv_vmseq_mu(vbool8_t mask,vbool8_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,vl); +} + + +vbool4_t test___riscv_vmseq_mu(vbool4_t mask,vbool4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,vl); +} + + +vbool2_t test___riscv_vmseq_mu(vbool2_t mask,vbool2_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,vl); +} + + +vbool64_t test___riscv_vmseq_mu(vbool64_t mask,vbool64_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,vl); +} + + +vbool32_t test___riscv_vmseq_mu(vbool32_t mask,vbool32_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,vl); +} + + +vbool16_t test___riscv_vmseq_mu(vbool16_t mask,vbool16_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,vl); +} + + +vbool8_t test___riscv_vmseq_mu(vbool8_t mask,vbool8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,vl); +} + + +vbool4_t test___riscv_vmseq_mu(vbool4_t mask,vbool4_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,vl); +} + + +vbool64_t test___riscv_vmseq_mu(vbool64_t mask,vbool64_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,vl); +} + + +vbool32_t test___riscv_vmseq_mu(vbool32_t mask,vbool32_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,vl); +} + + +vbool16_t test___riscv_vmseq_mu(vbool16_t mask,vbool16_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,vl); +} + + +vbool8_t test___riscv_vmseq_mu(vbool8_t mask,vbool8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vv_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vv_mu-2.C new file mode 100644 index 00000000000..ba7bb9d74a3 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vv_mu-2.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool64_t test___riscv_vmseq_mu(vbool64_t mask,vbool64_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,31); +} + + +vbool32_t test___riscv_vmseq_mu(vbool32_t mask,vbool32_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,31); +} + + +vbool16_t test___riscv_vmseq_mu(vbool16_t mask,vbool16_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,31); +} + + +vbool8_t test___riscv_vmseq_mu(vbool8_t mask,vbool8_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,31); +} + + +vbool4_t test___riscv_vmseq_mu(vbool4_t mask,vbool4_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,31); +} + + +vbool2_t test___riscv_vmseq_mu(vbool2_t mask,vbool2_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,31); +} + + +vbool1_t test___riscv_vmseq_mu(vbool1_t mask,vbool1_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,31); +} + + +vbool64_t test___riscv_vmseq_mu(vbool64_t mask,vbool64_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,31); +} + + +vbool32_t test___riscv_vmseq_mu(vbool32_t mask,vbool32_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,31); +} + + +vbool16_t test___riscv_vmseq_mu(vbool16_t mask,vbool16_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,31); +} + + +vbool8_t test___riscv_vmseq_mu(vbool8_t mask,vbool8_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,31); +} + + +vbool4_t test___riscv_vmseq_mu(vbool4_t mask,vbool4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,31); +} + + +vbool2_t test___riscv_vmseq_mu(vbool2_t mask,vbool2_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,31); +} + + +vbool64_t test___riscv_vmseq_mu(vbool64_t mask,vbool64_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,31); +} + + +vbool32_t test___riscv_vmseq_mu(vbool32_t mask,vbool32_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,31); +} + + +vbool16_t test___riscv_vmseq_mu(vbool16_t mask,vbool16_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,31); +} + + +vbool8_t test___riscv_vmseq_mu(vbool8_t mask,vbool8_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,31); +} + + +vbool4_t test___riscv_vmseq_mu(vbool4_t mask,vbool4_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,31); +} + + +vbool64_t test___riscv_vmseq_mu(vbool64_t mask,vbool64_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,31); +} + + +vbool32_t test___riscv_vmseq_mu(vbool32_t mask,vbool32_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,31); +} + + +vbool16_t test___riscv_vmseq_mu(vbool16_t mask,vbool16_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,31); +} + + +vbool8_t test___riscv_vmseq_mu(vbool8_t mask,vbool8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,31); +} + + +vbool64_t test___riscv_vmseq_mu(vbool64_t mask,vbool64_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,31); +} + + +vbool32_t test___riscv_vmseq_mu(vbool32_t mask,vbool32_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,31); +} + + +vbool16_t test___riscv_vmseq_mu(vbool16_t mask,vbool16_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,31); +} + + +vbool8_t test___riscv_vmseq_mu(vbool8_t mask,vbool8_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,31); +} + + +vbool4_t test___riscv_vmseq_mu(vbool4_t mask,vbool4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,31); +} + + +vbool2_t test___riscv_vmseq_mu(vbool2_t mask,vbool2_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,31); +} + + +vbool1_t test___riscv_vmseq_mu(vbool1_t mask,vbool1_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,31); +} + + +vbool64_t test___riscv_vmseq_mu(vbool64_t mask,vbool64_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,31); +} + + +vbool32_t test___riscv_vmseq_mu(vbool32_t mask,vbool32_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,31); +} + + +vbool16_t test___riscv_vmseq_mu(vbool16_t mask,vbool16_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,31); +} + + +vbool8_t test___riscv_vmseq_mu(vbool8_t mask,vbool8_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,31); +} + + +vbool4_t test___riscv_vmseq_mu(vbool4_t mask,vbool4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,31); +} + + +vbool2_t test___riscv_vmseq_mu(vbool2_t mask,vbool2_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,31); +} + + +vbool64_t test___riscv_vmseq_mu(vbool64_t mask,vbool64_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,31); +} + + +vbool32_t test___riscv_vmseq_mu(vbool32_t mask,vbool32_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,31); +} + + +vbool16_t test___riscv_vmseq_mu(vbool16_t mask,vbool16_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,31); +} + + +vbool8_t test___riscv_vmseq_mu(vbool8_t mask,vbool8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,31); +} + + +vbool4_t test___riscv_vmseq_mu(vbool4_t mask,vbool4_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,31); +} + + +vbool64_t test___riscv_vmseq_mu(vbool64_t mask,vbool64_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,31); +} + + +vbool32_t test___riscv_vmseq_mu(vbool32_t mask,vbool32_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,31); +} + + +vbool16_t test___riscv_vmseq_mu(vbool16_t mask,vbool16_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,31); +} + + +vbool8_t test___riscv_vmseq_mu(vbool8_t mask,vbool8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vv_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vv_mu-3.C new file mode 100644 index 00000000000..1eead95e21e --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vv_mu-3.C @@ -0,0 +1,292 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool64_t test___riscv_vmseq_mu(vbool64_t mask,vbool64_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,32); +} + + +vbool32_t test___riscv_vmseq_mu(vbool32_t mask,vbool32_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,32); +} + + +vbool16_t test___riscv_vmseq_mu(vbool16_t mask,vbool16_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,32); +} + + +vbool8_t test___riscv_vmseq_mu(vbool8_t mask,vbool8_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,32); +} + + +vbool4_t test___riscv_vmseq_mu(vbool4_t mask,vbool4_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,32); +} + + +vbool2_t test___riscv_vmseq_mu(vbool2_t mask,vbool2_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,32); +} + + +vbool1_t test___riscv_vmseq_mu(vbool1_t mask,vbool1_t merge,vint8m8_t op1,vint8m8_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,32); +} + + +vbool64_t test___riscv_vmseq_mu(vbool64_t mask,vbool64_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,32); +} + + +vbool32_t test___riscv_vmseq_mu(vbool32_t mask,vbool32_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,32); +} + + +vbool16_t test___riscv_vmseq_mu(vbool16_t mask,vbool16_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,32); +} + + +vbool8_t test___riscv_vmseq_mu(vbool8_t mask,vbool8_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,32); +} + + +vbool4_t test___riscv_vmseq_mu(vbool4_t mask,vbool4_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,32); +} + + +vbool2_t test___riscv_vmseq_mu(vbool2_t mask,vbool2_t merge,vint16m8_t op1,vint16m8_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,32); +} + + +vbool64_t test___riscv_vmseq_mu(vbool64_t mask,vbool64_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,32); +} + + +vbool32_t test___riscv_vmseq_mu(vbool32_t mask,vbool32_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,32); +} + + +vbool16_t test___riscv_vmseq_mu(vbool16_t mask,vbool16_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,32); +} + + +vbool8_t test___riscv_vmseq_mu(vbool8_t mask,vbool8_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,32); +} + + +vbool4_t test___riscv_vmseq_mu(vbool4_t mask,vbool4_t merge,vint32m8_t op1,vint32m8_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,32); +} + + +vbool64_t test___riscv_vmseq_mu(vbool64_t mask,vbool64_t merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,32); +} + + +vbool32_t test___riscv_vmseq_mu(vbool32_t mask,vbool32_t merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,32); +} + + +vbool16_t test___riscv_vmseq_mu(vbool16_t mask,vbool16_t merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,32); +} + + +vbool8_t test___riscv_vmseq_mu(vbool8_t mask,vbool8_t merge,vint64m8_t op1,vint64m8_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,32); +} + + +vbool64_t test___riscv_vmseq_mu(vbool64_t mask,vbool64_t merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,32); +} + + +vbool32_t test___riscv_vmseq_mu(vbool32_t mask,vbool32_t merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,32); +} + + +vbool16_t test___riscv_vmseq_mu(vbool16_t mask,vbool16_t merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,32); +} + + +vbool8_t test___riscv_vmseq_mu(vbool8_t mask,vbool8_t merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,32); +} + + +vbool4_t test___riscv_vmseq_mu(vbool4_t mask,vbool4_t merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,32); +} + + +vbool2_t test___riscv_vmseq_mu(vbool2_t mask,vbool2_t merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,32); +} + + +vbool1_t test___riscv_vmseq_mu(vbool1_t mask,vbool1_t merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,32); +} + + +vbool64_t test___riscv_vmseq_mu(vbool64_t mask,vbool64_t merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,32); +} + + +vbool32_t test___riscv_vmseq_mu(vbool32_t mask,vbool32_t merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,32); +} + + +vbool16_t test___riscv_vmseq_mu(vbool16_t mask,vbool16_t merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,32); +} + + +vbool8_t test___riscv_vmseq_mu(vbool8_t mask,vbool8_t merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,32); +} + + +vbool4_t test___riscv_vmseq_mu(vbool4_t mask,vbool4_t merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,32); +} + + +vbool2_t test___riscv_vmseq_mu(vbool2_t mask,vbool2_t merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,32); +} + + +vbool64_t test___riscv_vmseq_mu(vbool64_t mask,vbool64_t merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,32); +} + + +vbool32_t test___riscv_vmseq_mu(vbool32_t mask,vbool32_t merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,32); +} + + +vbool16_t test___riscv_vmseq_mu(vbool16_t mask,vbool16_t merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,32); +} + + +vbool8_t test___riscv_vmseq_mu(vbool8_t mask,vbool8_t merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,32); +} + + +vbool4_t test___riscv_vmseq_mu(vbool4_t mask,vbool4_t merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,32); +} + + +vbool64_t test___riscv_vmseq_mu(vbool64_t mask,vbool64_t merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,32); +} + + +vbool32_t test___riscv_vmseq_mu(vbool32_t mask,vbool32_t merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,32); +} + + +vbool16_t test___riscv_vmseq_mu(vbool16_t mask,vbool16_t merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,32); +} + + +vbool8_t test___riscv_vmseq_mu(vbool8_t mask,vbool8_t merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{ + return __riscv_vmseq_mu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vmseq\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 2 } } */ -- 2.36.3