From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtpbguseast2.qq.com (smtpbguseast2.qq.com [54.204.34.130]) by sourceware.org (Postfix) with ESMTPS id B7BFD3858412 for ; Tue, 14 Feb 2023 14:14:54 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org B7BFD3858412 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp65t1676384074tawpq610 Received: from rios-cad5.localdomain ( [58.60.1.11]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 14 Feb 2023 22:14:33 +0800 (CST) X-QQ-SSF: 01400000002000E0L000B00A0000000 X-QQ-FEAT: CR3LFp2JE4kMPHApyUqUTDTG7n/hATRdEgqhzWfb47n6oW9WyaLtSTWvV9yTf ceIx4gzOHka+bkT1h52y3a+RnudJ6mmwIG2QnBQphmC9KRRS/bU1+91jSZdHi6EFm4WWXTE IqEEKn+tFGkvaxnOhHGaXSipcOxPPEM9dcEgTKA/uxUaZu/Fws+ZEMbY7jw0uYF6TizdR8s meU+xsEaoH/9cl9JNsI9WNyNc3utd5hcfSsoqVekSp0TDRBMoN+CcfxcgA5g3I9ETHyScbk VL7HN9hg74wrQk4CpC+zC65xd4ekU+6smEujFKgC4Bbjdv2IdR/xezrZM3VRCqa7W3lWQPo UyRgD6uVdtzcgOCnXHFJ4WvOczOZUzjQMFxNjZibFFKAxtOuV4KABoe8SBPGbyjSgdUOdlZ X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: Add vwmacc vv C++ api tests Date: Tue, 14 Feb 2023 22:14:23 +0800 Message-Id: <20230214141423.151090-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-12.9 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Ju-Zhe Zhong gcc/testsuite/ChangeLog: * g++.target/riscv/rvv/base/vwmacc_vv-1.C: New test. * g++.target/riscv/rvv/base/vwmacc_vv-2.C: New test. * g++.target/riscv/rvv/base/vwmacc_vv-3.C: New test. * g++.target/riscv/rvv/base/vwmacc_vv_mu-1.C: New test. * g++.target/riscv/rvv/base/vwmacc_vv_mu-2.C: New test. * g++.target/riscv/rvv/base/vwmacc_vv_mu-3.C: New test. * g++.target/riscv/rvv/base/vwmacc_vv_tu-1.C: New test. * g++.target/riscv/rvv/base/vwmacc_vv_tu-2.C: New test. * g++.target/riscv/rvv/base/vwmacc_vv_tu-3.C: New test. * g++.target/riscv/rvv/base/vwmacc_vv_tum-1.C: New test. * g++.target/riscv/rvv/base/vwmacc_vv_tum-2.C: New test. * g++.target/riscv/rvv/base/vwmacc_vv_tum-3.C: New test. * g++.target/riscv/rvv/base/vwmacc_vv_tumu-1.C: New test. * g++.target/riscv/rvv/base/vwmacc_vv_tumu-2.C: New test. * g++.target/riscv/rvv/base/vwmacc_vv_tumu-3.C: New test. * g++.target/riscv/rvv/base/vwmaccsu_vv-1.C: New test. * g++.target/riscv/rvv/base/vwmaccsu_vv-2.C: New test. * g++.target/riscv/rvv/base/vwmaccsu_vv-3.C: New test. * g++.target/riscv/rvv/base/vwmaccsu_vv_mu-1.C: New test. * g++.target/riscv/rvv/base/vwmaccsu_vv_mu-2.C: New test. * g++.target/riscv/rvv/base/vwmaccsu_vv_mu-3.C: New test. * g++.target/riscv/rvv/base/vwmaccsu_vv_tu-1.C: New test. * g++.target/riscv/rvv/base/vwmaccsu_vv_tu-2.C: New test. * g++.target/riscv/rvv/base/vwmaccsu_vv_tu-3.C: New test. * g++.target/riscv/rvv/base/vwmaccsu_vv_tum-1.C: New test. * g++.target/riscv/rvv/base/vwmaccsu_vv_tum-2.C: New test. * g++.target/riscv/rvv/base/vwmaccsu_vv_tum-3.C: New test. * g++.target/riscv/rvv/base/vwmaccsu_vv_tumu-1.C: New test. * g++.target/riscv/rvv/base/vwmaccsu_vv_tumu-2.C: New test. * g++.target/riscv/rvv/base/vwmaccsu_vv_tumu-3.C: New test. * g++.target/riscv/rvv/base/vwmaccu_vv-1.C: New test. * g++.target/riscv/rvv/base/vwmaccu_vv-2.C: New test. * g++.target/riscv/rvv/base/vwmaccu_vv-3.C: New test. * g++.target/riscv/rvv/base/vwmaccu_vv_mu-1.C: New test. * g++.target/riscv/rvv/base/vwmaccu_vv_mu-2.C: New test. * g++.target/riscv/rvv/base/vwmaccu_vv_mu-3.C: New test. * g++.target/riscv/rvv/base/vwmaccu_vv_tu-1.C: New test. * g++.target/riscv/rvv/base/vwmaccu_vv_tu-2.C: New test. * g++.target/riscv/rvv/base/vwmaccu_vv_tu-3.C: New test. * g++.target/riscv/rvv/base/vwmaccu_vv_tum-1.C: New test. * g++.target/riscv/rvv/base/vwmaccu_vv_tum-2.C: New test. * g++.target/riscv/rvv/base/vwmaccu_vv_tum-3.C: New test. * g++.target/riscv/rvv/base/vwmaccu_vv_tumu-1.C: New test. * g++.target/riscv/rvv/base/vwmaccu_vv_tumu-2.C: New test. * g++.target/riscv/rvv/base/vwmaccu_vv_tumu-3.C: New test. --- .../g++.target/riscv/rvv/base/vwmacc_vv-1.C | 216 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vwmacc_vv-2.C | 216 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vwmacc_vv-3.C | 216 ++++++++++++++++++ .../riscv/rvv/base/vwmacc_vv_mu-1.C | 111 +++++++++ .../riscv/rvv/base/vwmacc_vv_mu-2.C | 111 +++++++++ .../riscv/rvv/base/vwmacc_vv_mu-3.C | 111 +++++++++ .../riscv/rvv/base/vwmacc_vv_tu-1.C | 111 +++++++++ .../riscv/rvv/base/vwmacc_vv_tu-2.C | 111 +++++++++ .../riscv/rvv/base/vwmacc_vv_tu-3.C | 111 +++++++++ .../riscv/rvv/base/vwmacc_vv_tum-1.C | 111 +++++++++ .../riscv/rvv/base/vwmacc_vv_tum-2.C | 111 +++++++++ .../riscv/rvv/base/vwmacc_vv_tum-3.C | 111 +++++++++ .../riscv/rvv/base/vwmacc_vv_tumu-1.C | 111 +++++++++ .../riscv/rvv/base/vwmacc_vv_tumu-2.C | 111 +++++++++ .../riscv/rvv/base/vwmacc_vv_tumu-3.C | 111 +++++++++ .../g++.target/riscv/rvv/base/vwmaccsu_vv-1.C | 216 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vwmaccsu_vv-2.C | 216 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vwmaccsu_vv-3.C | 216 ++++++++++++++++++ .../riscv/rvv/base/vwmaccsu_vv_mu-1.C | 111 +++++++++ .../riscv/rvv/base/vwmaccsu_vv_mu-2.C | 111 +++++++++ .../riscv/rvv/base/vwmaccsu_vv_mu-3.C | 111 +++++++++ .../riscv/rvv/base/vwmaccsu_vv_tu-1.C | 111 +++++++++ .../riscv/rvv/base/vwmaccsu_vv_tu-2.C | 111 +++++++++ .../riscv/rvv/base/vwmaccsu_vv_tu-3.C | 111 +++++++++ .../riscv/rvv/base/vwmaccsu_vv_tum-1.C | 111 +++++++++ .../riscv/rvv/base/vwmaccsu_vv_tum-2.C | 111 +++++++++ .../riscv/rvv/base/vwmaccsu_vv_tum-3.C | 111 +++++++++ .../riscv/rvv/base/vwmaccsu_vv_tumu-1.C | 111 +++++++++ .../riscv/rvv/base/vwmaccsu_vv_tumu-2.C | 111 +++++++++ .../riscv/rvv/base/vwmaccsu_vv_tumu-3.C | 111 +++++++++ .../g++.target/riscv/rvv/base/vwmaccu_vv-1.C | 216 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vwmaccu_vv-2.C | 216 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vwmaccu_vv-3.C | 216 ++++++++++++++++++ .../riscv/rvv/base/vwmaccu_vv_mu-1.C | 111 +++++++++ .../riscv/rvv/base/vwmaccu_vv_mu-2.C | 111 +++++++++ .../riscv/rvv/base/vwmaccu_vv_mu-3.C | 111 +++++++++ .../riscv/rvv/base/vwmaccu_vv_tu-1.C | 111 +++++++++ .../riscv/rvv/base/vwmaccu_vv_tu-2.C | 111 +++++++++ .../riscv/rvv/base/vwmaccu_vv_tu-3.C | 111 +++++++++ .../riscv/rvv/base/vwmaccu_vv_tum-1.C | 111 +++++++++ .../riscv/rvv/base/vwmaccu_vv_tum-2.C | 111 +++++++++ .../riscv/rvv/base/vwmaccu_vv_tum-3.C | 111 +++++++++ .../riscv/rvv/base/vwmaccu_vv_tumu-1.C | 111 +++++++++ .../riscv/rvv/base/vwmaccu_vv_tumu-2.C | 111 +++++++++ .../riscv/rvv/base/vwmaccu_vv_tumu-3.C | 111 +++++++++ 45 files changed, 5940 insertions(+) create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tumu-3.C diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv-1.C new file mode 100644 index 00000000000..481fe63f074 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv-1.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmacc(vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmacc(vd,vs1,vs2,vl); +} + + +vint16mf2_t test___riscv_vwmacc(vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc(vd,vs1,vs2,vl); +} + + +vint16m1_t test___riscv_vwmacc(vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc(vd,vs1,vs2,vl); +} + + +vint16m2_t test___riscv_vwmacc(vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vwmacc(vd,vs1,vs2,vl); +} + + +vint16m4_t test___riscv_vwmacc(vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vwmacc(vd,vs1,vs2,vl); +} + + +vint16m8_t test___riscv_vwmacc(vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vwmacc(vd,vs1,vs2,vl); +} + + +vint32mf2_t test___riscv_vwmacc(vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc(vd,vs1,vs2,vl); +} + + +vint32m1_t test___riscv_vwmacc(vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc(vd,vs1,vs2,vl); +} + + +vint32m2_t test___riscv_vwmacc(vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vwmacc(vd,vs1,vs2,vl); +} + + +vint32m4_t test___riscv_vwmacc(vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vwmacc(vd,vs1,vs2,vl); +} + + +vint32m8_t test___riscv_vwmacc(vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vwmacc(vd,vs1,vs2,vl); +} + + +vint64m1_t test___riscv_vwmacc(vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc(vd,vs1,vs2,vl); +} + + +vint64m2_t test___riscv_vwmacc(vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vwmacc(vd,vs1,vs2,vl); +} + + +vint64m4_t test___riscv_vwmacc(vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vwmacc(vd,vs1,vs2,vl); +} + + +vint64m8_t test___riscv_vwmacc(vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vwmacc(vd,vs1,vs2,vl); +} + + +vint16mf4_t test___riscv_vwmacc(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmacc(mask,vd,vs1,vs2,vl); +} + + +vint16mf2_t test___riscv_vwmacc(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc(mask,vd,vs1,vs2,vl); +} + + +vint16m1_t test___riscv_vwmacc(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc(mask,vd,vs1,vs2,vl); +} + + +vint16m2_t test___riscv_vwmacc(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vwmacc(mask,vd,vs1,vs2,vl); +} + + +vint16m4_t test___riscv_vwmacc(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vwmacc(mask,vd,vs1,vs2,vl); +} + + +vint16m8_t test___riscv_vwmacc(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vwmacc(mask,vd,vs1,vs2,vl); +} + + +vint32mf2_t test___riscv_vwmacc(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc(mask,vd,vs1,vs2,vl); +} + + +vint32m1_t test___riscv_vwmacc(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc(mask,vd,vs1,vs2,vl); +} + + +vint32m2_t test___riscv_vwmacc(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vwmacc(mask,vd,vs1,vs2,vl); +} + + +vint32m4_t test___riscv_vwmacc(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vwmacc(mask,vd,vs1,vs2,vl); +} + + +vint32m8_t test___riscv_vwmacc(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vwmacc(mask,vd,vs1,vs2,vl); +} + + +vint64m1_t test___riscv_vwmacc(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc(mask,vd,vs1,vs2,vl); +} + + +vint64m2_t test___riscv_vwmacc(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vwmacc(mask,vd,vs1,vs2,vl); +} + + +vint64m4_t test___riscv_vwmacc(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vwmacc(mask,vd,vs1,vs2,vl); +} + + +vint64m8_t test___riscv_vwmacc(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vwmacc(mask,vd,vs1,vs2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv-2.C new file mode 100644 index 00000000000..08c16d3955d --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv-2.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmacc(vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmacc(vd,vs1,vs2,31); +} + + +vint16mf2_t test___riscv_vwmacc(vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc(vd,vs1,vs2,31); +} + + +vint16m1_t test___riscv_vwmacc(vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc(vd,vs1,vs2,31); +} + + +vint16m2_t test___riscv_vwmacc(vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vwmacc(vd,vs1,vs2,31); +} + + +vint16m4_t test___riscv_vwmacc(vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vwmacc(vd,vs1,vs2,31); +} + + +vint16m8_t test___riscv_vwmacc(vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vwmacc(vd,vs1,vs2,31); +} + + +vint32mf2_t test___riscv_vwmacc(vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc(vd,vs1,vs2,31); +} + + +vint32m1_t test___riscv_vwmacc(vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc(vd,vs1,vs2,31); +} + + +vint32m2_t test___riscv_vwmacc(vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vwmacc(vd,vs1,vs2,31); +} + + +vint32m4_t test___riscv_vwmacc(vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vwmacc(vd,vs1,vs2,31); +} + + +vint32m8_t test___riscv_vwmacc(vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vwmacc(vd,vs1,vs2,31); +} + + +vint64m1_t test___riscv_vwmacc(vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc(vd,vs1,vs2,31); +} + + +vint64m2_t test___riscv_vwmacc(vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vwmacc(vd,vs1,vs2,31); +} + + +vint64m4_t test___riscv_vwmacc(vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vwmacc(vd,vs1,vs2,31); +} + + +vint64m8_t test___riscv_vwmacc(vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vwmacc(vd,vs1,vs2,31); +} + + +vint16mf4_t test___riscv_vwmacc(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmacc(mask,vd,vs1,vs2,31); +} + + +vint16mf2_t test___riscv_vwmacc(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc(mask,vd,vs1,vs2,31); +} + + +vint16m1_t test___riscv_vwmacc(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc(mask,vd,vs1,vs2,31); +} + + +vint16m2_t test___riscv_vwmacc(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vwmacc(mask,vd,vs1,vs2,31); +} + + +vint16m4_t test___riscv_vwmacc(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vwmacc(mask,vd,vs1,vs2,31); +} + + +vint16m8_t test___riscv_vwmacc(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vwmacc(mask,vd,vs1,vs2,31); +} + + +vint32mf2_t test___riscv_vwmacc(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc(mask,vd,vs1,vs2,31); +} + + +vint32m1_t test___riscv_vwmacc(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc(mask,vd,vs1,vs2,31); +} + + +vint32m2_t test___riscv_vwmacc(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vwmacc(mask,vd,vs1,vs2,31); +} + + +vint32m4_t test___riscv_vwmacc(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vwmacc(mask,vd,vs1,vs2,31); +} + + +vint32m8_t test___riscv_vwmacc(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vwmacc(mask,vd,vs1,vs2,31); +} + + +vint64m1_t test___riscv_vwmacc(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc(mask,vd,vs1,vs2,31); +} + + +vint64m2_t test___riscv_vwmacc(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vwmacc(mask,vd,vs1,vs2,31); +} + + +vint64m4_t test___riscv_vwmacc(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vwmacc(mask,vd,vs1,vs2,31); +} + + +vint64m8_t test___riscv_vwmacc(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vwmacc(mask,vd,vs1,vs2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv-3.C new file mode 100644 index 00000000000..870b62cf392 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv-3.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmacc(vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmacc(vd,vs1,vs2,32); +} + + +vint16mf2_t test___riscv_vwmacc(vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc(vd,vs1,vs2,32); +} + + +vint16m1_t test___riscv_vwmacc(vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc(vd,vs1,vs2,32); +} + + +vint16m2_t test___riscv_vwmacc(vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vwmacc(vd,vs1,vs2,32); +} + + +vint16m4_t test___riscv_vwmacc(vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vwmacc(vd,vs1,vs2,32); +} + + +vint16m8_t test___riscv_vwmacc(vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vwmacc(vd,vs1,vs2,32); +} + + +vint32mf2_t test___riscv_vwmacc(vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc(vd,vs1,vs2,32); +} + + +vint32m1_t test___riscv_vwmacc(vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc(vd,vs1,vs2,32); +} + + +vint32m2_t test___riscv_vwmacc(vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vwmacc(vd,vs1,vs2,32); +} + + +vint32m4_t test___riscv_vwmacc(vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vwmacc(vd,vs1,vs2,32); +} + + +vint32m8_t test___riscv_vwmacc(vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vwmacc(vd,vs1,vs2,32); +} + + +vint64m1_t test___riscv_vwmacc(vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc(vd,vs1,vs2,32); +} + + +vint64m2_t test___riscv_vwmacc(vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vwmacc(vd,vs1,vs2,32); +} + + +vint64m4_t test___riscv_vwmacc(vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vwmacc(vd,vs1,vs2,32); +} + + +vint64m8_t test___riscv_vwmacc(vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vwmacc(vd,vs1,vs2,32); +} + + +vint16mf4_t test___riscv_vwmacc(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmacc(mask,vd,vs1,vs2,32); +} + + +vint16mf2_t test___riscv_vwmacc(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc(mask,vd,vs1,vs2,32); +} + + +vint16m1_t test___riscv_vwmacc(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc(mask,vd,vs1,vs2,32); +} + + +vint16m2_t test___riscv_vwmacc(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vwmacc(mask,vd,vs1,vs2,32); +} + + +vint16m4_t test___riscv_vwmacc(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vwmacc(mask,vd,vs1,vs2,32); +} + + +vint16m8_t test___riscv_vwmacc(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vwmacc(mask,vd,vs1,vs2,32); +} + + +vint32mf2_t test___riscv_vwmacc(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc(mask,vd,vs1,vs2,32); +} + + +vint32m1_t test___riscv_vwmacc(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc(mask,vd,vs1,vs2,32); +} + + +vint32m2_t test___riscv_vwmacc(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vwmacc(mask,vd,vs1,vs2,32); +} + + +vint32m4_t test___riscv_vwmacc(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vwmacc(mask,vd,vs1,vs2,32); +} + + +vint32m8_t test___riscv_vwmacc(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vwmacc(mask,vd,vs1,vs2,32); +} + + +vint64m1_t test___riscv_vwmacc(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc(mask,vd,vs1,vs2,32); +} + + +vint64m2_t test___riscv_vwmacc(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vwmacc(mask,vd,vs1,vs2,32); +} + + +vint64m4_t test___riscv_vwmacc(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vwmacc(mask,vd,vs1,vs2,32); +} + + +vint64m8_t test___riscv_vwmacc(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vwmacc(mask,vd,vs1,vs2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_mu-1.C new file mode 100644 index 00000000000..4d8564beaeb --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_mu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmacc_mu(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmacc_mu(mask,vd,vs1,vs2,vl); +} + + +vint16mf2_t test___riscv_vwmacc_mu(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_mu(mask,vd,vs1,vs2,vl); +} + + +vint16m1_t test___riscv_vwmacc_mu(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_mu(mask,vd,vs1,vs2,vl); +} + + +vint16m2_t test___riscv_vwmacc_mu(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_mu(mask,vd,vs1,vs2,vl); +} + + +vint16m4_t test___riscv_vwmacc_mu(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_mu(mask,vd,vs1,vs2,vl); +} + + +vint16m8_t test___riscv_vwmacc_mu(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_mu(mask,vd,vs1,vs2,vl); +} + + +vint32mf2_t test___riscv_vwmacc_mu(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_mu(mask,vd,vs1,vs2,vl); +} + + +vint32m1_t test___riscv_vwmacc_mu(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_mu(mask,vd,vs1,vs2,vl); +} + + +vint32m2_t test___riscv_vwmacc_mu(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_mu(mask,vd,vs1,vs2,vl); +} + + +vint32m4_t test___riscv_vwmacc_mu(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_mu(mask,vd,vs1,vs2,vl); +} + + +vint32m8_t test___riscv_vwmacc_mu(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_mu(mask,vd,vs1,vs2,vl); +} + + +vint64m1_t test___riscv_vwmacc_mu(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_mu(mask,vd,vs1,vs2,vl); +} + + +vint64m2_t test___riscv_vwmacc_mu(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_mu(mask,vd,vs1,vs2,vl); +} + + +vint64m4_t test___riscv_vwmacc_mu(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_mu(mask,vd,vs1,vs2,vl); +} + + +vint64m8_t test___riscv_vwmacc_mu(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_mu(mask,vd,vs1,vs2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_mu-2.C new file mode 100644 index 00000000000..23ec15b7568 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_mu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmacc_mu(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmacc_mu(mask,vd,vs1,vs2,31); +} + + +vint16mf2_t test___riscv_vwmacc_mu(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_mu(mask,vd,vs1,vs2,31); +} + + +vint16m1_t test___riscv_vwmacc_mu(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_mu(mask,vd,vs1,vs2,31); +} + + +vint16m2_t test___riscv_vwmacc_mu(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_mu(mask,vd,vs1,vs2,31); +} + + +vint16m4_t test___riscv_vwmacc_mu(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_mu(mask,vd,vs1,vs2,31); +} + + +vint16m8_t test___riscv_vwmacc_mu(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_mu(mask,vd,vs1,vs2,31); +} + + +vint32mf2_t test___riscv_vwmacc_mu(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_mu(mask,vd,vs1,vs2,31); +} + + +vint32m1_t test___riscv_vwmacc_mu(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_mu(mask,vd,vs1,vs2,31); +} + + +vint32m2_t test___riscv_vwmacc_mu(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_mu(mask,vd,vs1,vs2,31); +} + + +vint32m4_t test___riscv_vwmacc_mu(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_mu(mask,vd,vs1,vs2,31); +} + + +vint32m8_t test___riscv_vwmacc_mu(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_mu(mask,vd,vs1,vs2,31); +} + + +vint64m1_t test___riscv_vwmacc_mu(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_mu(mask,vd,vs1,vs2,31); +} + + +vint64m2_t test___riscv_vwmacc_mu(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_mu(mask,vd,vs1,vs2,31); +} + + +vint64m4_t test___riscv_vwmacc_mu(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_mu(mask,vd,vs1,vs2,31); +} + + +vint64m8_t test___riscv_vwmacc_mu(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_mu(mask,vd,vs1,vs2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_mu-3.C new file mode 100644 index 00000000000..3e16e035563 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_mu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmacc_mu(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmacc_mu(mask,vd,vs1,vs2,32); +} + + +vint16mf2_t test___riscv_vwmacc_mu(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_mu(mask,vd,vs1,vs2,32); +} + + +vint16m1_t test___riscv_vwmacc_mu(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_mu(mask,vd,vs1,vs2,32); +} + + +vint16m2_t test___riscv_vwmacc_mu(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_mu(mask,vd,vs1,vs2,32); +} + + +vint16m4_t test___riscv_vwmacc_mu(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_mu(mask,vd,vs1,vs2,32); +} + + +vint16m8_t test___riscv_vwmacc_mu(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_mu(mask,vd,vs1,vs2,32); +} + + +vint32mf2_t test___riscv_vwmacc_mu(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_mu(mask,vd,vs1,vs2,32); +} + + +vint32m1_t test___riscv_vwmacc_mu(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_mu(mask,vd,vs1,vs2,32); +} + + +vint32m2_t test___riscv_vwmacc_mu(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_mu(mask,vd,vs1,vs2,32); +} + + +vint32m4_t test___riscv_vwmacc_mu(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_mu(mask,vd,vs1,vs2,32); +} + + +vint32m8_t test___riscv_vwmacc_mu(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_mu(mask,vd,vs1,vs2,32); +} + + +vint64m1_t test___riscv_vwmacc_mu(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_mu(mask,vd,vs1,vs2,32); +} + + +vint64m2_t test___riscv_vwmacc_mu(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_mu(mask,vd,vs1,vs2,32); +} + + +vint64m4_t test___riscv_vwmacc_mu(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_mu(mask,vd,vs1,vs2,32); +} + + +vint64m8_t test___riscv_vwmacc_mu(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_mu(mask,vd,vs1,vs2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tu-1.C new file mode 100644 index 00000000000..397d3f01198 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmacc_tu(vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmacc_tu(vd,vs1,vs2,vl); +} + + +vint16mf2_t test___riscv_vwmacc_tu(vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_tu(vd,vs1,vs2,vl); +} + + +vint16m1_t test___riscv_vwmacc_tu(vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_tu(vd,vs1,vs2,vl); +} + + +vint16m2_t test___riscv_vwmacc_tu(vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_tu(vd,vs1,vs2,vl); +} + + +vint16m4_t test___riscv_vwmacc_tu(vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_tu(vd,vs1,vs2,vl); +} + + +vint16m8_t test___riscv_vwmacc_tu(vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_tu(vd,vs1,vs2,vl); +} + + +vint32mf2_t test___riscv_vwmacc_tu(vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_tu(vd,vs1,vs2,vl); +} + + +vint32m1_t test___riscv_vwmacc_tu(vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_tu(vd,vs1,vs2,vl); +} + + +vint32m2_t test___riscv_vwmacc_tu(vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_tu(vd,vs1,vs2,vl); +} + + +vint32m4_t test___riscv_vwmacc_tu(vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_tu(vd,vs1,vs2,vl); +} + + +vint32m8_t test___riscv_vwmacc_tu(vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_tu(vd,vs1,vs2,vl); +} + + +vint64m1_t test___riscv_vwmacc_tu(vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_tu(vd,vs1,vs2,vl); +} + + +vint64m2_t test___riscv_vwmacc_tu(vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_tu(vd,vs1,vs2,vl); +} + + +vint64m4_t test___riscv_vwmacc_tu(vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_tu(vd,vs1,vs2,vl); +} + + +vint64m8_t test___riscv_vwmacc_tu(vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_tu(vd,vs1,vs2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tu-2.C new file mode 100644 index 00000000000..08276ad193c --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmacc_tu(vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmacc_tu(vd,vs1,vs2,31); +} + + +vint16mf2_t test___riscv_vwmacc_tu(vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_tu(vd,vs1,vs2,31); +} + + +vint16m1_t test___riscv_vwmacc_tu(vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_tu(vd,vs1,vs2,31); +} + + +vint16m2_t test___riscv_vwmacc_tu(vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_tu(vd,vs1,vs2,31); +} + + +vint16m4_t test___riscv_vwmacc_tu(vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_tu(vd,vs1,vs2,31); +} + + +vint16m8_t test___riscv_vwmacc_tu(vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_tu(vd,vs1,vs2,31); +} + + +vint32mf2_t test___riscv_vwmacc_tu(vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_tu(vd,vs1,vs2,31); +} + + +vint32m1_t test___riscv_vwmacc_tu(vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_tu(vd,vs1,vs2,31); +} + + +vint32m2_t test___riscv_vwmacc_tu(vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_tu(vd,vs1,vs2,31); +} + + +vint32m4_t test___riscv_vwmacc_tu(vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_tu(vd,vs1,vs2,31); +} + + +vint32m8_t test___riscv_vwmacc_tu(vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_tu(vd,vs1,vs2,31); +} + + +vint64m1_t test___riscv_vwmacc_tu(vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_tu(vd,vs1,vs2,31); +} + + +vint64m2_t test___riscv_vwmacc_tu(vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_tu(vd,vs1,vs2,31); +} + + +vint64m4_t test___riscv_vwmacc_tu(vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_tu(vd,vs1,vs2,31); +} + + +vint64m8_t test___riscv_vwmacc_tu(vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_tu(vd,vs1,vs2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tu-3.C new file mode 100644 index 00000000000..f7df4b17e66 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmacc_tu(vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmacc_tu(vd,vs1,vs2,32); +} + + +vint16mf2_t test___riscv_vwmacc_tu(vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_tu(vd,vs1,vs2,32); +} + + +vint16m1_t test___riscv_vwmacc_tu(vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_tu(vd,vs1,vs2,32); +} + + +vint16m2_t test___riscv_vwmacc_tu(vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_tu(vd,vs1,vs2,32); +} + + +vint16m4_t test___riscv_vwmacc_tu(vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_tu(vd,vs1,vs2,32); +} + + +vint16m8_t test___riscv_vwmacc_tu(vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_tu(vd,vs1,vs2,32); +} + + +vint32mf2_t test___riscv_vwmacc_tu(vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_tu(vd,vs1,vs2,32); +} + + +vint32m1_t test___riscv_vwmacc_tu(vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_tu(vd,vs1,vs2,32); +} + + +vint32m2_t test___riscv_vwmacc_tu(vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_tu(vd,vs1,vs2,32); +} + + +vint32m4_t test___riscv_vwmacc_tu(vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_tu(vd,vs1,vs2,32); +} + + +vint32m8_t test___riscv_vwmacc_tu(vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_tu(vd,vs1,vs2,32); +} + + +vint64m1_t test___riscv_vwmacc_tu(vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_tu(vd,vs1,vs2,32); +} + + +vint64m2_t test___riscv_vwmacc_tu(vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_tu(vd,vs1,vs2,32); +} + + +vint64m4_t test___riscv_vwmacc_tu(vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_tu(vd,vs1,vs2,32); +} + + +vint64m8_t test___riscv_vwmacc_tu(vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_tu(vd,vs1,vs2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tum-1.C new file mode 100644 index 00000000000..afed070daf9 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tum-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmacc_tum(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmacc_tum(mask,vd,vs1,vs2,vl); +} + + +vint16mf2_t test___riscv_vwmacc_tum(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_tum(mask,vd,vs1,vs2,vl); +} + + +vint16m1_t test___riscv_vwmacc_tum(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_tum(mask,vd,vs1,vs2,vl); +} + + +vint16m2_t test___riscv_vwmacc_tum(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_tum(mask,vd,vs1,vs2,vl); +} + + +vint16m4_t test___riscv_vwmacc_tum(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_tum(mask,vd,vs1,vs2,vl); +} + + +vint16m8_t test___riscv_vwmacc_tum(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_tum(mask,vd,vs1,vs2,vl); +} + + +vint32mf2_t test___riscv_vwmacc_tum(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_tum(mask,vd,vs1,vs2,vl); +} + + +vint32m1_t test___riscv_vwmacc_tum(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_tum(mask,vd,vs1,vs2,vl); +} + + +vint32m2_t test___riscv_vwmacc_tum(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_tum(mask,vd,vs1,vs2,vl); +} + + +vint32m4_t test___riscv_vwmacc_tum(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_tum(mask,vd,vs1,vs2,vl); +} + + +vint32m8_t test___riscv_vwmacc_tum(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_tum(mask,vd,vs1,vs2,vl); +} + + +vint64m1_t test___riscv_vwmacc_tum(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_tum(mask,vd,vs1,vs2,vl); +} + + +vint64m2_t test___riscv_vwmacc_tum(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_tum(mask,vd,vs1,vs2,vl); +} + + +vint64m4_t test___riscv_vwmacc_tum(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_tum(mask,vd,vs1,vs2,vl); +} + + +vint64m8_t test___riscv_vwmacc_tum(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_tum(mask,vd,vs1,vs2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tum-2.C new file mode 100644 index 00000000000..657b4d9cf23 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tum-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmacc_tum(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmacc_tum(mask,vd,vs1,vs2,31); +} + + +vint16mf2_t test___riscv_vwmacc_tum(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_tum(mask,vd,vs1,vs2,31); +} + + +vint16m1_t test___riscv_vwmacc_tum(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_tum(mask,vd,vs1,vs2,31); +} + + +vint16m2_t test___riscv_vwmacc_tum(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_tum(mask,vd,vs1,vs2,31); +} + + +vint16m4_t test___riscv_vwmacc_tum(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_tum(mask,vd,vs1,vs2,31); +} + + +vint16m8_t test___riscv_vwmacc_tum(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_tum(mask,vd,vs1,vs2,31); +} + + +vint32mf2_t test___riscv_vwmacc_tum(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_tum(mask,vd,vs1,vs2,31); +} + + +vint32m1_t test___riscv_vwmacc_tum(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_tum(mask,vd,vs1,vs2,31); +} + + +vint32m2_t test___riscv_vwmacc_tum(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_tum(mask,vd,vs1,vs2,31); +} + + +vint32m4_t test___riscv_vwmacc_tum(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_tum(mask,vd,vs1,vs2,31); +} + + +vint32m8_t test___riscv_vwmacc_tum(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_tum(mask,vd,vs1,vs2,31); +} + + +vint64m1_t test___riscv_vwmacc_tum(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_tum(mask,vd,vs1,vs2,31); +} + + +vint64m2_t test___riscv_vwmacc_tum(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_tum(mask,vd,vs1,vs2,31); +} + + +vint64m4_t test___riscv_vwmacc_tum(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_tum(mask,vd,vs1,vs2,31); +} + + +vint64m8_t test___riscv_vwmacc_tum(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_tum(mask,vd,vs1,vs2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tum-3.C new file mode 100644 index 00000000000..9d28777964d --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tum-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmacc_tum(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmacc_tum(mask,vd,vs1,vs2,32); +} + + +vint16mf2_t test___riscv_vwmacc_tum(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_tum(mask,vd,vs1,vs2,32); +} + + +vint16m1_t test___riscv_vwmacc_tum(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_tum(mask,vd,vs1,vs2,32); +} + + +vint16m2_t test___riscv_vwmacc_tum(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_tum(mask,vd,vs1,vs2,32); +} + + +vint16m4_t test___riscv_vwmacc_tum(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_tum(mask,vd,vs1,vs2,32); +} + + +vint16m8_t test___riscv_vwmacc_tum(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_tum(mask,vd,vs1,vs2,32); +} + + +vint32mf2_t test___riscv_vwmacc_tum(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_tum(mask,vd,vs1,vs2,32); +} + + +vint32m1_t test___riscv_vwmacc_tum(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_tum(mask,vd,vs1,vs2,32); +} + + +vint32m2_t test___riscv_vwmacc_tum(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_tum(mask,vd,vs1,vs2,32); +} + + +vint32m4_t test___riscv_vwmacc_tum(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_tum(mask,vd,vs1,vs2,32); +} + + +vint32m8_t test___riscv_vwmacc_tum(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_tum(mask,vd,vs1,vs2,32); +} + + +vint64m1_t test___riscv_vwmacc_tum(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_tum(mask,vd,vs1,vs2,32); +} + + +vint64m2_t test___riscv_vwmacc_tum(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_tum(mask,vd,vs1,vs2,32); +} + + +vint64m4_t test___riscv_vwmacc_tum(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_tum(mask,vd,vs1,vs2,32); +} + + +vint64m8_t test___riscv_vwmacc_tum(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_tum(mask,vd,vs1,vs2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tumu-1.C new file mode 100644 index 00000000000..e45bcf5695a --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tumu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmacc_tumu(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,vl); +} + + +vint16mf2_t test___riscv_vwmacc_tumu(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,vl); +} + + +vint16m1_t test___riscv_vwmacc_tumu(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,vl); +} + + +vint16m2_t test___riscv_vwmacc_tumu(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,vl); +} + + +vint16m4_t test___riscv_vwmacc_tumu(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,vl); +} + + +vint16m8_t test___riscv_vwmacc_tumu(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,vl); +} + + +vint32mf2_t test___riscv_vwmacc_tumu(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,vl); +} + + +vint32m1_t test___riscv_vwmacc_tumu(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,vl); +} + + +vint32m2_t test___riscv_vwmacc_tumu(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,vl); +} + + +vint32m4_t test___riscv_vwmacc_tumu(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,vl); +} + + +vint32m8_t test___riscv_vwmacc_tumu(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,vl); +} + + +vint64m1_t test___riscv_vwmacc_tumu(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,vl); +} + + +vint64m2_t test___riscv_vwmacc_tumu(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,vl); +} + + +vint64m4_t test___riscv_vwmacc_tumu(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,vl); +} + + +vint64m8_t test___riscv_vwmacc_tumu(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tumu-2.C new file mode 100644 index 00000000000..d5a01238cc6 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tumu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmacc_tumu(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,31); +} + + +vint16mf2_t test___riscv_vwmacc_tumu(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,31); +} + + +vint16m1_t test___riscv_vwmacc_tumu(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,31); +} + + +vint16m2_t test___riscv_vwmacc_tumu(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,31); +} + + +vint16m4_t test___riscv_vwmacc_tumu(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,31); +} + + +vint16m8_t test___riscv_vwmacc_tumu(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,31); +} + + +vint32mf2_t test___riscv_vwmacc_tumu(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,31); +} + + +vint32m1_t test___riscv_vwmacc_tumu(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,31); +} + + +vint32m2_t test___riscv_vwmacc_tumu(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,31); +} + + +vint32m4_t test___riscv_vwmacc_tumu(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,31); +} + + +vint32m8_t test___riscv_vwmacc_tumu(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,31); +} + + +vint64m1_t test___riscv_vwmacc_tumu(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,31); +} + + +vint64m2_t test___riscv_vwmacc_tumu(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,31); +} + + +vint64m4_t test___riscv_vwmacc_tumu(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,31); +} + + +vint64m8_t test___riscv_vwmacc_tumu(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tumu-3.C new file mode 100644 index 00000000000..773f7095c9c --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmacc_vv_tumu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmacc_tumu(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,32); +} + + +vint16mf2_t test___riscv_vwmacc_tumu(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,32); +} + + +vint16m1_t test___riscv_vwmacc_tumu(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,32); +} + + +vint16m2_t test___riscv_vwmacc_tumu(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vint8m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,32); +} + + +vint16m4_t test___riscv_vwmacc_tumu(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vint8m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,32); +} + + +vint16m8_t test___riscv_vwmacc_tumu(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vint8m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,32); +} + + +vint32mf2_t test___riscv_vwmacc_tumu(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,32); +} + + +vint32m1_t test___riscv_vwmacc_tumu(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,32); +} + + +vint32m2_t test___riscv_vwmacc_tumu(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vint16m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,32); +} + + +vint32m4_t test___riscv_vwmacc_tumu(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vint16m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,32); +} + + +vint32m8_t test___riscv_vwmacc_tumu(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vint16m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,32); +} + + +vint64m1_t test___riscv_vwmacc_tumu(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,32); +} + + +vint64m2_t test___riscv_vwmacc_tumu(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vint32m1_t vs2,size_t vl) +{ + return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,32); +} + + +vint64m4_t test___riscv_vwmacc_tumu(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vint32m2_t vs2,size_t vl) +{ + return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,32); +} + + +vint64m8_t test___riscv_vwmacc_tumu(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vint32m4_t vs2,size_t vl) +{ + return __riscv_vwmacc_tumu(mask,vd,vs1,vs2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmacc\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv-1.C new file mode 100644 index 00000000000..28f5a3831c9 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv-1.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmaccsu(vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(vd,vs1,vs2,vl); +} + + +vint16mf2_t test___riscv_vwmaccsu(vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(vd,vs1,vs2,vl); +} + + +vint16m1_t test___riscv_vwmaccsu(vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(vd,vs1,vs2,vl); +} + + +vint16m2_t test___riscv_vwmaccsu(vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(vd,vs1,vs2,vl); +} + + +vint16m4_t test___riscv_vwmaccsu(vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(vd,vs1,vs2,vl); +} + + +vint16m8_t test___riscv_vwmaccsu(vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(vd,vs1,vs2,vl); +} + + +vint32mf2_t test___riscv_vwmaccsu(vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(vd,vs1,vs2,vl); +} + + +vint32m1_t test___riscv_vwmaccsu(vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(vd,vs1,vs2,vl); +} + + +vint32m2_t test___riscv_vwmaccsu(vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(vd,vs1,vs2,vl); +} + + +vint32m4_t test___riscv_vwmaccsu(vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(vd,vs1,vs2,vl); +} + + +vint32m8_t test___riscv_vwmaccsu(vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(vd,vs1,vs2,vl); +} + + +vint64m1_t test___riscv_vwmaccsu(vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(vd,vs1,vs2,vl); +} + + +vint64m2_t test___riscv_vwmaccsu(vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(vd,vs1,vs2,vl); +} + + +vint64m4_t test___riscv_vwmaccsu(vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(vd,vs1,vs2,vl); +} + + +vint64m8_t test___riscv_vwmaccsu(vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(vd,vs1,vs2,vl); +} + + +vint16mf4_t test___riscv_vwmaccsu(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(mask,vd,vs1,vs2,vl); +} + + +vint16mf2_t test___riscv_vwmaccsu(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(mask,vd,vs1,vs2,vl); +} + + +vint16m1_t test___riscv_vwmaccsu(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(mask,vd,vs1,vs2,vl); +} + + +vint16m2_t test___riscv_vwmaccsu(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(mask,vd,vs1,vs2,vl); +} + + +vint16m4_t test___riscv_vwmaccsu(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(mask,vd,vs1,vs2,vl); +} + + +vint16m8_t test___riscv_vwmaccsu(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(mask,vd,vs1,vs2,vl); +} + + +vint32mf2_t test___riscv_vwmaccsu(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(mask,vd,vs1,vs2,vl); +} + + +vint32m1_t test___riscv_vwmaccsu(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(mask,vd,vs1,vs2,vl); +} + + +vint32m2_t test___riscv_vwmaccsu(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(mask,vd,vs1,vs2,vl); +} + + +vint32m4_t test___riscv_vwmaccsu(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(mask,vd,vs1,vs2,vl); +} + + +vint32m8_t test___riscv_vwmaccsu(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(mask,vd,vs1,vs2,vl); +} + + +vint64m1_t test___riscv_vwmaccsu(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(mask,vd,vs1,vs2,vl); +} + + +vint64m2_t test___riscv_vwmaccsu(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(mask,vd,vs1,vs2,vl); +} + + +vint64m4_t test___riscv_vwmaccsu(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(mask,vd,vs1,vs2,vl); +} + + +vint64m8_t test___riscv_vwmaccsu(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(mask,vd,vs1,vs2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv-2.C new file mode 100644 index 00000000000..4ccbc3a703a --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv-2.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmaccsu(vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(vd,vs1,vs2,31); +} + + +vint16mf2_t test___riscv_vwmaccsu(vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(vd,vs1,vs2,31); +} + + +vint16m1_t test___riscv_vwmaccsu(vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(vd,vs1,vs2,31); +} + + +vint16m2_t test___riscv_vwmaccsu(vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(vd,vs1,vs2,31); +} + + +vint16m4_t test___riscv_vwmaccsu(vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(vd,vs1,vs2,31); +} + + +vint16m8_t test___riscv_vwmaccsu(vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(vd,vs1,vs2,31); +} + + +vint32mf2_t test___riscv_vwmaccsu(vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(vd,vs1,vs2,31); +} + + +vint32m1_t test___riscv_vwmaccsu(vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(vd,vs1,vs2,31); +} + + +vint32m2_t test___riscv_vwmaccsu(vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(vd,vs1,vs2,31); +} + + +vint32m4_t test___riscv_vwmaccsu(vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(vd,vs1,vs2,31); +} + + +vint32m8_t test___riscv_vwmaccsu(vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(vd,vs1,vs2,31); +} + + +vint64m1_t test___riscv_vwmaccsu(vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(vd,vs1,vs2,31); +} + + +vint64m2_t test___riscv_vwmaccsu(vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(vd,vs1,vs2,31); +} + + +vint64m4_t test___riscv_vwmaccsu(vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(vd,vs1,vs2,31); +} + + +vint64m8_t test___riscv_vwmaccsu(vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(vd,vs1,vs2,31); +} + + +vint16mf4_t test___riscv_vwmaccsu(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(mask,vd,vs1,vs2,31); +} + + +vint16mf2_t test___riscv_vwmaccsu(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(mask,vd,vs1,vs2,31); +} + + +vint16m1_t test___riscv_vwmaccsu(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(mask,vd,vs1,vs2,31); +} + + +vint16m2_t test___riscv_vwmaccsu(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(mask,vd,vs1,vs2,31); +} + + +vint16m4_t test___riscv_vwmaccsu(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(mask,vd,vs1,vs2,31); +} + + +vint16m8_t test___riscv_vwmaccsu(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(mask,vd,vs1,vs2,31); +} + + +vint32mf2_t test___riscv_vwmaccsu(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(mask,vd,vs1,vs2,31); +} + + +vint32m1_t test___riscv_vwmaccsu(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(mask,vd,vs1,vs2,31); +} + + +vint32m2_t test___riscv_vwmaccsu(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(mask,vd,vs1,vs2,31); +} + + +vint32m4_t test___riscv_vwmaccsu(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(mask,vd,vs1,vs2,31); +} + + +vint32m8_t test___riscv_vwmaccsu(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(mask,vd,vs1,vs2,31); +} + + +vint64m1_t test___riscv_vwmaccsu(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(mask,vd,vs1,vs2,31); +} + + +vint64m2_t test___riscv_vwmaccsu(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(mask,vd,vs1,vs2,31); +} + + +vint64m4_t test___riscv_vwmaccsu(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(mask,vd,vs1,vs2,31); +} + + +vint64m8_t test___riscv_vwmaccsu(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(mask,vd,vs1,vs2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv-3.C new file mode 100644 index 00000000000..b60666b0319 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv-3.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmaccsu(vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(vd,vs1,vs2,32); +} + + +vint16mf2_t test___riscv_vwmaccsu(vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(vd,vs1,vs2,32); +} + + +vint16m1_t test___riscv_vwmaccsu(vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(vd,vs1,vs2,32); +} + + +vint16m2_t test___riscv_vwmaccsu(vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(vd,vs1,vs2,32); +} + + +vint16m4_t test___riscv_vwmaccsu(vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(vd,vs1,vs2,32); +} + + +vint16m8_t test___riscv_vwmaccsu(vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(vd,vs1,vs2,32); +} + + +vint32mf2_t test___riscv_vwmaccsu(vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(vd,vs1,vs2,32); +} + + +vint32m1_t test___riscv_vwmaccsu(vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(vd,vs1,vs2,32); +} + + +vint32m2_t test___riscv_vwmaccsu(vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(vd,vs1,vs2,32); +} + + +vint32m4_t test___riscv_vwmaccsu(vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(vd,vs1,vs2,32); +} + + +vint32m8_t test___riscv_vwmaccsu(vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(vd,vs1,vs2,32); +} + + +vint64m1_t test___riscv_vwmaccsu(vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(vd,vs1,vs2,32); +} + + +vint64m2_t test___riscv_vwmaccsu(vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(vd,vs1,vs2,32); +} + + +vint64m4_t test___riscv_vwmaccsu(vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(vd,vs1,vs2,32); +} + + +vint64m8_t test___riscv_vwmaccsu(vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(vd,vs1,vs2,32); +} + + +vint16mf4_t test___riscv_vwmaccsu(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(mask,vd,vs1,vs2,32); +} + + +vint16mf2_t test___riscv_vwmaccsu(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(mask,vd,vs1,vs2,32); +} + + +vint16m1_t test___riscv_vwmaccsu(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(mask,vd,vs1,vs2,32); +} + + +vint16m2_t test___riscv_vwmaccsu(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(mask,vd,vs1,vs2,32); +} + + +vint16m4_t test___riscv_vwmaccsu(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(mask,vd,vs1,vs2,32); +} + + +vint16m8_t test___riscv_vwmaccsu(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(mask,vd,vs1,vs2,32); +} + + +vint32mf2_t test___riscv_vwmaccsu(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(mask,vd,vs1,vs2,32); +} + + +vint32m1_t test___riscv_vwmaccsu(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(mask,vd,vs1,vs2,32); +} + + +vint32m2_t test___riscv_vwmaccsu(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(mask,vd,vs1,vs2,32); +} + + +vint32m4_t test___riscv_vwmaccsu(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(mask,vd,vs1,vs2,32); +} + + +vint32m8_t test___riscv_vwmaccsu(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(mask,vd,vs1,vs2,32); +} + + +vint64m1_t test___riscv_vwmaccsu(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(mask,vd,vs1,vs2,32); +} + + +vint64m2_t test___riscv_vwmaccsu(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(mask,vd,vs1,vs2,32); +} + + +vint64m4_t test___riscv_vwmaccsu(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(mask,vd,vs1,vs2,32); +} + + +vint64m8_t test___riscv_vwmaccsu(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu(mask,vd,vs1,vs2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_mu-1.C new file mode 100644 index 00000000000..65815081b04 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_mu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmaccsu_mu(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,vl); +} + + +vint16mf2_t test___riscv_vwmaccsu_mu(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,vl); +} + + +vint16m1_t test___riscv_vwmaccsu_mu(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,vl); +} + + +vint16m2_t test___riscv_vwmaccsu_mu(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,vl); +} + + +vint16m4_t test___riscv_vwmaccsu_mu(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,vl); +} + + +vint16m8_t test___riscv_vwmaccsu_mu(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,vl); +} + + +vint32mf2_t test___riscv_vwmaccsu_mu(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,vl); +} + + +vint32m1_t test___riscv_vwmaccsu_mu(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,vl); +} + + +vint32m2_t test___riscv_vwmaccsu_mu(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,vl); +} + + +vint32m4_t test___riscv_vwmaccsu_mu(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,vl); +} + + +vint32m8_t test___riscv_vwmaccsu_mu(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,vl); +} + + +vint64m1_t test___riscv_vwmaccsu_mu(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,vl); +} + + +vint64m2_t test___riscv_vwmaccsu_mu(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,vl); +} + + +vint64m4_t test___riscv_vwmaccsu_mu(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,vl); +} + + +vint64m8_t test___riscv_vwmaccsu_mu(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_mu-2.C new file mode 100644 index 00000000000..1704a0c9611 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_mu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmaccsu_mu(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,31); +} + + +vint16mf2_t test___riscv_vwmaccsu_mu(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,31); +} + + +vint16m1_t test___riscv_vwmaccsu_mu(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,31); +} + + +vint16m2_t test___riscv_vwmaccsu_mu(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,31); +} + + +vint16m4_t test___riscv_vwmaccsu_mu(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,31); +} + + +vint16m8_t test___riscv_vwmaccsu_mu(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,31); +} + + +vint32mf2_t test___riscv_vwmaccsu_mu(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,31); +} + + +vint32m1_t test___riscv_vwmaccsu_mu(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,31); +} + + +vint32m2_t test___riscv_vwmaccsu_mu(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,31); +} + + +vint32m4_t test___riscv_vwmaccsu_mu(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,31); +} + + +vint32m8_t test___riscv_vwmaccsu_mu(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,31); +} + + +vint64m1_t test___riscv_vwmaccsu_mu(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,31); +} + + +vint64m2_t test___riscv_vwmaccsu_mu(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,31); +} + + +vint64m4_t test___riscv_vwmaccsu_mu(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,31); +} + + +vint64m8_t test___riscv_vwmaccsu_mu(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_mu-3.C new file mode 100644 index 00000000000..4107fd73e8d --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_mu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmaccsu_mu(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,32); +} + + +vint16mf2_t test___riscv_vwmaccsu_mu(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,32); +} + + +vint16m1_t test___riscv_vwmaccsu_mu(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,32); +} + + +vint16m2_t test___riscv_vwmaccsu_mu(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,32); +} + + +vint16m4_t test___riscv_vwmaccsu_mu(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,32); +} + + +vint16m8_t test___riscv_vwmaccsu_mu(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,32); +} + + +vint32mf2_t test___riscv_vwmaccsu_mu(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,32); +} + + +vint32m1_t test___riscv_vwmaccsu_mu(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,32); +} + + +vint32m2_t test___riscv_vwmaccsu_mu(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,32); +} + + +vint32m4_t test___riscv_vwmaccsu_mu(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,32); +} + + +vint32m8_t test___riscv_vwmaccsu_mu(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,32); +} + + +vint64m1_t test___riscv_vwmaccsu_mu(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,32); +} + + +vint64m2_t test___riscv_vwmaccsu_mu(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,32); +} + + +vint64m4_t test___riscv_vwmaccsu_mu(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,32); +} + + +vint64m8_t test___riscv_vwmaccsu_mu(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_mu(mask,vd,vs1,vs2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tu-1.C new file mode 100644 index 00000000000..5570d279db7 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmaccsu_tu(vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tu(vd,vs1,vs2,vl); +} + + +vint16mf2_t test___riscv_vwmaccsu_tu(vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tu(vd,vs1,vs2,vl); +} + + +vint16m1_t test___riscv_vwmaccsu_tu(vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tu(vd,vs1,vs2,vl); +} + + +vint16m2_t test___riscv_vwmaccsu_tu(vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tu(vd,vs1,vs2,vl); +} + + +vint16m4_t test___riscv_vwmaccsu_tu(vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tu(vd,vs1,vs2,vl); +} + + +vint16m8_t test___riscv_vwmaccsu_tu(vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tu(vd,vs1,vs2,vl); +} + + +vint32mf2_t test___riscv_vwmaccsu_tu(vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tu(vd,vs1,vs2,vl); +} + + +vint32m1_t test___riscv_vwmaccsu_tu(vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tu(vd,vs1,vs2,vl); +} + + +vint32m2_t test___riscv_vwmaccsu_tu(vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tu(vd,vs1,vs2,vl); +} + + +vint32m4_t test___riscv_vwmaccsu_tu(vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tu(vd,vs1,vs2,vl); +} + + +vint32m8_t test___riscv_vwmaccsu_tu(vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tu(vd,vs1,vs2,vl); +} + + +vint64m1_t test___riscv_vwmaccsu_tu(vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tu(vd,vs1,vs2,vl); +} + + +vint64m2_t test___riscv_vwmaccsu_tu(vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tu(vd,vs1,vs2,vl); +} + + +vint64m4_t test___riscv_vwmaccsu_tu(vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tu(vd,vs1,vs2,vl); +} + + +vint64m8_t test___riscv_vwmaccsu_tu(vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tu(vd,vs1,vs2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tu-2.C new file mode 100644 index 00000000000..5034aa4a753 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmaccsu_tu(vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tu(vd,vs1,vs2,31); +} + + +vint16mf2_t test___riscv_vwmaccsu_tu(vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tu(vd,vs1,vs2,31); +} + + +vint16m1_t test___riscv_vwmaccsu_tu(vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tu(vd,vs1,vs2,31); +} + + +vint16m2_t test___riscv_vwmaccsu_tu(vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tu(vd,vs1,vs2,31); +} + + +vint16m4_t test___riscv_vwmaccsu_tu(vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tu(vd,vs1,vs2,31); +} + + +vint16m8_t test___riscv_vwmaccsu_tu(vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tu(vd,vs1,vs2,31); +} + + +vint32mf2_t test___riscv_vwmaccsu_tu(vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tu(vd,vs1,vs2,31); +} + + +vint32m1_t test___riscv_vwmaccsu_tu(vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tu(vd,vs1,vs2,31); +} + + +vint32m2_t test___riscv_vwmaccsu_tu(vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tu(vd,vs1,vs2,31); +} + + +vint32m4_t test___riscv_vwmaccsu_tu(vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tu(vd,vs1,vs2,31); +} + + +vint32m8_t test___riscv_vwmaccsu_tu(vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tu(vd,vs1,vs2,31); +} + + +vint64m1_t test___riscv_vwmaccsu_tu(vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tu(vd,vs1,vs2,31); +} + + +vint64m2_t test___riscv_vwmaccsu_tu(vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tu(vd,vs1,vs2,31); +} + + +vint64m4_t test___riscv_vwmaccsu_tu(vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tu(vd,vs1,vs2,31); +} + + +vint64m8_t test___riscv_vwmaccsu_tu(vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tu(vd,vs1,vs2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tu-3.C new file mode 100644 index 00000000000..6e0b65b0c22 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmaccsu_tu(vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tu(vd,vs1,vs2,32); +} + + +vint16mf2_t test___riscv_vwmaccsu_tu(vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tu(vd,vs1,vs2,32); +} + + +vint16m1_t test___riscv_vwmaccsu_tu(vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tu(vd,vs1,vs2,32); +} + + +vint16m2_t test___riscv_vwmaccsu_tu(vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tu(vd,vs1,vs2,32); +} + + +vint16m4_t test___riscv_vwmaccsu_tu(vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tu(vd,vs1,vs2,32); +} + + +vint16m8_t test___riscv_vwmaccsu_tu(vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tu(vd,vs1,vs2,32); +} + + +vint32mf2_t test___riscv_vwmaccsu_tu(vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tu(vd,vs1,vs2,32); +} + + +vint32m1_t test___riscv_vwmaccsu_tu(vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tu(vd,vs1,vs2,32); +} + + +vint32m2_t test___riscv_vwmaccsu_tu(vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tu(vd,vs1,vs2,32); +} + + +vint32m4_t test___riscv_vwmaccsu_tu(vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tu(vd,vs1,vs2,32); +} + + +vint32m8_t test___riscv_vwmaccsu_tu(vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tu(vd,vs1,vs2,32); +} + + +vint64m1_t test___riscv_vwmaccsu_tu(vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tu(vd,vs1,vs2,32); +} + + +vint64m2_t test___riscv_vwmaccsu_tu(vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tu(vd,vs1,vs2,32); +} + + +vint64m4_t test___riscv_vwmaccsu_tu(vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tu(vd,vs1,vs2,32); +} + + +vint64m8_t test___riscv_vwmaccsu_tu(vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tu(vd,vs1,vs2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tum-1.C new file mode 100644 index 00000000000..5c2a3a5bca6 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tum-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmaccsu_tum(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,vl); +} + + +vint16mf2_t test___riscv_vwmaccsu_tum(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,vl); +} + + +vint16m1_t test___riscv_vwmaccsu_tum(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,vl); +} + + +vint16m2_t test___riscv_vwmaccsu_tum(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,vl); +} + + +vint16m4_t test___riscv_vwmaccsu_tum(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,vl); +} + + +vint16m8_t test___riscv_vwmaccsu_tum(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,vl); +} + + +vint32mf2_t test___riscv_vwmaccsu_tum(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,vl); +} + + +vint32m1_t test___riscv_vwmaccsu_tum(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,vl); +} + + +vint32m2_t test___riscv_vwmaccsu_tum(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,vl); +} + + +vint32m4_t test___riscv_vwmaccsu_tum(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,vl); +} + + +vint32m8_t test___riscv_vwmaccsu_tum(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,vl); +} + + +vint64m1_t test___riscv_vwmaccsu_tum(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,vl); +} + + +vint64m2_t test___riscv_vwmaccsu_tum(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,vl); +} + + +vint64m4_t test___riscv_vwmaccsu_tum(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,vl); +} + + +vint64m8_t test___riscv_vwmaccsu_tum(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tum-2.C new file mode 100644 index 00000000000..6aaf403fca8 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tum-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmaccsu_tum(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,31); +} + + +vint16mf2_t test___riscv_vwmaccsu_tum(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,31); +} + + +vint16m1_t test___riscv_vwmaccsu_tum(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,31); +} + + +vint16m2_t test___riscv_vwmaccsu_tum(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,31); +} + + +vint16m4_t test___riscv_vwmaccsu_tum(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,31); +} + + +vint16m8_t test___riscv_vwmaccsu_tum(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,31); +} + + +vint32mf2_t test___riscv_vwmaccsu_tum(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,31); +} + + +vint32m1_t test___riscv_vwmaccsu_tum(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,31); +} + + +vint32m2_t test___riscv_vwmaccsu_tum(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,31); +} + + +vint32m4_t test___riscv_vwmaccsu_tum(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,31); +} + + +vint32m8_t test___riscv_vwmaccsu_tum(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,31); +} + + +vint64m1_t test___riscv_vwmaccsu_tum(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,31); +} + + +vint64m2_t test___riscv_vwmaccsu_tum(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,31); +} + + +vint64m4_t test___riscv_vwmaccsu_tum(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,31); +} + + +vint64m8_t test___riscv_vwmaccsu_tum(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tum-3.C new file mode 100644 index 00000000000..fd6fc26515b --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tum-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmaccsu_tum(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,32); +} + + +vint16mf2_t test___riscv_vwmaccsu_tum(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,32); +} + + +vint16m1_t test___riscv_vwmaccsu_tum(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,32); +} + + +vint16m2_t test___riscv_vwmaccsu_tum(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,32); +} + + +vint16m4_t test___riscv_vwmaccsu_tum(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,32); +} + + +vint16m8_t test___riscv_vwmaccsu_tum(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,32); +} + + +vint32mf2_t test___riscv_vwmaccsu_tum(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,32); +} + + +vint32m1_t test___riscv_vwmaccsu_tum(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,32); +} + + +vint32m2_t test___riscv_vwmaccsu_tum(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,32); +} + + +vint32m4_t test___riscv_vwmaccsu_tum(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,32); +} + + +vint32m8_t test___riscv_vwmaccsu_tum(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,32); +} + + +vint64m1_t test___riscv_vwmaccsu_tum(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,32); +} + + +vint64m2_t test___riscv_vwmaccsu_tum(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,32); +} + + +vint64m4_t test___riscv_vwmaccsu_tum(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,32); +} + + +vint64m8_t test___riscv_vwmaccsu_tum(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tum(mask,vd,vs1,vs2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tumu-1.C new file mode 100644 index 00000000000..1aa27dbe36d --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tumu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmaccsu_tumu(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,vl); +} + + +vint16mf2_t test___riscv_vwmaccsu_tumu(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,vl); +} + + +vint16m1_t test___riscv_vwmaccsu_tumu(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,vl); +} + + +vint16m2_t test___riscv_vwmaccsu_tumu(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,vl); +} + + +vint16m4_t test___riscv_vwmaccsu_tumu(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,vl); +} + + +vint16m8_t test___riscv_vwmaccsu_tumu(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,vl); +} + + +vint32mf2_t test___riscv_vwmaccsu_tumu(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,vl); +} + + +vint32m1_t test___riscv_vwmaccsu_tumu(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,vl); +} + + +vint32m2_t test___riscv_vwmaccsu_tumu(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,vl); +} + + +vint32m4_t test___riscv_vwmaccsu_tumu(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,vl); +} + + +vint32m8_t test___riscv_vwmaccsu_tumu(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,vl); +} + + +vint64m1_t test___riscv_vwmaccsu_tumu(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,vl); +} + + +vint64m2_t test___riscv_vwmaccsu_tumu(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,vl); +} + + +vint64m4_t test___riscv_vwmaccsu_tumu(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,vl); +} + + +vint64m8_t test___riscv_vwmaccsu_tumu(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tumu-2.C new file mode 100644 index 00000000000..94d4b3d8776 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tumu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmaccsu_tumu(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,31); +} + + +vint16mf2_t test___riscv_vwmaccsu_tumu(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,31); +} + + +vint16m1_t test___riscv_vwmaccsu_tumu(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,31); +} + + +vint16m2_t test___riscv_vwmaccsu_tumu(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,31); +} + + +vint16m4_t test___riscv_vwmaccsu_tumu(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,31); +} + + +vint16m8_t test___riscv_vwmaccsu_tumu(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,31); +} + + +vint32mf2_t test___riscv_vwmaccsu_tumu(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,31); +} + + +vint32m1_t test___riscv_vwmaccsu_tumu(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,31); +} + + +vint32m2_t test___riscv_vwmaccsu_tumu(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,31); +} + + +vint32m4_t test___riscv_vwmaccsu_tumu(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,31); +} + + +vint32m8_t test___riscv_vwmaccsu_tumu(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,31); +} + + +vint64m1_t test___riscv_vwmaccsu_tumu(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,31); +} + + +vint64m2_t test___riscv_vwmaccsu_tumu(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,31); +} + + +vint64m4_t test___riscv_vwmaccsu_tumu(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,31); +} + + +vint64m8_t test___riscv_vwmaccsu_tumu(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tumu-3.C new file mode 100644 index 00000000000..2f694edeb42 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccsu_vv_tumu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmaccsu_tumu(vbool64_t mask,vint16mf4_t vd,vint8mf8_t vs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,32); +} + + +vint16mf2_t test___riscv_vwmaccsu_tumu(vbool32_t mask,vint16mf2_t vd,vint8mf4_t vs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,32); +} + + +vint16m1_t test___riscv_vwmaccsu_tumu(vbool16_t mask,vint16m1_t vd,vint8mf2_t vs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,32); +} + + +vint16m2_t test___riscv_vwmaccsu_tumu(vbool8_t mask,vint16m2_t vd,vint8m1_t vs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,32); +} + + +vint16m4_t test___riscv_vwmaccsu_tumu(vbool4_t mask,vint16m4_t vd,vint8m2_t vs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,32); +} + + +vint16m8_t test___riscv_vwmaccsu_tumu(vbool2_t mask,vint16m8_t vd,vint8m4_t vs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,32); +} + + +vint32mf2_t test___riscv_vwmaccsu_tumu(vbool64_t mask,vint32mf2_t vd,vint16mf4_t vs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,32); +} + + +vint32m1_t test___riscv_vwmaccsu_tumu(vbool32_t mask,vint32m1_t vd,vint16mf2_t vs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,32); +} + + +vint32m2_t test___riscv_vwmaccsu_tumu(vbool16_t mask,vint32m2_t vd,vint16m1_t vs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,32); +} + + +vint32m4_t test___riscv_vwmaccsu_tumu(vbool8_t mask,vint32m4_t vd,vint16m2_t vs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,32); +} + + +vint32m8_t test___riscv_vwmaccsu_tumu(vbool4_t mask,vint32m8_t vd,vint16m4_t vs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,32); +} + + +vint64m1_t test___riscv_vwmaccsu_tumu(vbool64_t mask,vint64m1_t vd,vint32mf2_t vs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,32); +} + + +vint64m2_t test___riscv_vwmaccsu_tumu(vbool32_t mask,vint64m2_t vd,vint32m1_t vs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,32); +} + + +vint64m4_t test___riscv_vwmaccsu_tumu(vbool16_t mask,vint64m4_t vd,vint32m2_t vs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,32); +} + + +vint64m8_t test___riscv_vwmaccsu_tumu(vbool8_t mask,vint64m8_t vd,vint32m4_t vs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccsu_tumu(mask,vd,vs1,vs2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmaccsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv-1.C new file mode 100644 index 00000000000..b2c49896513 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv-1.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmaccu(vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccu(vd,vs1,vs2,vl); +} + + +vuint16mf2_t test___riscv_vwmaccu(vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu(vd,vs1,vs2,vl); +} + + +vuint16m1_t test___riscv_vwmaccu(vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu(vd,vs1,vs2,vl); +} + + +vuint16m2_t test___riscv_vwmaccu(vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu(vd,vs1,vs2,vl); +} + + +vuint16m4_t test___riscv_vwmaccu(vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu(vd,vs1,vs2,vl); +} + + +vuint16m8_t test___riscv_vwmaccu(vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu(vd,vs1,vs2,vl); +} + + +vuint32mf2_t test___riscv_vwmaccu(vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu(vd,vs1,vs2,vl); +} + + +vuint32m1_t test___riscv_vwmaccu(vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu(vd,vs1,vs2,vl); +} + + +vuint32m2_t test___riscv_vwmaccu(vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu(vd,vs1,vs2,vl); +} + + +vuint32m4_t test___riscv_vwmaccu(vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu(vd,vs1,vs2,vl); +} + + +vuint32m8_t test___riscv_vwmaccu(vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu(vd,vs1,vs2,vl); +} + + +vuint64m1_t test___riscv_vwmaccu(vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu(vd,vs1,vs2,vl); +} + + +vuint64m2_t test___riscv_vwmaccu(vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu(vd,vs1,vs2,vl); +} + + +vuint64m4_t test___riscv_vwmaccu(vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu(vd,vs1,vs2,vl); +} + + +vuint64m8_t test___riscv_vwmaccu(vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu(vd,vs1,vs2,vl); +} + + +vuint16mf4_t test___riscv_vwmaccu(vbool64_t mask,vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccu(mask,vd,vs1,vs2,vl); +} + + +vuint16mf2_t test___riscv_vwmaccu(vbool32_t mask,vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu(mask,vd,vs1,vs2,vl); +} + + +vuint16m1_t test___riscv_vwmaccu(vbool16_t mask,vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu(mask,vd,vs1,vs2,vl); +} + + +vuint16m2_t test___riscv_vwmaccu(vbool8_t mask,vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu(mask,vd,vs1,vs2,vl); +} + + +vuint16m4_t test___riscv_vwmaccu(vbool4_t mask,vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu(mask,vd,vs1,vs2,vl); +} + + +vuint16m8_t test___riscv_vwmaccu(vbool2_t mask,vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu(mask,vd,vs1,vs2,vl); +} + + +vuint32mf2_t test___riscv_vwmaccu(vbool64_t mask,vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu(mask,vd,vs1,vs2,vl); +} + + +vuint32m1_t test___riscv_vwmaccu(vbool32_t mask,vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu(mask,vd,vs1,vs2,vl); +} + + +vuint32m2_t test___riscv_vwmaccu(vbool16_t mask,vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu(mask,vd,vs1,vs2,vl); +} + + +vuint32m4_t test___riscv_vwmaccu(vbool8_t mask,vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu(mask,vd,vs1,vs2,vl); +} + + +vuint32m8_t test___riscv_vwmaccu(vbool4_t mask,vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu(mask,vd,vs1,vs2,vl); +} + + +vuint64m1_t test___riscv_vwmaccu(vbool64_t mask,vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu(mask,vd,vs1,vs2,vl); +} + + +vuint64m2_t test___riscv_vwmaccu(vbool32_t mask,vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu(mask,vd,vs1,vs2,vl); +} + + +vuint64m4_t test___riscv_vwmaccu(vbool16_t mask,vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu(mask,vd,vs1,vs2,vl); +} + + +vuint64m8_t test___riscv_vwmaccu(vbool8_t mask,vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu(mask,vd,vs1,vs2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv-2.C new file mode 100644 index 00000000000..c9f3e7ed08b --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv-2.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmaccu(vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccu(vd,vs1,vs2,31); +} + + +vuint16mf2_t test___riscv_vwmaccu(vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu(vd,vs1,vs2,31); +} + + +vuint16m1_t test___riscv_vwmaccu(vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu(vd,vs1,vs2,31); +} + + +vuint16m2_t test___riscv_vwmaccu(vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu(vd,vs1,vs2,31); +} + + +vuint16m4_t test___riscv_vwmaccu(vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu(vd,vs1,vs2,31); +} + + +vuint16m8_t test___riscv_vwmaccu(vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu(vd,vs1,vs2,31); +} + + +vuint32mf2_t test___riscv_vwmaccu(vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu(vd,vs1,vs2,31); +} + + +vuint32m1_t test___riscv_vwmaccu(vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu(vd,vs1,vs2,31); +} + + +vuint32m2_t test___riscv_vwmaccu(vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu(vd,vs1,vs2,31); +} + + +vuint32m4_t test___riscv_vwmaccu(vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu(vd,vs1,vs2,31); +} + + +vuint32m8_t test___riscv_vwmaccu(vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu(vd,vs1,vs2,31); +} + + +vuint64m1_t test___riscv_vwmaccu(vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu(vd,vs1,vs2,31); +} + + +vuint64m2_t test___riscv_vwmaccu(vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu(vd,vs1,vs2,31); +} + + +vuint64m4_t test___riscv_vwmaccu(vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu(vd,vs1,vs2,31); +} + + +vuint64m8_t test___riscv_vwmaccu(vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu(vd,vs1,vs2,31); +} + + +vuint16mf4_t test___riscv_vwmaccu(vbool64_t mask,vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccu(mask,vd,vs1,vs2,31); +} + + +vuint16mf2_t test___riscv_vwmaccu(vbool32_t mask,vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu(mask,vd,vs1,vs2,31); +} + + +vuint16m1_t test___riscv_vwmaccu(vbool16_t mask,vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu(mask,vd,vs1,vs2,31); +} + + +vuint16m2_t test___riscv_vwmaccu(vbool8_t mask,vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu(mask,vd,vs1,vs2,31); +} + + +vuint16m4_t test___riscv_vwmaccu(vbool4_t mask,vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu(mask,vd,vs1,vs2,31); +} + + +vuint16m8_t test___riscv_vwmaccu(vbool2_t mask,vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu(mask,vd,vs1,vs2,31); +} + + +vuint32mf2_t test___riscv_vwmaccu(vbool64_t mask,vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu(mask,vd,vs1,vs2,31); +} + + +vuint32m1_t test___riscv_vwmaccu(vbool32_t mask,vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu(mask,vd,vs1,vs2,31); +} + + +vuint32m2_t test___riscv_vwmaccu(vbool16_t mask,vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu(mask,vd,vs1,vs2,31); +} + + +vuint32m4_t test___riscv_vwmaccu(vbool8_t mask,vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu(mask,vd,vs1,vs2,31); +} + + +vuint32m8_t test___riscv_vwmaccu(vbool4_t mask,vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu(mask,vd,vs1,vs2,31); +} + + +vuint64m1_t test___riscv_vwmaccu(vbool64_t mask,vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu(mask,vd,vs1,vs2,31); +} + + +vuint64m2_t test___riscv_vwmaccu(vbool32_t mask,vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu(mask,vd,vs1,vs2,31); +} + + +vuint64m4_t test___riscv_vwmaccu(vbool16_t mask,vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu(mask,vd,vs1,vs2,31); +} + + +vuint64m8_t test___riscv_vwmaccu(vbool8_t mask,vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu(mask,vd,vs1,vs2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv-3.C new file mode 100644 index 00000000000..210311dca50 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv-3.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmaccu(vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccu(vd,vs1,vs2,32); +} + + +vuint16mf2_t test___riscv_vwmaccu(vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu(vd,vs1,vs2,32); +} + + +vuint16m1_t test___riscv_vwmaccu(vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu(vd,vs1,vs2,32); +} + + +vuint16m2_t test___riscv_vwmaccu(vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu(vd,vs1,vs2,32); +} + + +vuint16m4_t test___riscv_vwmaccu(vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu(vd,vs1,vs2,32); +} + + +vuint16m8_t test___riscv_vwmaccu(vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu(vd,vs1,vs2,32); +} + + +vuint32mf2_t test___riscv_vwmaccu(vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu(vd,vs1,vs2,32); +} + + +vuint32m1_t test___riscv_vwmaccu(vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu(vd,vs1,vs2,32); +} + + +vuint32m2_t test___riscv_vwmaccu(vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu(vd,vs1,vs2,32); +} + + +vuint32m4_t test___riscv_vwmaccu(vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu(vd,vs1,vs2,32); +} + + +vuint32m8_t test___riscv_vwmaccu(vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu(vd,vs1,vs2,32); +} + + +vuint64m1_t test___riscv_vwmaccu(vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu(vd,vs1,vs2,32); +} + + +vuint64m2_t test___riscv_vwmaccu(vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu(vd,vs1,vs2,32); +} + + +vuint64m4_t test___riscv_vwmaccu(vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu(vd,vs1,vs2,32); +} + + +vuint64m8_t test___riscv_vwmaccu(vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu(vd,vs1,vs2,32); +} + + +vuint16mf4_t test___riscv_vwmaccu(vbool64_t mask,vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccu(mask,vd,vs1,vs2,32); +} + + +vuint16mf2_t test___riscv_vwmaccu(vbool32_t mask,vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu(mask,vd,vs1,vs2,32); +} + + +vuint16m1_t test___riscv_vwmaccu(vbool16_t mask,vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu(mask,vd,vs1,vs2,32); +} + + +vuint16m2_t test___riscv_vwmaccu(vbool8_t mask,vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu(mask,vd,vs1,vs2,32); +} + + +vuint16m4_t test___riscv_vwmaccu(vbool4_t mask,vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu(mask,vd,vs1,vs2,32); +} + + +vuint16m8_t test___riscv_vwmaccu(vbool2_t mask,vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu(mask,vd,vs1,vs2,32); +} + + +vuint32mf2_t test___riscv_vwmaccu(vbool64_t mask,vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu(mask,vd,vs1,vs2,32); +} + + +vuint32m1_t test___riscv_vwmaccu(vbool32_t mask,vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu(mask,vd,vs1,vs2,32); +} + + +vuint32m2_t test___riscv_vwmaccu(vbool16_t mask,vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu(mask,vd,vs1,vs2,32); +} + + +vuint32m4_t test___riscv_vwmaccu(vbool8_t mask,vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu(mask,vd,vs1,vs2,32); +} + + +vuint32m8_t test___riscv_vwmaccu(vbool4_t mask,vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu(mask,vd,vs1,vs2,32); +} + + +vuint64m1_t test___riscv_vwmaccu(vbool64_t mask,vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu(mask,vd,vs1,vs2,32); +} + + +vuint64m2_t test___riscv_vwmaccu(vbool32_t mask,vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu(mask,vd,vs1,vs2,32); +} + + +vuint64m4_t test___riscv_vwmaccu(vbool16_t mask,vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu(mask,vd,vs1,vs2,32); +} + + +vuint64m8_t test___riscv_vwmaccu(vbool8_t mask,vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu(mask,vd,vs1,vs2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_mu-1.C new file mode 100644 index 00000000000..a77d935e1fc --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_mu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmaccu_mu(vbool64_t mask,vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,vl); +} + + +vuint16mf2_t test___riscv_vwmaccu_mu(vbool32_t mask,vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,vl); +} + + +vuint16m1_t test___riscv_vwmaccu_mu(vbool16_t mask,vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,vl); +} + + +vuint16m2_t test___riscv_vwmaccu_mu(vbool8_t mask,vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,vl); +} + + +vuint16m4_t test___riscv_vwmaccu_mu(vbool4_t mask,vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,vl); +} + + +vuint16m8_t test___riscv_vwmaccu_mu(vbool2_t mask,vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,vl); +} + + +vuint32mf2_t test___riscv_vwmaccu_mu(vbool64_t mask,vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,vl); +} + + +vuint32m1_t test___riscv_vwmaccu_mu(vbool32_t mask,vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,vl); +} + + +vuint32m2_t test___riscv_vwmaccu_mu(vbool16_t mask,vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,vl); +} + + +vuint32m4_t test___riscv_vwmaccu_mu(vbool8_t mask,vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,vl); +} + + +vuint32m8_t test___riscv_vwmaccu_mu(vbool4_t mask,vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,vl); +} + + +vuint64m1_t test___riscv_vwmaccu_mu(vbool64_t mask,vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,vl); +} + + +vuint64m2_t test___riscv_vwmaccu_mu(vbool32_t mask,vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,vl); +} + + +vuint64m4_t test___riscv_vwmaccu_mu(vbool16_t mask,vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,vl); +} + + +vuint64m8_t test___riscv_vwmaccu_mu(vbool8_t mask,vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_mu-2.C new file mode 100644 index 00000000000..b2c4a795688 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_mu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmaccu_mu(vbool64_t mask,vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,31); +} + + +vuint16mf2_t test___riscv_vwmaccu_mu(vbool32_t mask,vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,31); +} + + +vuint16m1_t test___riscv_vwmaccu_mu(vbool16_t mask,vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,31); +} + + +vuint16m2_t test___riscv_vwmaccu_mu(vbool8_t mask,vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,31); +} + + +vuint16m4_t test___riscv_vwmaccu_mu(vbool4_t mask,vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,31); +} + + +vuint16m8_t test___riscv_vwmaccu_mu(vbool2_t mask,vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,31); +} + + +vuint32mf2_t test___riscv_vwmaccu_mu(vbool64_t mask,vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,31); +} + + +vuint32m1_t test___riscv_vwmaccu_mu(vbool32_t mask,vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,31); +} + + +vuint32m2_t test___riscv_vwmaccu_mu(vbool16_t mask,vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,31); +} + + +vuint32m4_t test___riscv_vwmaccu_mu(vbool8_t mask,vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,31); +} + + +vuint32m8_t test___riscv_vwmaccu_mu(vbool4_t mask,vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,31); +} + + +vuint64m1_t test___riscv_vwmaccu_mu(vbool64_t mask,vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,31); +} + + +vuint64m2_t test___riscv_vwmaccu_mu(vbool32_t mask,vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,31); +} + + +vuint64m4_t test___riscv_vwmaccu_mu(vbool16_t mask,vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,31); +} + + +vuint64m8_t test___riscv_vwmaccu_mu(vbool8_t mask,vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_mu-3.C new file mode 100644 index 00000000000..47bf138422f --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_mu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmaccu_mu(vbool64_t mask,vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,32); +} + + +vuint16mf2_t test___riscv_vwmaccu_mu(vbool32_t mask,vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,32); +} + + +vuint16m1_t test___riscv_vwmaccu_mu(vbool16_t mask,vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,32); +} + + +vuint16m2_t test___riscv_vwmaccu_mu(vbool8_t mask,vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,32); +} + + +vuint16m4_t test___riscv_vwmaccu_mu(vbool4_t mask,vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,32); +} + + +vuint16m8_t test___riscv_vwmaccu_mu(vbool2_t mask,vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,32); +} + + +vuint32mf2_t test___riscv_vwmaccu_mu(vbool64_t mask,vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,32); +} + + +vuint32m1_t test___riscv_vwmaccu_mu(vbool32_t mask,vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,32); +} + + +vuint32m2_t test___riscv_vwmaccu_mu(vbool16_t mask,vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,32); +} + + +vuint32m4_t test___riscv_vwmaccu_mu(vbool8_t mask,vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,32); +} + + +vuint32m8_t test___riscv_vwmaccu_mu(vbool4_t mask,vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,32); +} + + +vuint64m1_t test___riscv_vwmaccu_mu(vbool64_t mask,vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,32); +} + + +vuint64m2_t test___riscv_vwmaccu_mu(vbool32_t mask,vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,32); +} + + +vuint64m4_t test___riscv_vwmaccu_mu(vbool16_t mask,vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,32); +} + + +vuint64m8_t test___riscv_vwmaccu_mu(vbool8_t mask,vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_mu(mask,vd,vs1,vs2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tu-1.C new file mode 100644 index 00000000000..9470b52fd8a --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmaccu_tu(vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tu(vd,vs1,vs2,vl); +} + + +vuint16mf2_t test___riscv_vwmaccu_tu(vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tu(vd,vs1,vs2,vl); +} + + +vuint16m1_t test___riscv_vwmaccu_tu(vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tu(vd,vs1,vs2,vl); +} + + +vuint16m2_t test___riscv_vwmaccu_tu(vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tu(vd,vs1,vs2,vl); +} + + +vuint16m4_t test___riscv_vwmaccu_tu(vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tu(vd,vs1,vs2,vl); +} + + +vuint16m8_t test___riscv_vwmaccu_tu(vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tu(vd,vs1,vs2,vl); +} + + +vuint32mf2_t test___riscv_vwmaccu_tu(vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tu(vd,vs1,vs2,vl); +} + + +vuint32m1_t test___riscv_vwmaccu_tu(vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tu(vd,vs1,vs2,vl); +} + + +vuint32m2_t test___riscv_vwmaccu_tu(vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tu(vd,vs1,vs2,vl); +} + + +vuint32m4_t test___riscv_vwmaccu_tu(vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tu(vd,vs1,vs2,vl); +} + + +vuint32m8_t test___riscv_vwmaccu_tu(vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tu(vd,vs1,vs2,vl); +} + + +vuint64m1_t test___riscv_vwmaccu_tu(vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tu(vd,vs1,vs2,vl); +} + + +vuint64m2_t test___riscv_vwmaccu_tu(vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tu(vd,vs1,vs2,vl); +} + + +vuint64m4_t test___riscv_vwmaccu_tu(vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tu(vd,vs1,vs2,vl); +} + + +vuint64m8_t test___riscv_vwmaccu_tu(vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tu(vd,vs1,vs2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tu-2.C new file mode 100644 index 00000000000..dacab0af322 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmaccu_tu(vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tu(vd,vs1,vs2,31); +} + + +vuint16mf2_t test___riscv_vwmaccu_tu(vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tu(vd,vs1,vs2,31); +} + + +vuint16m1_t test___riscv_vwmaccu_tu(vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tu(vd,vs1,vs2,31); +} + + +vuint16m2_t test___riscv_vwmaccu_tu(vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tu(vd,vs1,vs2,31); +} + + +vuint16m4_t test___riscv_vwmaccu_tu(vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tu(vd,vs1,vs2,31); +} + + +vuint16m8_t test___riscv_vwmaccu_tu(vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tu(vd,vs1,vs2,31); +} + + +vuint32mf2_t test___riscv_vwmaccu_tu(vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tu(vd,vs1,vs2,31); +} + + +vuint32m1_t test___riscv_vwmaccu_tu(vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tu(vd,vs1,vs2,31); +} + + +vuint32m2_t test___riscv_vwmaccu_tu(vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tu(vd,vs1,vs2,31); +} + + +vuint32m4_t test___riscv_vwmaccu_tu(vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tu(vd,vs1,vs2,31); +} + + +vuint32m8_t test___riscv_vwmaccu_tu(vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tu(vd,vs1,vs2,31); +} + + +vuint64m1_t test___riscv_vwmaccu_tu(vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tu(vd,vs1,vs2,31); +} + + +vuint64m2_t test___riscv_vwmaccu_tu(vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tu(vd,vs1,vs2,31); +} + + +vuint64m4_t test___riscv_vwmaccu_tu(vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tu(vd,vs1,vs2,31); +} + + +vuint64m8_t test___riscv_vwmaccu_tu(vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tu(vd,vs1,vs2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tu-3.C new file mode 100644 index 00000000000..d31989fe726 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmaccu_tu(vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tu(vd,vs1,vs2,32); +} + + +vuint16mf2_t test___riscv_vwmaccu_tu(vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tu(vd,vs1,vs2,32); +} + + +vuint16m1_t test___riscv_vwmaccu_tu(vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tu(vd,vs1,vs2,32); +} + + +vuint16m2_t test___riscv_vwmaccu_tu(vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tu(vd,vs1,vs2,32); +} + + +vuint16m4_t test___riscv_vwmaccu_tu(vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tu(vd,vs1,vs2,32); +} + + +vuint16m8_t test___riscv_vwmaccu_tu(vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tu(vd,vs1,vs2,32); +} + + +vuint32mf2_t test___riscv_vwmaccu_tu(vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tu(vd,vs1,vs2,32); +} + + +vuint32m1_t test___riscv_vwmaccu_tu(vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tu(vd,vs1,vs2,32); +} + + +vuint32m2_t test___riscv_vwmaccu_tu(vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tu(vd,vs1,vs2,32); +} + + +vuint32m4_t test___riscv_vwmaccu_tu(vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tu(vd,vs1,vs2,32); +} + + +vuint32m8_t test___riscv_vwmaccu_tu(vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tu(vd,vs1,vs2,32); +} + + +vuint64m1_t test___riscv_vwmaccu_tu(vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tu(vd,vs1,vs2,32); +} + + +vuint64m2_t test___riscv_vwmaccu_tu(vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tu(vd,vs1,vs2,32); +} + + +vuint64m4_t test___riscv_vwmaccu_tu(vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tu(vd,vs1,vs2,32); +} + + +vuint64m8_t test___riscv_vwmaccu_tu(vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tu(vd,vs1,vs2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tum-1.C new file mode 100644 index 00000000000..515c6d8e31f --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tum-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmaccu_tum(vbool64_t mask,vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,vl); +} + + +vuint16mf2_t test___riscv_vwmaccu_tum(vbool32_t mask,vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,vl); +} + + +vuint16m1_t test___riscv_vwmaccu_tum(vbool16_t mask,vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,vl); +} + + +vuint16m2_t test___riscv_vwmaccu_tum(vbool8_t mask,vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,vl); +} + + +vuint16m4_t test___riscv_vwmaccu_tum(vbool4_t mask,vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,vl); +} + + +vuint16m8_t test___riscv_vwmaccu_tum(vbool2_t mask,vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,vl); +} + + +vuint32mf2_t test___riscv_vwmaccu_tum(vbool64_t mask,vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,vl); +} + + +vuint32m1_t test___riscv_vwmaccu_tum(vbool32_t mask,vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,vl); +} + + +vuint32m2_t test___riscv_vwmaccu_tum(vbool16_t mask,vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,vl); +} + + +vuint32m4_t test___riscv_vwmaccu_tum(vbool8_t mask,vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,vl); +} + + +vuint32m8_t test___riscv_vwmaccu_tum(vbool4_t mask,vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,vl); +} + + +vuint64m1_t test___riscv_vwmaccu_tum(vbool64_t mask,vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,vl); +} + + +vuint64m2_t test___riscv_vwmaccu_tum(vbool32_t mask,vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,vl); +} + + +vuint64m4_t test___riscv_vwmaccu_tum(vbool16_t mask,vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,vl); +} + + +vuint64m8_t test___riscv_vwmaccu_tum(vbool8_t mask,vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tum-2.C new file mode 100644 index 00000000000..1aa0b331367 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tum-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmaccu_tum(vbool64_t mask,vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,31); +} + + +vuint16mf2_t test___riscv_vwmaccu_tum(vbool32_t mask,vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,31); +} + + +vuint16m1_t test___riscv_vwmaccu_tum(vbool16_t mask,vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,31); +} + + +vuint16m2_t test___riscv_vwmaccu_tum(vbool8_t mask,vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,31); +} + + +vuint16m4_t test___riscv_vwmaccu_tum(vbool4_t mask,vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,31); +} + + +vuint16m8_t test___riscv_vwmaccu_tum(vbool2_t mask,vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,31); +} + + +vuint32mf2_t test___riscv_vwmaccu_tum(vbool64_t mask,vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,31); +} + + +vuint32m1_t test___riscv_vwmaccu_tum(vbool32_t mask,vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,31); +} + + +vuint32m2_t test___riscv_vwmaccu_tum(vbool16_t mask,vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,31); +} + + +vuint32m4_t test___riscv_vwmaccu_tum(vbool8_t mask,vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,31); +} + + +vuint32m8_t test___riscv_vwmaccu_tum(vbool4_t mask,vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,31); +} + + +vuint64m1_t test___riscv_vwmaccu_tum(vbool64_t mask,vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,31); +} + + +vuint64m2_t test___riscv_vwmaccu_tum(vbool32_t mask,vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,31); +} + + +vuint64m4_t test___riscv_vwmaccu_tum(vbool16_t mask,vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,31); +} + + +vuint64m8_t test___riscv_vwmaccu_tum(vbool8_t mask,vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tum-3.C new file mode 100644 index 00000000000..6e2bbdab7df --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tum-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmaccu_tum(vbool64_t mask,vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,32); +} + + +vuint16mf2_t test___riscv_vwmaccu_tum(vbool32_t mask,vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,32); +} + + +vuint16m1_t test___riscv_vwmaccu_tum(vbool16_t mask,vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,32); +} + + +vuint16m2_t test___riscv_vwmaccu_tum(vbool8_t mask,vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,32); +} + + +vuint16m4_t test___riscv_vwmaccu_tum(vbool4_t mask,vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,32); +} + + +vuint16m8_t test___riscv_vwmaccu_tum(vbool2_t mask,vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,32); +} + + +vuint32mf2_t test___riscv_vwmaccu_tum(vbool64_t mask,vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,32); +} + + +vuint32m1_t test___riscv_vwmaccu_tum(vbool32_t mask,vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,32); +} + + +vuint32m2_t test___riscv_vwmaccu_tum(vbool16_t mask,vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,32); +} + + +vuint32m4_t test___riscv_vwmaccu_tum(vbool8_t mask,vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,32); +} + + +vuint32m8_t test___riscv_vwmaccu_tum(vbool4_t mask,vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,32); +} + + +vuint64m1_t test___riscv_vwmaccu_tum(vbool64_t mask,vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,32); +} + + +vuint64m2_t test___riscv_vwmaccu_tum(vbool32_t mask,vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,32); +} + + +vuint64m4_t test___riscv_vwmaccu_tum(vbool16_t mask,vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,32); +} + + +vuint64m8_t test___riscv_vwmaccu_tum(vbool8_t mask,vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tum(mask,vd,vs1,vs2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tumu-1.C new file mode 100644 index 00000000000..39aff25d25d --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tumu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmaccu_tumu(vbool64_t mask,vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,vl); +} + + +vuint16mf2_t test___riscv_vwmaccu_tumu(vbool32_t mask,vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,vl); +} + + +vuint16m1_t test___riscv_vwmaccu_tumu(vbool16_t mask,vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,vl); +} + + +vuint16m2_t test___riscv_vwmaccu_tumu(vbool8_t mask,vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,vl); +} + + +vuint16m4_t test___riscv_vwmaccu_tumu(vbool4_t mask,vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,vl); +} + + +vuint16m8_t test___riscv_vwmaccu_tumu(vbool2_t mask,vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,vl); +} + + +vuint32mf2_t test___riscv_vwmaccu_tumu(vbool64_t mask,vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,vl); +} + + +vuint32m1_t test___riscv_vwmaccu_tumu(vbool32_t mask,vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,vl); +} + + +vuint32m2_t test___riscv_vwmaccu_tumu(vbool16_t mask,vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,vl); +} + + +vuint32m4_t test___riscv_vwmaccu_tumu(vbool8_t mask,vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,vl); +} + + +vuint32m8_t test___riscv_vwmaccu_tumu(vbool4_t mask,vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,vl); +} + + +vuint64m1_t test___riscv_vwmaccu_tumu(vbool64_t mask,vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,vl); +} + + +vuint64m2_t test___riscv_vwmaccu_tumu(vbool32_t mask,vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,vl); +} + + +vuint64m4_t test___riscv_vwmaccu_tumu(vbool16_t mask,vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,vl); +} + + +vuint64m8_t test___riscv_vwmaccu_tumu(vbool8_t mask,vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tumu-2.C new file mode 100644 index 00000000000..2f4176a78f9 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tumu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmaccu_tumu(vbool64_t mask,vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,31); +} + + +vuint16mf2_t test___riscv_vwmaccu_tumu(vbool32_t mask,vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,31); +} + + +vuint16m1_t test___riscv_vwmaccu_tumu(vbool16_t mask,vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,31); +} + + +vuint16m2_t test___riscv_vwmaccu_tumu(vbool8_t mask,vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,31); +} + + +vuint16m4_t test___riscv_vwmaccu_tumu(vbool4_t mask,vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,31); +} + + +vuint16m8_t test___riscv_vwmaccu_tumu(vbool2_t mask,vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,31); +} + + +vuint32mf2_t test___riscv_vwmaccu_tumu(vbool64_t mask,vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,31); +} + + +vuint32m1_t test___riscv_vwmaccu_tumu(vbool32_t mask,vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,31); +} + + +vuint32m2_t test___riscv_vwmaccu_tumu(vbool16_t mask,vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,31); +} + + +vuint32m4_t test___riscv_vwmaccu_tumu(vbool8_t mask,vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,31); +} + + +vuint32m8_t test___riscv_vwmaccu_tumu(vbool4_t mask,vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,31); +} + + +vuint64m1_t test___riscv_vwmaccu_tumu(vbool64_t mask,vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,31); +} + + +vuint64m2_t test___riscv_vwmaccu_tumu(vbool32_t mask,vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,31); +} + + +vuint64m4_t test___riscv_vwmaccu_tumu(vbool16_t mask,vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,31); +} + + +vuint64m8_t test___riscv_vwmaccu_tumu(vbool8_t mask,vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tumu-3.C new file mode 100644 index 00000000000..0fe3dffe1b3 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmaccu_vv_tumu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint16mf4_t test___riscv_vwmaccu_tumu(vbool64_t mask,vuint16mf4_t vd,vuint8mf8_t vs1,vuint8mf8_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,32); +} + + +vuint16mf2_t test___riscv_vwmaccu_tumu(vbool32_t mask,vuint16mf2_t vd,vuint8mf4_t vs1,vuint8mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,32); +} + + +vuint16m1_t test___riscv_vwmaccu_tumu(vbool16_t mask,vuint16m1_t vd,vuint8mf2_t vs1,vuint8mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,32); +} + + +vuint16m2_t test___riscv_vwmaccu_tumu(vbool8_t mask,vuint16m2_t vd,vuint8m1_t vs1,vuint8m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,32); +} + + +vuint16m4_t test___riscv_vwmaccu_tumu(vbool4_t mask,vuint16m4_t vd,vuint8m2_t vs1,vuint8m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,32); +} + + +vuint16m8_t test___riscv_vwmaccu_tumu(vbool2_t mask,vuint16m8_t vd,vuint8m4_t vs1,vuint8m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,32); +} + + +vuint32mf2_t test___riscv_vwmaccu_tumu(vbool64_t mask,vuint32mf2_t vd,vuint16mf4_t vs1,vuint16mf4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,32); +} + + +vuint32m1_t test___riscv_vwmaccu_tumu(vbool32_t mask,vuint32m1_t vd,vuint16mf2_t vs1,vuint16mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,32); +} + + +vuint32m2_t test___riscv_vwmaccu_tumu(vbool16_t mask,vuint32m2_t vd,vuint16m1_t vs1,vuint16m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,32); +} + + +vuint32m4_t test___riscv_vwmaccu_tumu(vbool8_t mask,vuint32m4_t vd,vuint16m2_t vs1,vuint16m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,32); +} + + +vuint32m8_t test___riscv_vwmaccu_tumu(vbool4_t mask,vuint32m8_t vd,vuint16m4_t vs1,vuint16m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,32); +} + + +vuint64m1_t test___riscv_vwmaccu_tumu(vbool64_t mask,vuint64m1_t vd,vuint32mf2_t vs1,vuint32mf2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,32); +} + + +vuint64m2_t test___riscv_vwmaccu_tumu(vbool32_t mask,vuint64m2_t vd,vuint32m1_t vs1,vuint32m1_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,32); +} + + +vuint64m4_t test___riscv_vwmaccu_tumu(vbool16_t mask,vuint64m4_t vd,vuint32m2_t vs1,vuint32m2_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,32); +} + + +vuint64m8_t test___riscv_vwmaccu_tumu(vbool8_t mask,vuint64m8_t vd,vuint32m4_t vs1,vuint32m4_t vs2,size_t vl) +{ + return __riscv_vwmaccu_tumu(mask,vd,vs1,vs2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmaccu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ -- 2.36.3