From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtpbgau2.qq.com (smtpbgau2.qq.com [54.206.34.216]) by sourceware.org (Postfix) with ESMTPS id EB6BB3858D1E for ; Wed, 15 Feb 2023 08:40:03 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org EB6BB3858D1E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp65t1676450396twe6s5ex Received: from rios-cad5.localdomain ( [58.60.1.11]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 15 Feb 2023 16:39:55 +0800 (CST) X-QQ-SSF: 01400000000000E0L000000A0000000 X-QQ-FEAT: niM2FYwlzCHAZZTk56H+pS+Ex+nwSyhh8G5ZSNJAiDxNLy91VfhoWmnGhc+B0 dFBdYCzQWAiLoLJDUaP3i7KASfDigMemZkwOtGUrx8bwlgNoqeBA8LCrxLj/K//t4zlAfX0 rDWvIwYZKnKkymZOGKmLKLveyzRg8zM/iYXgu5cxZX544KJRIJa19QL9q1eR/7/VjeF+ZRc sv35/Z6e2jdYUUo2DoOcAz5yMH07pmokT3f1s6rnoKzQ4B6dyrJeHSX26chFRL6gyzJQreL 1Q8MAQju0O567xUqVxGN9W/hnj3oYayR+2nsHYFDYBzhjyx7nXOkYOLYTJMC0ZrPd3Titxm 04ezeRuiGdj4T54FySQZJMkVurCR+jGKnMf4W/wPXYzMeONLcsrrjjB1+WBtSPkEVFdiRY7 X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, Ju-Zhe Zhong , kito-cheng Subject: [PATCH] RISC-V: Normalize SEW = 64 handling into a simplified function Date: Wed, 15 Feb 2023 16:39:54 +0800 Message-Id: <20230215083954.274514-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-13.0 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Ju-Zhe Zhong Co-authored-by: kito-cheng gcc/ChangeLog: * config/riscv/riscv-protos.h (sew64_scalar_helper): New function. * config/riscv/riscv-v.cc (has_vi_variant_p): Adjust. (sew64_scalar_helper): New function. * config/riscv/vector.md: Normalization. Co-authored-by: kito-cheng --- gcc/config/riscv/riscv-protos.h | 2 + gcc/config/riscv/riscv-v.cc | 46 +- gcc/config/riscv/vector.md | 771 +++++++++++--------------------- 3 files changed, 316 insertions(+), 503 deletions(-) diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 81ad2eabc00..37c634eca1d 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -181,6 +181,8 @@ bool neg_simm5_p (rtx); #ifdef RTX_CODE bool has_vi_variant_p (rtx_code, rtx); #endif +bool sew64_scalar_helper (rtx *, rtx *, rtx, machine_mode, machine_mode, + bool, void (*)(rtx *, rtx)); } /* We classify builtin types into two classes: diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index dd70bf9b541..59c25c65cd5 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -418,14 +418,11 @@ has_vi_variant_p (rtx_code code, rtx x) switch (code) { case PLUS: - case MINUS: case AND: case IOR: case XOR: case SS_PLUS: - case SS_MINUS: case US_PLUS: - case US_MINUS: case EQ: case NE: case LE: @@ -438,10 +435,53 @@ has_vi_variant_p (rtx_code code, rtx x) case LTU: case GE: case GEU: + case MINUS: + case SS_MINUS: return neg_simm5_p (x); + default: return false; } } +bool +sew64_scalar_helper (rtx *operands, rtx *scalar_op, rtx vl, + machine_mode vector_mode, machine_mode mask_mode, + bool has_vi_variant_p, + void (*emit_vector_func) (rtx *, rtx)) +{ + machine_mode scalar_mode = GET_MODE_INNER (vector_mode); + if (has_vi_variant_p) + { + *scalar_op = force_reg (scalar_mode, *scalar_op); + return false; + } + + if (TARGET_64BIT) + { + if (!rtx_equal_p (*scalar_op, const0_rtx)) + *scalar_op = force_reg (scalar_mode, *scalar_op); + return false; + } + + if (immediate_operand (*scalar_op, Pmode)) + { + if (!rtx_equal_p (*scalar_op, const0_rtx)) + *scalar_op = force_reg (Pmode, *scalar_op); + + *scalar_op = gen_rtx_SIGN_EXTEND (scalar_mode, *scalar_op); + return false; + } + + if (CONST_INT_P (*scalar_op)) + *scalar_op = force_reg (scalar_mode, *scalar_op); + + rtx tmp = gen_reg_rtx (vector_mode); + riscv_vector::emit_nonvlmax_op (code_for_pred_broadcast (vector_mode), tmp, + *scalar_op, vl, mask_mode); + emit_vector_func (operands, tmp); + + return true; +} + } // namespace riscv_vector diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 764d9316ad9..c897a365819 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -882,32 +882,21 @@ (match_operand:VI_D 2 "register_operand")) (match_operand:VI_D 1 "vector_merge_operand")))] "TARGET_VECTOR" - { - if (riscv_vector::simm5_p (operands[3])) - operands[3] = force_reg (mode, operands[3]); - else if (!TARGET_64BIT) - { - rtx v = gen_reg_rtx (mode); - - if (immediate_operand (operands[3], Pmode)) - operands[3] = gen_rtx_SIGN_EXTEND (mode, - force_reg (Pmode, operands[3])); - else - { - if (CONST_INT_P (operands[3])) - operands[3] = force_reg (mode, operands[3]); - - riscv_vector::emit_nonvlmax_op (code_for_pred_broadcast (mode), - v, operands[3], operands[5], mode); - emit_insn (gen_pred_merge (operands[0], operands[1], - operands[2], v, operands[4],operands[5], - operands[6], operands[7])); - DONE; - } - } - else - operands[3] = force_reg (mode, operands[3]); - }) +{ + if (riscv_vector::sew64_scalar_helper ( + operands, + /* scalar op */&operands[3], + /* vl */operands[5], + mode, + mode, + riscv_vector::simm5_p (operands[3]), + [] (rtx *operands, rtx boardcast_scalar) { + emit_insn (gen_pred_merge (operands[0], operands[1], + operands[2], boardcast_scalar, operands[4], operands[5], + operands[6], operands[7])); + })) + DONE; +}) (define_insn "*pred_merge_scalar" [(set (match_operand:VI_D 0 "register_operand" "=vd") @@ -1471,38 +1460,21 @@ (match_operand:VI_D 3 "register_operand")) (match_operand:VI_D 2 "vector_merge_operand")))] "TARGET_VECTOR" - { - if (riscv_vector::has_vi_variant_p (, operands[4])) - operands[4] = force_reg (mode, operands[4]); - else if (!TARGET_64BIT) - { - rtx v = gen_reg_rtx (mode); - - if (immediate_operand (operands[4], Pmode)) - { - if (!rtx_equal_p (operands[4], const0_rtx)) - operands[4] = force_reg (Pmode, operands[4]); - operands[4] = gen_rtx_SIGN_EXTEND (mode, operands[4]); - } - else - { - if (CONST_INT_P (operands[4])) - operands[4] = force_reg (mode, operands[4]); - - riscv_vector::emit_nonvlmax_op (code_for_pred_broadcast (mode), - v, operands[4], operands[5], mode); - emit_insn (gen_pred_ (operands[0], operands[1], - operands[2], operands[3], v, operands[5], - operands[6], operands[7], operands[8])); - DONE; - } - } - else - { - if (!rtx_equal_p (operands[4], const0_rtx)) - operands[4] = force_reg (mode, operands[4]); - } - }) +{ + if (riscv_vector::sew64_scalar_helper ( + operands, + /* scalar op */&operands[4], + /* vl */operands[5], + mode, + mode, + riscv_vector::has_vi_variant_p (, operands[4]), + [] (rtx *operands, rtx boardcast_scalar) { + emit_insn (gen_pred_ (operands[0], operands[1], + operands[2], operands[3], boardcast_scalar, operands[5], + operands[6], operands[7], operands[8])); + })) + DONE; +}) (define_insn "*pred__scalar" [(set (match_operand:VI_D 0 "register_operand" "=vd, vr") @@ -1564,38 +1536,21 @@ (match_operand: 4 "reg_or_int_operand"))) (match_operand:VI_D 2 "vector_merge_operand")))] "TARGET_VECTOR" - { - if (riscv_vector::has_vi_variant_p (, operands[4])) - operands[4] = force_reg (mode, operands[4]); - else if (!TARGET_64BIT) - { - rtx v = gen_reg_rtx (mode); - - if (immediate_operand (operands[4], Pmode)) - { - if (!rtx_equal_p (operands[4], const0_rtx)) - operands[4] = force_reg (Pmode, operands[4]); - operands[4] = gen_rtx_SIGN_EXTEND (mode, operands[4]); - } - else - { - if (CONST_INT_P (operands[4])) - operands[4] = force_reg (mode, operands[4]); - - riscv_vector::emit_nonvlmax_op (code_for_pred_broadcast (mode), - v, operands[4], operands[5], mode); - emit_insn (gen_pred_ (operands[0], operands[1], - operands[2], operands[3], v, operands[5], - operands[6], operands[7], operands[8])); - DONE; - } - } - else - { - if (!rtx_equal_p (operands[4], const0_rtx)) - operands[4] = force_reg (mode, operands[4]); - } - }) +{ + if (riscv_vector::sew64_scalar_helper ( + operands, + /* scalar op */&operands[4], + /* vl */operands[5], + mode, + mode, + riscv_vector::has_vi_variant_p (, operands[4]), + [] (rtx *operands, rtx boardcast_scalar) { + emit_insn (gen_pred_ (operands[0], operands[1], + operands[2], operands[3], boardcast_scalar, operands[5], + operands[6], operands[7], operands[8])); + })) + DONE; +}) (define_insn "*pred__scalar" [(set (match_operand:VI_D 0 "register_operand" "=vd, vr") @@ -1657,32 +1612,21 @@ (match_operand:VI_D 3 "register_operand")) (match_operand:VI_D 2 "vector_merge_operand")))] "TARGET_VECTOR" - { - if (riscv_vector::neg_simm5_p (operands[4])) - operands[4] = force_reg (mode, operands[4]); - else if (!TARGET_64BIT) - { - rtx v = gen_reg_rtx (mode); - - if (immediate_operand (operands[4], Pmode)) - operands[4] = gen_rtx_SIGN_EXTEND (mode, - force_reg (Pmode, operands[4])); - else - { - if (CONST_INT_P (operands[4])) - operands[4] = force_reg (mode, operands[4]); - - riscv_vector::emit_nonvlmax_op (code_for_pred_broadcast (mode), - v, operands[4], operands[5], mode); - emit_insn (gen_pred_sub (operands[0], operands[1], - operands[2], operands[3], v, operands[5], - operands[6], operands[7], operands[8])); - DONE; - } - } - else - operands[4] = force_reg (mode, operands[4]); - }) +{ + if (riscv_vector::sew64_scalar_helper ( + operands, + /* scalar op */&operands[4], + /* vl */operands[5], + mode, + mode, + riscv_vector::neg_simm5_p (operands[4]), + [] (rtx *operands, rtx boardcast_scalar) { + emit_insn (gen_pred_sub (operands[0], operands[1], + operands[2], operands[3], boardcast_scalar, operands[5], + operands[6], operands[7], operands[8])); + })) + DONE; +}) (define_insn "*pred_sub_reverse_scalar" [(set (match_operand:VI_D 0 "register_operand" "=vd, vr") @@ -1786,36 +1730,21 @@ (match_operand:VFULLI_D 3 "register_operand")] VMULH) (match_operand:VFULLI_D 2 "vector_merge_operand")))] "TARGET_VECTOR" - { - if (!TARGET_64BIT) - { - rtx v = gen_reg_rtx (mode); - - if (immediate_operand (operands[4], Pmode)) - { - if (!rtx_equal_p (operands[4], const0_rtx)) - operands[4] = force_reg (Pmode, operands[4]); - operands[4] = gen_rtx_SIGN_EXTEND (mode, operands[4]); - } - else - { - if (CONST_INT_P (operands[4])) - operands[4] = force_reg (mode, operands[4]); - - riscv_vector::emit_nonvlmax_op (code_for_pred_broadcast (mode), - v, operands[4], operands[5], mode); - emit_insn (gen_pred_mulh (operands[0], operands[1], - operands[2], operands[3], v, operands[5], - operands[6], operands[7], operands[8])); - DONE; - } - } - else - { - if (!rtx_equal_p (operands[4], const0_rtx)) - operands[4] = force_reg (mode, operands[4]); - } - }) +{ + if (riscv_vector::sew64_scalar_helper ( + operands, + /* scalar op */&operands[4], + /* vl */operands[5], + mode, + mode, + false, + [] (rtx *operands, rtx boardcast_scalar) { + emit_insn (gen_pred_mulh (operands[0], operands[1], + operands[2], operands[3], boardcast_scalar, operands[5], + operands[6], operands[7], operands[8])); + })) + DONE; +}) (define_insn "*pred_mulh_scalar" [(set (match_operand:VFULLI_D 0 "register_operand" "=vd, vr") @@ -1976,33 +1905,21 @@ (match_operand: 4 "register_operand")] UNSPEC_VADC) (match_operand:VI_D 1 "vector_merge_operand")))] "TARGET_VECTOR" - { - if (riscv_vector::simm5_p (operands[3])) - operands[3] = force_reg (mode, operands[3]); - else if (!TARGET_64BIT) - { - rtx v = gen_reg_rtx (mode); - - if (immediate_operand (operands[3], Pmode)) - operands[3] = gen_rtx_SIGN_EXTEND (mode, - force_reg (Pmode, operands[3])); - else - { - if (CONST_INT_P (operands[3])) - operands[3] = force_reg (mode, operands[3]); - - riscv_vector::emit_nonvlmax_op (code_for_pred_broadcast (mode), - v, operands[3], operands[5], - mode); - emit_insn (gen_pred_adc (operands[0], operands[1], operands[2], - v, operands[4], operands[5], - operands[6], operands[7])); - DONE; - } - } - else - operands[3] = force_reg (mode, operands[3]); - }) +{ + if (riscv_vector::sew64_scalar_helper ( + operands, + /* scalar op */&operands[3], + /* vl */operands[5], + mode, + mode, + riscv_vector::simm5_p (operands[3]), + [] (rtx *operands, rtx boardcast_scalar) { + emit_insn (gen_pred_adc (operands[0], operands[1], + operands[2], boardcast_scalar, operands[4], operands[5], + operands[6], operands[7])); + })) + DONE; +}) (define_insn "*pred_adc_scalar" [(set (match_operand:VI_D 0 "register_operand" "=&vr") @@ -2016,12 +1933,12 @@ (unspec:VI_D [(plus:VI_D (vec_duplicate:VI_D - (match_operand: 3 "register_operand" " r")) + (match_operand: 3 "reg_or_0_operand" " rJ")) (match_operand:VI_D 2 "register_operand" " vr")) (match_operand: 4 "register_operand" " vm")] UNSPEC_VADC) (match_operand:VI_D 1 "vector_merge_operand" "0vu")))] "TARGET_VECTOR" - "vadc.vxm\t%0,%2,%3,%4" + "vadc.vxm\t%0,%2,%z3,%4" [(set_attr "type" "vicalu") (set_attr "mode" "") (set_attr "merge_op_idx" "1") @@ -2042,12 +1959,12 @@ [(plus:VI_D (vec_duplicate:VI_D (sign_extend: - (match_operand: 3 "register_operand" " r"))) + (match_operand: 3 "reg_or_0_operand" " rJ"))) (match_operand:VI_D 2 "register_operand" " vr")) (match_operand: 4 "register_operand" " vm")] UNSPEC_VADC) (match_operand:VI_D 1 "vector_merge_operand" "0vu")))] "TARGET_VECTOR" - "vadc.vxm\t%0,%2,%3,%4" + "vadc.vxm\t%0,%2,%z3,%4" [(set_attr "type" "vicalu") (set_attr "mode" "") (set_attr "merge_op_idx" "1") @@ -2072,37 +1989,21 @@ (match_operand: 4 "register_operand")] UNSPEC_VSBC) (match_operand:VI_D 1 "vector_merge_operand")))] "TARGET_VECTOR" - { - if (!TARGET_64BIT) - { - rtx v = gen_reg_rtx (mode); - - if (immediate_operand (operands[3], Pmode)) - { - if (!rtx_equal_p (operands[3], const0_rtx)) - operands[3] = force_reg (Pmode, operands[3]); - operands[3] = gen_rtx_SIGN_EXTEND (mode, operands[3]); - } - else - { - if (CONST_INT_P (operands[3])) - operands[3] = force_reg (mode, operands[3]); - - riscv_vector::emit_nonvlmax_op (code_for_pred_broadcast (mode), - v, operands[3], operands[5], - mode); - emit_insn (gen_pred_sbc (operands[0], operands[1], operands[2], - v, operands[4], operands[5], - operands[6], operands[7])); - DONE; - } - } - else - { - if (!rtx_equal_p (operands[3], const0_rtx)) - operands[3] = force_reg (mode, operands[3]); - } - }) +{ + if (riscv_vector::sew64_scalar_helper ( + operands, + /* scalar op */&operands[3], + /* vl */operands[5], + mode, + mode, + false, + [] (rtx *operands, rtx boardcast_scalar) { + emit_insn (gen_pred_sbc (operands[0], operands[1], + operands[2], boardcast_scalar, operands[4], operands[5], + operands[6], operands[7])); + })) + DONE; +}) (define_insn "*pred_sbc_scalar" [(set (match_operand:VI_D 0 "register_operand" "=&vr") @@ -2247,39 +2148,27 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMADC))] "TARGET_VECTOR" - { - if (riscv_vector::simm5_p (operands[2])) - operands[2] = force_reg (mode, operands[2]); - else if (!TARGET_64BIT) - { - rtx v = gen_reg_rtx (mode); - - if (immediate_operand (operands[2], Pmode)) - operands[2] = gen_rtx_SIGN_EXTEND (mode, - force_reg (Pmode, operands[2])); - else - { - if (CONST_INT_P (operands[2])) - operands[2] = force_reg (mode, operands[2]); - - riscv_vector::emit_nonvlmax_op (code_for_pred_broadcast (mode), - v, operands[2], operands[5], - mode); - emit_insn (gen_pred_madc (operands[0], operands[1], v, operands[3], - operands[4], operands[5])); - DONE; - } - } - else - operands[2] = force_reg (mode, operands[2]); - }) +{ + if (riscv_vector::sew64_scalar_helper ( + operands, + /* scalar op */&operands[2], + /* vl */operands[4], + mode, + mode, + riscv_vector::simm5_p (operands[2]), + [] (rtx *operands, rtx boardcast_scalar) { + emit_insn (gen_pred_madc (operands[0], operands[1], + boardcast_scalar, operands[3], operands[4], operands[5])); + })) + DONE; +}) (define_insn "*pred_madc_scalar" [(set (match_operand: 0 "register_operand" "=&vr") (unspec: [(plus:VI_D (vec_duplicate:VI_D - (match_operand: 2 "register_operand" " r")) + (match_operand: 2 "reg_or_0_operand" " rJ")) (match_operand:VI_D 1 "register_operand" " vr")) (match_operand: 3 "register_operand" " vm") (unspec: @@ -2288,7 +2177,7 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMADC))] "TARGET_VECTOR" - "vmadc.vxm\t%0,%1,%2,%3" + "vmadc.vxm\t%0,%1,%z2,%3" [(set_attr "type" "vicalu") (set_attr "mode" "") (set_attr "vl_op_idx" "4") @@ -2300,7 +2189,7 @@ [(plus:VI_D (vec_duplicate:VI_D (sign_extend: - (match_operand: 2 "register_operand" " r"))) + (match_operand: 2 "reg_or_0_operand" " rJ"))) (match_operand:VI_D 1 "register_operand" " vr")) (match_operand: 3 "register_operand" " vm") (unspec: @@ -2309,7 +2198,7 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMADC))] "TARGET_VECTOR" - "vmadc.vxm\t%0,%1,%2,%3" + "vmadc.vxm\t%0,%1,%z2,%3" [(set_attr "type" "vicalu") (set_attr "mode" "") (set_attr "vl_op_idx" "4") @@ -2329,36 +2218,20 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_VMSBC))] "TARGET_VECTOR" - { - if (!TARGET_64BIT) - { - rtx v = gen_reg_rtx (mode); - - if (immediate_operand (operands[2], Pmode)) - { - if (!rtx_equal_p (operands[2], const0_rtx)) - operands[2] = force_reg (Pmode, operands[2]); - operands[2] = gen_rtx_SIGN_EXTEND (mode, operands[2]); - } - else - { - if (CONST_INT_P (operands[2])) - operands[2] = force_reg (mode, operands[2]); - - riscv_vector::emit_nonvlmax_op (code_for_pred_broadcast (mode), - v, operands[2], operands[5], - mode); - emit_insn (gen_pred_msbc (operands[0], operands[1], v, operands[3], - operands[4], operands[5])); - DONE; - } - } - else - { - if (!rtx_equal_p (operands[2], const0_rtx)) - operands[2] = force_reg (mode, operands[2]); - } - }) +{ + if (riscv_vector::sew64_scalar_helper ( + operands, + /* scalar op */&operands[2], + /* vl */operands[4], + mode, + mode, + false, + [] (rtx *operands, rtx boardcast_scalar) { + emit_insn (gen_pred_msbc (operands[0], operands[1], + boardcast_scalar, operands[3], operands[4], operands[5])); + })) + DONE; +}) (define_insn "*pred_msbc_scalar" [(set (match_operand: 0 "register_operand" "=&vr") @@ -2442,7 +2315,7 @@ (unspec: [(plus:VI_QHS (vec_duplicate:VI_QHS - (match_operand: 2 "register_operand" " r")) + (match_operand: 2 "reg_or_0_operand" " rJ")) (match_operand:VI_QHS 1 "register_operand" " vr")) (unspec: [(match_operand 3 "vector_length_operand" " rK") @@ -2450,7 +2323,7 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))] "TARGET_VECTOR" - "vmadc.vx\t%0,%1,%2" + "vmadc.vx\t%0,%1,%z2" [(set_attr "type" "vicalu") (set_attr "mode" "") (set_attr "vl_op_idx" "3") @@ -2488,39 +2361,27 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))] "TARGET_VECTOR" - { - if (riscv_vector::simm5_p (operands[2])) - operands[2] = force_reg (mode, operands[2]); - else if (!TARGET_64BIT) - { - rtx v = gen_reg_rtx (mode); - - if (immediate_operand (operands[2], Pmode)) - operands[2] = gen_rtx_SIGN_EXTEND (mode, - force_reg (Pmode, operands[2])); - else - { - if (CONST_INT_P (operands[2])) - operands[2] = force_reg (mode, operands[2]); - - riscv_vector::emit_nonvlmax_op (code_for_pred_broadcast (mode), - v, operands[2], operands[3], - mode); - emit_insn (gen_pred_madc_overflow (operands[0], operands[1], - v, operands[3], operands[4])); - DONE; - } - } - else - operands[2] = force_reg (mode, operands[2]); - }) +{ + if (riscv_vector::sew64_scalar_helper ( + operands, + /* scalar op */&operands[2], + /* vl */operands[3], + mode, + mode, + riscv_vector::simm5_p (operands[2]), + [] (rtx *operands, rtx boardcast_scalar) { + emit_insn (gen_pred_madc_overflow (operands[0], operands[1], + boardcast_scalar, operands[3], operands[4])); + })) + DONE; +}) (define_insn "*pred_madc_overflow_scalar" [(set (match_operand: 0 "register_operand" "=&vr") (unspec: [(plus:VI_D (vec_duplicate:VI_D - (match_operand: 2 "register_operand" " r")) + (match_operand: 2 "reg_or_0_operand" " rJ")) (match_operand:VI_D 1 "register_operand" " vr")) (unspec: [(match_operand 3 "vector_length_operand" " rK") @@ -2528,7 +2389,7 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))] "TARGET_VECTOR" - "vmadc.vx\t%0,%1,%2" + "vmadc.vx\t%0,%1,%z2" [(set_attr "type" "vicalu") (set_attr "mode" "") (set_attr "vl_op_idx" "3") @@ -2540,7 +2401,7 @@ [(plus:VI_D (vec_duplicate:VI_D (sign_extend: - (match_operand: 2 "register_operand" " r"))) + (match_operand: 2 "reg_or_0_operand" " rJ"))) (match_operand:VI_D 1 "register_operand" " vr")) (unspec: [(match_operand 3 "vector_length_operand" " rK") @@ -2548,7 +2409,7 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))] "TARGET_VECTOR" - "vmadc.vx\t%0,%1,%2" + "vmadc.vx\t%0,%1,%z2" [(set_attr "type" "vicalu") (set_attr "mode" "") (set_attr "vl_op_idx" "3") @@ -2567,36 +2428,20 @@ (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)] UNSPEC_OVERFLOW))] "TARGET_VECTOR" - { - if (!TARGET_64BIT) - { - rtx v = gen_reg_rtx (mode); - - if (immediate_operand (operands[2], Pmode)) - { - if (!rtx_equal_p (operands[2], const0_rtx)) - operands[2] = force_reg (Pmode, operands[2]); - operands[2] = gen_rtx_SIGN_EXTEND (mode, operands[2]); - } - else - { - if (CONST_INT_P (operands[2])) - operands[2] = force_reg (mode, operands[2]); - - riscv_vector::emit_nonvlmax_op (code_for_pred_broadcast (mode), - v, operands[2], operands[3], - mode); - emit_insn (gen_pred_msbc_overflow (operands[0], operands[1], - v, operands[3], operands[4])); - DONE; - } - } - else - { - if (!rtx_equal_p (operands[2], const0_rtx)) - operands[2] = force_reg (mode, operands[2]); - } - }) +{ + if (riscv_vector::sew64_scalar_helper ( + operands, + /* scalar op */&operands[2], + /* vl */operands[3], + mode, + mode, + false, + [] (rtx *operands, rtx boardcast_scalar) { + emit_insn (gen_pred_msbc_overflow (operands[0], operands[1], + boardcast_scalar, operands[3], operands[4])); + })) + DONE; +}) (define_insn "*pred_msbc_overflow_scalar" [(set (match_operand: 0 "register_operand" "=&vr") @@ -3069,32 +2914,21 @@ (match_operand:VI_D 3 "register_operand")) (match_operand:VI_D 2 "vector_merge_operand")))] "TARGET_VECTOR" - { - if (riscv_vector::has_vi_variant_p (, operands[4])) - operands[4] = force_reg (mode, operands[4]); - else if (!TARGET_64BIT) - { - rtx v = gen_reg_rtx (mode); - - if (immediate_operand (operands[4], Pmode)) - operands[4] = gen_rtx_SIGN_EXTEND (mode, - force_reg (Pmode, operands[4])); - else - { - if (CONST_INT_P (operands[4])) - operands[4] = force_reg (mode, operands[4]); - - riscv_vector::emit_nonvlmax_op (code_for_pred_broadcast (mode), - v, operands[4], operands[5], mode); - emit_insn (gen_pred_ (operands[0], operands[1], - operands[2], operands[3], v, operands[5], - operands[6], operands[7], operands[8])); - DONE; - } - } - else - operands[4] = force_reg (mode, operands[4]); - }) +{ + if (riscv_vector::sew64_scalar_helper ( + operands, + /* scalar op */&operands[4], + /* vl */operands[5], + mode, + mode, + riscv_vector::has_vi_variant_p (, operands[4]), + [] (rtx *operands, rtx boardcast_scalar) { + emit_insn (gen_pred_ (operands[0], operands[1], + operands[2], operands[3], boardcast_scalar, operands[5], + operands[6], operands[7], operands[8])); + })) + DONE; +}) (define_insn "*pred__scalar" [(set (match_operand:VI_D 0 "register_operand" "=vd, vr") @@ -3156,32 +2990,21 @@ (match_operand: 4 "reg_or_int_operand"))) (match_operand:VI_D 2 "vector_merge_operand")))] "TARGET_VECTOR" - { - if (riscv_vector::has_vi_variant_p (, operands[4])) - operands[4] = force_reg (mode, operands[4]); - else if (!TARGET_64BIT) - { - rtx v = gen_reg_rtx (mode); - - if (immediate_operand (operands[4], Pmode)) - operands[4] = gen_rtx_SIGN_EXTEND (mode, - force_reg (Pmode, operands[4])); - else - { - if (CONST_INT_P (operands[4])) - operands[4] = force_reg (mode, operands[4]); - - riscv_vector::emit_nonvlmax_op (code_for_pred_broadcast (mode), - v, operands[4], operands[5], mode); - emit_insn (gen_pred_ (operands[0], operands[1], - operands[2], operands[3], v, operands[5], - operands[6], operands[7], operands[8])); - DONE; - } - } - else - operands[4] = force_reg (mode, operands[4]); - }) +{ + if (riscv_vector::sew64_scalar_helper ( + operands, + /* scalar op */&operands[4], + /* vl */operands[5], + mode, + mode, + riscv_vector::has_vi_variant_p (, operands[4]), + [] (rtx *operands, rtx boardcast_scalar) { + emit_insn (gen_pred_ (operands[0], operands[1], + operands[2], operands[3], boardcast_scalar, operands[5], + operands[6], operands[7], operands[8])); + })) + DONE; +}) (define_insn "*pred__scalar" [(set (match_operand:VI_D 0 "register_operand" "=vd, vr") @@ -3305,36 +3128,21 @@ (match_operand: 4 "reg_or_int_operand")] VSAT_ARITH_OP) (match_operand:VI_D 2 "vector_merge_operand")))] "TARGET_VECTOR" - { - if (!TARGET_64BIT) - { - rtx v = gen_reg_rtx (mode); - - if (immediate_operand (operands[4], Pmode)) - { - if (!rtx_equal_p (operands[4], const0_rtx)) - operands[4] = force_reg (Pmode, operands[4]); - operands[4] = gen_rtx_SIGN_EXTEND (mode, operands[4]); - } - else - { - if (CONST_INT_P (operands[4])) - operands[4] = force_reg (mode, operands[4]); - - riscv_vector::emit_nonvlmax_op (code_for_pred_broadcast (mode), - v, operands[4], operands[5], mode); - emit_insn (gen_pred_ (operands[0], operands[1], - operands[2], operands[3], v, operands[5], - operands[6], operands[7], operands[8])); - DONE; - } - } - else - { - if (!rtx_equal_p (operands[4], const0_rtx)) - operands[4] = force_reg (mode, operands[4]); - } - }) +{ + if (riscv_vector::sew64_scalar_helper ( + operands, + /* scalar op */&operands[4], + /* vl */operands[5], + mode, + mode, + false, + [] (rtx *operands, rtx boardcast_scalar) { + emit_insn (gen_pred_ (operands[0], operands[1], + operands[2], operands[3], boardcast_scalar, operands[5], + operands[6], operands[7], operands[8])); + })) + DONE; +}) (define_insn "*pred__scalar" [(set (match_operand:VI_D 0 "register_operand" "=vd, vr") @@ -3677,42 +3485,29 @@ (match_operand: 5 "reg_or_int_operand"))]) (match_operand: 2 "vector_merge_operand")))] "TARGET_VECTOR" - { - enum rtx_code code = GET_CODE (operands[3]); - - if (riscv_vector::has_vi_variant_p (code, operands[5])) - operands[5] = force_reg (mode, operands[5]); - else if (!TARGET_64BIT) - { - rtx v = gen_reg_rtx (mode); - - if (immediate_operand (operands[5], Pmode)) - { - if (!rtx_equal_p (operands[5], const0_rtx)) - operands[5] = force_reg (Pmode, operands[5]); - operands[5] = gen_rtx_SIGN_EXTEND (mode, operands[5]); - } - else - { - if (CONST_INT_P (operands[5])) - operands[5] = force_reg (mode, operands[5]); - - riscv_vector::emit_nonvlmax_op (code_for_pred_broadcast (mode), - v, operands[5], operands[6], mode); - if (code == LT || code == LTU) - emit_insn (gen_pred_ltge (operands[0], operands[1], - operands[2], operands[3], operands[4], v, - operands[6], operands[7], operands[8])); - else - emit_insn (gen_pred_cmp (operands[0], operands[1], - operands[2], operands[3], operands[4], v, - operands[6], operands[7], operands[8])); - DONE; - } - } - else - operands[5] = force_reg (mode, operands[5]); - }) +{ + enum rtx_code code = GET_CODE (operands[3]); + if (riscv_vector::sew64_scalar_helper ( + operands, + /* scalar op */&operands[5], + /* vl */operands[6], + mode, + mode, + riscv_vector::has_vi_variant_p (code, operands[5]), + code == LT || code == LTU ? + [] (rtx *operands, rtx boardcast_scalar) { + emit_insn (gen_pred_ltge (operands[0], operands[1], + operands[2], operands[3], operands[4], boardcast_scalar, + operands[6], operands[7], operands[8])); + } + : + [] (rtx *operands, rtx boardcast_scalar) { + emit_insn (gen_pred_cmp (operands[0], operands[1], + operands[2], operands[3], operands[4], boardcast_scalar, + operands[6], operands[7], operands[8])); + })) + DONE; +}) (define_expand "@pred_eqne_scalar" [(set (match_operand: 0 "register_operand") @@ -3730,37 +3525,22 @@ (match_operand:VI_D 4 "register_operand")]) (match_operand: 2 "vector_merge_operand")))] "TARGET_VECTOR" - { - enum rtx_code code = GET_CODE (operands[3]); - - if (riscv_vector::has_vi_variant_p (code, operands[5])) - operands[5] = force_reg (mode, operands[5]); - else if (!TARGET_64BIT) - { - rtx v = gen_reg_rtx (mode); - - if (immediate_operand (operands[5], Pmode)) - { - if (!rtx_equal_p (operands[5], const0_rtx)) - operands[5] = force_reg (Pmode, operands[5]); - operands[5] = gen_rtx_SIGN_EXTEND (mode, operands[5]); - } - else - { - if (CONST_INT_P (operands[5])) - operands[5] = force_reg (mode, operands[5]); - - riscv_vector::emit_nonvlmax_op (code_for_pred_broadcast (mode), - v, operands[5], operands[6], mode); - emit_insn (gen_pred_cmp (operands[0], operands[1], - operands[2], operands[3], operands[4], v, - operands[6], operands[7], operands[8])); - DONE; - } - } - else - operands[5] = force_reg (mode, operands[5]); - }) +{ + enum rtx_code code = GET_CODE (operands[3]); + if (riscv_vector::sew64_scalar_helper ( + operands, + /* scalar op */&operands[5], + /* vl */operands[6], + mode, + mode, + riscv_vector::has_vi_variant_p (code, operands[5]), + [] (rtx *operands, rtx boardcast_scalar) { + emit_insn (gen_pred_cmp (operands[0], operands[1], + operands[2], operands[3], operands[4], boardcast_scalar, + operands[6], operands[7], operands[8])); + })) + DONE; +}) ;; We don't use early-clobber for LMUL <= 1 to get better codegen. (define_insn "*pred_cmp_scalar" @@ -4400,28 +4180,19 @@ (match_operand:VI_D 5 "vector_merge_operand")))] "TARGET_VECTOR" { - if (!TARGET_64BIT) - { - rtx v = gen_reg_rtx (mode); - - if (immediate_operand (operands[2], Pmode)) - operands[2] = gen_rtx_SIGN_EXTEND (mode, - force_reg (Pmode, operands[2])); - else - { - if (CONST_INT_P (operands[2])) - operands[2] = force_reg (mode, operands[2]); - - riscv_vector::emit_nonvlmax_op (code_for_pred_broadcast (mode), - v, operands[2], operands[6], mode); + if (riscv_vector::sew64_scalar_helper ( + operands, + /* scalar op */&operands[2], + /* vl */operands[6], + mode, + mode, + false, + [] (rtx *operands, rtx boardcast_scalar) { emit_insn (gen_pred_mul_ (operands[0], operands[1], - v, operands[3], operands[4], operands[5], operands[6], - operands[7], operands[8], operands[9])); - DONE; - } - } - else - operands[2] = force_reg (mode, operands[2]); + boardcast_scalar, operands[3], operands[4], operands[5], + operands[6], operands[7], operands[8], operands[9])); + })) + DONE; }) (define_insn "*pred_mul__undef_merge_extended_scalar" -- 2.36.3