From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtpbgbr2.qq.com (smtpbgbr2.qq.com [54.207.22.56]) by sourceware.org (Postfix) with ESMTPS id A99BC3858D33 for ; Thu, 16 Feb 2023 03:38:27 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org A99BC3858D33 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp79t1676518700trzrygus Received: from server1.localdomain ( [58.60.1.22]) by bizesmtp.qq.com (ESMTP) with id ; Thu, 16 Feb 2023 11:38:19 +0800 (CST) X-QQ-SSF: 01400000000000E0M000000A0000000 X-QQ-FEAT: q+yjhizk/eLz7UHKb5Yx9QAIHJpGPE8wLnhkZ/0bvuCtZJA2wDGM+qh9CKrhB kYLe/G9TA/5qSW3F8bfd9JPaz3cgKQNn2sdJB9malOH+NmFU81g3dikGptIWVqgBy9sNG6q DKW8tOh3N6Tlpwq7wWOvSxNMBUqlKjgs+doETNMEEAfcjSYgfck/IH+jt2CFdI72gB4WG8g FAiXXihuvNGbNBArsfNYt/GsUXareFWNfrkKtjlGJSJ8mBPabJbax6NtaIgfUINFkXkJybA Fpjj4JSF2iYLcX4qlq/NZUROUcbhZQ9WFZ9/7wBJxO6n1Uo1/M1q0rWBE6YIvV/+3Lk4+EX IFDKBWN81GPDpM9sccLf4fSgExh2kfPDenayE3HKKQDNeZKXJR6F20BamT12A== X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: Add vid.v/viota.m C api tests Date: Thu, 16 Feb 2023 11:38:19 +0800 Message-Id: <20230216033819.16850-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,KAM_SHORT,RCVD_IN_BARRACUDACENTRAL,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Ju-Zhe Zhong gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/vid_v-1.c: New test. * gcc.target/riscv/rvv/base/vid_v-2.c: New test. * gcc.target/riscv/rvv/base/vid_v-3.c: New test. * gcc.target/riscv/rvv/base/vid_v_m-1.c: New test. * gcc.target/riscv/rvv/base/vid_v_m-2.c: New test. * gcc.target/riscv/rvv/base/vid_v_m-3.c: New test. * gcc.target/riscv/rvv/base/vid_v_mu-1.c: New test. * gcc.target/riscv/rvv/base/vid_v_mu-2.c: New test. * gcc.target/riscv/rvv/base/vid_v_mu-3.c: New test. * gcc.target/riscv/rvv/base/vid_v_tu-1.c: New test. * gcc.target/riscv/rvv/base/vid_v_tu-2.c: New test. * gcc.target/riscv/rvv/base/vid_v_tu-3.c: New test. * gcc.target/riscv/rvv/base/vid_v_tum-1.c: New test. * gcc.target/riscv/rvv/base/vid_v_tum-2.c: New test. * gcc.target/riscv/rvv/base/vid_v_tum-3.c: New test. * gcc.target/riscv/rvv/base/vid_v_tumu-1.c: New test. * gcc.target/riscv/rvv/base/vid_v_tumu-2.c: New test. * gcc.target/riscv/rvv/base/vid_v_tumu-3.c: New test. * gcc.target/riscv/rvv/base/viota_m_m-1.c: New test. * gcc.target/riscv/rvv/base/viota_m_m-2.c: New test. * gcc.target/riscv/rvv/base/viota_m_m-3.c: New test. * gcc.target/riscv/rvv/base/viota_m_mu-1.c: New test. * gcc.target/riscv/rvv/base/viota_m_mu-2.c: New test. * gcc.target/riscv/rvv/base/viota_m_mu-3.c: New test. * gcc.target/riscv/rvv/base/viota_m_tu-1.c: New test. * gcc.target/riscv/rvv/base/viota_m_tu-2.c: New test. * gcc.target/riscv/rvv/base/viota_m_tu-3.c: New test. * gcc.target/riscv/rvv/base/viota_m_tum-1.c: New test. * gcc.target/riscv/rvv/base/viota_m_tum-2.c: New test. * gcc.target/riscv/rvv/base/viota_m_tum-3.c: New test. * gcc.target/riscv/rvv/base/viota_m_tumu-1.c: New test. * gcc.target/riscv/rvv/base/viota_m_tumu-2.c: New test. * gcc.target/riscv/rvv/base/viota_m_tumu-3.c: New test. --- .../gcc.target/riscv/rvv/base/vid_v-1.c | 160 +++++++++ .../gcc.target/riscv/rvv/base/vid_v-2.c | 160 +++++++++ .../gcc.target/riscv/rvv/base/vid_v-3.c | 160 +++++++++ .../gcc.target/riscv/rvv/base/vid_v_m-1.c | 160 +++++++++ .../gcc.target/riscv/rvv/base/vid_v_m-2.c | 160 +++++++++ .../gcc.target/riscv/rvv/base/vid_v_m-3.c | 160 +++++++++ .../gcc.target/riscv/rvv/base/vid_v_mu-1.c | 160 +++++++++ .../gcc.target/riscv/rvv/base/vid_v_mu-2.c | 160 +++++++++ .../gcc.target/riscv/rvv/base/vid_v_mu-3.c | 160 +++++++++ .../gcc.target/riscv/rvv/base/vid_v_tu-1.c | 160 +++++++++ .../gcc.target/riscv/rvv/base/vid_v_tu-2.c | 160 +++++++++ .../gcc.target/riscv/rvv/base/vid_v_tu-3.c | 160 +++++++++ .../gcc.target/riscv/rvv/base/vid_v_tum-1.c | 160 +++++++++ .../gcc.target/riscv/rvv/base/vid_v_tum-2.c | 160 +++++++++ .../gcc.target/riscv/rvv/base/vid_v_tum-3.c | 160 +++++++++ .../gcc.target/riscv/rvv/base/vid_v_tumu-1.c | 160 +++++++++ .../gcc.target/riscv/rvv/base/vid_v_tumu-2.c | 160 +++++++++ .../gcc.target/riscv/rvv/base/vid_v_tumu-3.c | 160 +++++++++ .../gcc.target/riscv/rvv/base/viota_m_m-1.c | 314 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/viota_m_m-2.c | 314 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/viota_m_m-3.c | 314 ++++++++++++++++++ .../gcc.target/riscv/rvv/base/viota_m_mu-1.c | 160 +++++++++ .../gcc.target/riscv/rvv/base/viota_m_mu-2.c | 160 +++++++++ .../gcc.target/riscv/rvv/base/viota_m_mu-3.c | 160 +++++++++ .../gcc.target/riscv/rvv/base/viota_m_tu-1.c | 160 +++++++++ .../gcc.target/riscv/rvv/base/viota_m_tu-2.c | 160 +++++++++ .../gcc.target/riscv/rvv/base/viota_m_tu-3.c | 160 +++++++++ .../gcc.target/riscv/rvv/base/viota_m_tum-1.c | 160 +++++++++ .../gcc.target/riscv/rvv/base/viota_m_tum-2.c | 160 +++++++++ .../gcc.target/riscv/rvv/base/viota_m_tum-3.c | 160 +++++++++ .../riscv/rvv/base/viota_m_tumu-1.c | 160 +++++++++ .../riscv/rvv/base/viota_m_tumu-2.c | 160 +++++++++ .../riscv/rvv/base/viota_m_tumu-3.c | 160 +++++++++ 33 files changed, 5742 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vid_v-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vid_v-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vid_v-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vid_v_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vid_v_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vid_v_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vid_v_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vid_v_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vid_v_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vid_v_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vid_v_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vid_v_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vid_v_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vid_v_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vid_v_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vid_v_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vid_v_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vid_v_tumu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/viota_m_m-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/viota_m_m-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/viota_m_m-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/viota_m_mu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/viota_m_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/viota_m_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/viota_m_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/viota_m_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/viota_m_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/viota_m_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/viota_m_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/viota_m_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/viota_m_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/viota_m_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/viota_m_tumu-3.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vid_v-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vid_v-1.c new file mode 100644 index 00000000000..96d0dc7b35e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vid_v-1.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vid_v_u8mf8(size_t vl) +{ + return __riscv_vid_v_u8mf8(vl); +} + + +vuint8mf4_t test___riscv_vid_v_u8mf4(size_t vl) +{ + return __riscv_vid_v_u8mf4(vl); +} + + +vuint8mf2_t test___riscv_vid_v_u8mf2(size_t vl) +{ + return __riscv_vid_v_u8mf2(vl); +} + + +vuint8m1_t test___riscv_vid_v_u8m1(size_t vl) +{ + return __riscv_vid_v_u8m1(vl); +} + + +vuint8m2_t test___riscv_vid_v_u8m2(size_t vl) +{ + return __riscv_vid_v_u8m2(vl); +} + + +vuint8m4_t test___riscv_vid_v_u8m4(size_t vl) +{ + return __riscv_vid_v_u8m4(vl); +} + + +vuint8m8_t test___riscv_vid_v_u8m8(size_t vl) +{ + return __riscv_vid_v_u8m8(vl); +} + + +vuint16mf4_t test___riscv_vid_v_u16mf4(size_t vl) +{ + return __riscv_vid_v_u16mf4(vl); +} + + +vuint16mf2_t test___riscv_vid_v_u16mf2(size_t vl) +{ + return __riscv_vid_v_u16mf2(vl); +} + + +vuint16m1_t test___riscv_vid_v_u16m1(size_t vl) +{ + return __riscv_vid_v_u16m1(vl); +} + + +vuint16m2_t test___riscv_vid_v_u16m2(size_t vl) +{ + return __riscv_vid_v_u16m2(vl); +} + + +vuint16m4_t test___riscv_vid_v_u16m4(size_t vl) +{ + return __riscv_vid_v_u16m4(vl); +} + + +vuint16m8_t test___riscv_vid_v_u16m8(size_t vl) +{ + return __riscv_vid_v_u16m8(vl); +} + + +vuint32mf2_t test___riscv_vid_v_u32mf2(size_t vl) +{ + return __riscv_vid_v_u32mf2(vl); +} + + +vuint32m1_t test___riscv_vid_v_u32m1(size_t vl) +{ + return __riscv_vid_v_u32m1(vl); +} + + +vuint32m2_t test___riscv_vid_v_u32m2(size_t vl) +{ + return __riscv_vid_v_u32m2(vl); +} + + +vuint32m4_t test___riscv_vid_v_u32m4(size_t vl) +{ + return __riscv_vid_v_u32m4(vl); +} + + +vuint32m8_t test___riscv_vid_v_u32m8(size_t vl) +{ + return __riscv_vid_v_u32m8(vl); +} + + +vuint64m1_t test___riscv_vid_v_u64m1(size_t vl) +{ + return __riscv_vid_v_u64m1(vl); +} + + +vuint64m2_t test___riscv_vid_v_u64m2(size_t vl) +{ + return __riscv_vid_v_u64m2(vl); +} + + +vuint64m4_t test___riscv_vid_v_u64m4(size_t vl) +{ + return __riscv_vid_v_u64m4(vl); +} + + +vuint64m8_t test___riscv_vid_v_u64m8(size_t vl) +{ + return __riscv_vid_v_u64m8(vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vid_v-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vid_v-2.c new file mode 100644 index 00000000000..9190b67ef77 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vid_v-2.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vid_v_u8mf8(size_t vl) +{ + return __riscv_vid_v_u8mf8(31); +} + + +vuint8mf4_t test___riscv_vid_v_u8mf4(size_t vl) +{ + return __riscv_vid_v_u8mf4(31); +} + + +vuint8mf2_t test___riscv_vid_v_u8mf2(size_t vl) +{ + return __riscv_vid_v_u8mf2(31); +} + + +vuint8m1_t test___riscv_vid_v_u8m1(size_t vl) +{ + return __riscv_vid_v_u8m1(31); +} + + +vuint8m2_t test___riscv_vid_v_u8m2(size_t vl) +{ + return __riscv_vid_v_u8m2(31); +} + + +vuint8m4_t test___riscv_vid_v_u8m4(size_t vl) +{ + return __riscv_vid_v_u8m4(31); +} + + +vuint8m8_t test___riscv_vid_v_u8m8(size_t vl) +{ + return __riscv_vid_v_u8m8(31); +} + + +vuint16mf4_t test___riscv_vid_v_u16mf4(size_t vl) +{ + return __riscv_vid_v_u16mf4(31); +} + + +vuint16mf2_t test___riscv_vid_v_u16mf2(size_t vl) +{ + return __riscv_vid_v_u16mf2(31); +} + + +vuint16m1_t test___riscv_vid_v_u16m1(size_t vl) +{ + return __riscv_vid_v_u16m1(31); +} + + +vuint16m2_t test___riscv_vid_v_u16m2(size_t vl) +{ + return __riscv_vid_v_u16m2(31); +} + + +vuint16m4_t test___riscv_vid_v_u16m4(size_t vl) +{ + return __riscv_vid_v_u16m4(31); +} + + +vuint16m8_t test___riscv_vid_v_u16m8(size_t vl) +{ + return __riscv_vid_v_u16m8(31); +} + + +vuint32mf2_t test___riscv_vid_v_u32mf2(size_t vl) +{ + return __riscv_vid_v_u32mf2(31); +} + + +vuint32m1_t test___riscv_vid_v_u32m1(size_t vl) +{ + return __riscv_vid_v_u32m1(31); +} + + +vuint32m2_t test___riscv_vid_v_u32m2(size_t vl) +{ + return __riscv_vid_v_u32m2(31); +} + + +vuint32m4_t test___riscv_vid_v_u32m4(size_t vl) +{ + return __riscv_vid_v_u32m4(31); +} + + +vuint32m8_t test___riscv_vid_v_u32m8(size_t vl) +{ + return __riscv_vid_v_u32m8(31); +} + + +vuint64m1_t test___riscv_vid_v_u64m1(size_t vl) +{ + return __riscv_vid_v_u64m1(31); +} + + +vuint64m2_t test___riscv_vid_v_u64m2(size_t vl) +{ + return __riscv_vid_v_u64m2(31); +} + + +vuint64m4_t test___riscv_vid_v_u64m4(size_t vl) +{ + return __riscv_vid_v_u64m4(31); +} + + +vuint64m8_t test___riscv_vid_v_u64m8(size_t vl) +{ + return __riscv_vid_v_u64m8(31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vid_v-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vid_v-3.c new file mode 100644 index 00000000000..b4cbce17aba --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vid_v-3.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vid_v_u8mf8(size_t vl) +{ + return __riscv_vid_v_u8mf8(32); +} + + +vuint8mf4_t test___riscv_vid_v_u8mf4(size_t vl) +{ + return __riscv_vid_v_u8mf4(32); +} + + +vuint8mf2_t test___riscv_vid_v_u8mf2(size_t vl) +{ + return __riscv_vid_v_u8mf2(32); +} + + +vuint8m1_t test___riscv_vid_v_u8m1(size_t vl) +{ + return __riscv_vid_v_u8m1(32); +} + + +vuint8m2_t test___riscv_vid_v_u8m2(size_t vl) +{ + return __riscv_vid_v_u8m2(32); +} + + +vuint8m4_t test___riscv_vid_v_u8m4(size_t vl) +{ + return __riscv_vid_v_u8m4(32); +} + + +vuint8m8_t test___riscv_vid_v_u8m8(size_t vl) +{ + return __riscv_vid_v_u8m8(32); +} + + +vuint16mf4_t test___riscv_vid_v_u16mf4(size_t vl) +{ + return __riscv_vid_v_u16mf4(32); +} + + +vuint16mf2_t test___riscv_vid_v_u16mf2(size_t vl) +{ + return __riscv_vid_v_u16mf2(32); +} + + +vuint16m1_t test___riscv_vid_v_u16m1(size_t vl) +{ + return __riscv_vid_v_u16m1(32); +} + + +vuint16m2_t test___riscv_vid_v_u16m2(size_t vl) +{ + return __riscv_vid_v_u16m2(32); +} + + +vuint16m4_t test___riscv_vid_v_u16m4(size_t vl) +{ + return __riscv_vid_v_u16m4(32); +} + + +vuint16m8_t test___riscv_vid_v_u16m8(size_t vl) +{ + return __riscv_vid_v_u16m8(32); +} + + +vuint32mf2_t test___riscv_vid_v_u32mf2(size_t vl) +{ + return __riscv_vid_v_u32mf2(32); +} + + +vuint32m1_t test___riscv_vid_v_u32m1(size_t vl) +{ + return __riscv_vid_v_u32m1(32); +} + + +vuint32m2_t test___riscv_vid_v_u32m2(size_t vl) +{ + return __riscv_vid_v_u32m2(32); +} + + +vuint32m4_t test___riscv_vid_v_u32m4(size_t vl) +{ + return __riscv_vid_v_u32m4(32); +} + + +vuint32m8_t test___riscv_vid_v_u32m8(size_t vl) +{ + return __riscv_vid_v_u32m8(32); +} + + +vuint64m1_t test___riscv_vid_v_u64m1(size_t vl) +{ + return __riscv_vid_v_u64m1(32); +} + + +vuint64m2_t test___riscv_vid_v_u64m2(size_t vl) +{ + return __riscv_vid_v_u64m2(32); +} + + +vuint64m4_t test___riscv_vid_v_u64m4(size_t vl) +{ + return __riscv_vid_v_u64m4(32); +} + + +vuint64m8_t test___riscv_vid_v_u64m8(size_t vl) +{ + return __riscv_vid_v_u64m8(32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vid_v_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vid_v_m-1.c new file mode 100644 index 00000000000..f5b028fdfc0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vid_v_m-1.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vid_v_u8mf8_m(vbool64_t mask,size_t vl) +{ + return __riscv_vid_v_u8mf8_m(mask,vl); +} + + +vuint8mf4_t test___riscv_vid_v_u8mf4_m(vbool32_t mask,size_t vl) +{ + return __riscv_vid_v_u8mf4_m(mask,vl); +} + + +vuint8mf2_t test___riscv_vid_v_u8mf2_m(vbool16_t mask,size_t vl) +{ + return __riscv_vid_v_u8mf2_m(mask,vl); +} + + +vuint8m1_t test___riscv_vid_v_u8m1_m(vbool8_t mask,size_t vl) +{ + return __riscv_vid_v_u8m1_m(mask,vl); +} + + +vuint8m2_t test___riscv_vid_v_u8m2_m(vbool4_t mask,size_t vl) +{ + return __riscv_vid_v_u8m2_m(mask,vl); +} + + +vuint8m4_t test___riscv_vid_v_u8m4_m(vbool2_t mask,size_t vl) +{ + return __riscv_vid_v_u8m4_m(mask,vl); +} + + +vuint8m8_t test___riscv_vid_v_u8m8_m(vbool1_t mask,size_t vl) +{ + return __riscv_vid_v_u8m8_m(mask,vl); +} + + +vuint16mf4_t test___riscv_vid_v_u16mf4_m(vbool64_t mask,size_t vl) +{ + return __riscv_vid_v_u16mf4_m(mask,vl); +} + + +vuint16mf2_t test___riscv_vid_v_u16mf2_m(vbool32_t mask,size_t vl) +{ + return __riscv_vid_v_u16mf2_m(mask,vl); +} + + +vuint16m1_t test___riscv_vid_v_u16m1_m(vbool16_t mask,size_t vl) +{ + return __riscv_vid_v_u16m1_m(mask,vl); +} + + +vuint16m2_t test___riscv_vid_v_u16m2_m(vbool8_t mask,size_t vl) +{ + return __riscv_vid_v_u16m2_m(mask,vl); +} + + +vuint16m4_t test___riscv_vid_v_u16m4_m(vbool4_t mask,size_t vl) +{ + return __riscv_vid_v_u16m4_m(mask,vl); +} + + +vuint16m8_t test___riscv_vid_v_u16m8_m(vbool2_t mask,size_t vl) +{ + return __riscv_vid_v_u16m8_m(mask,vl); +} + + +vuint32mf2_t test___riscv_vid_v_u32mf2_m(vbool64_t mask,size_t vl) +{ + return __riscv_vid_v_u32mf2_m(mask,vl); +} + + +vuint32m1_t test___riscv_vid_v_u32m1_m(vbool32_t mask,size_t vl) +{ + return __riscv_vid_v_u32m1_m(mask,vl); +} + + +vuint32m2_t test___riscv_vid_v_u32m2_m(vbool16_t mask,size_t vl) +{ + return __riscv_vid_v_u32m2_m(mask,vl); +} + + +vuint32m4_t test___riscv_vid_v_u32m4_m(vbool8_t mask,size_t vl) +{ + return __riscv_vid_v_u32m4_m(mask,vl); +} + + +vuint32m8_t test___riscv_vid_v_u32m8_m(vbool4_t mask,size_t vl) +{ + return __riscv_vid_v_u32m8_m(mask,vl); +} + + +vuint64m1_t test___riscv_vid_v_u64m1_m(vbool64_t mask,size_t vl) +{ + return __riscv_vid_v_u64m1_m(mask,vl); +} + + +vuint64m2_t test___riscv_vid_v_u64m2_m(vbool32_t mask,size_t vl) +{ + return __riscv_vid_v_u64m2_m(mask,vl); +} + + +vuint64m4_t test___riscv_vid_v_u64m4_m(vbool16_t mask,size_t vl) +{ + return __riscv_vid_v_u64m4_m(mask,vl); +} + + +vuint64m8_t test___riscv_vid_v_u64m8_m(vbool8_t mask,size_t vl) +{ + return __riscv_vid_v_u64m8_m(mask,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vid_v_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vid_v_m-2.c new file mode 100644 index 00000000000..7c87ca42914 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vid_v_m-2.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vid_v_u8mf8_m(vbool64_t mask,size_t vl) +{ + return __riscv_vid_v_u8mf8_m(mask,31); +} + + +vuint8mf4_t test___riscv_vid_v_u8mf4_m(vbool32_t mask,size_t vl) +{ + return __riscv_vid_v_u8mf4_m(mask,31); +} + + +vuint8mf2_t test___riscv_vid_v_u8mf2_m(vbool16_t mask,size_t vl) +{ + return __riscv_vid_v_u8mf2_m(mask,31); +} + + +vuint8m1_t test___riscv_vid_v_u8m1_m(vbool8_t mask,size_t vl) +{ + return __riscv_vid_v_u8m1_m(mask,31); +} + + +vuint8m2_t test___riscv_vid_v_u8m2_m(vbool4_t mask,size_t vl) +{ + return __riscv_vid_v_u8m2_m(mask,31); +} + + +vuint8m4_t test___riscv_vid_v_u8m4_m(vbool2_t mask,size_t vl) +{ + return __riscv_vid_v_u8m4_m(mask,31); +} + + +vuint8m8_t test___riscv_vid_v_u8m8_m(vbool1_t mask,size_t vl) +{ + return __riscv_vid_v_u8m8_m(mask,31); +} + + +vuint16mf4_t test___riscv_vid_v_u16mf4_m(vbool64_t mask,size_t vl) +{ + return __riscv_vid_v_u16mf4_m(mask,31); +} + + +vuint16mf2_t test___riscv_vid_v_u16mf2_m(vbool32_t mask,size_t vl) +{ + return __riscv_vid_v_u16mf2_m(mask,31); +} + + +vuint16m1_t test___riscv_vid_v_u16m1_m(vbool16_t mask,size_t vl) +{ + return __riscv_vid_v_u16m1_m(mask,31); +} + + +vuint16m2_t test___riscv_vid_v_u16m2_m(vbool8_t mask,size_t vl) +{ + return __riscv_vid_v_u16m2_m(mask,31); +} + + +vuint16m4_t test___riscv_vid_v_u16m4_m(vbool4_t mask,size_t vl) +{ + return __riscv_vid_v_u16m4_m(mask,31); +} + + +vuint16m8_t test___riscv_vid_v_u16m8_m(vbool2_t mask,size_t vl) +{ + return __riscv_vid_v_u16m8_m(mask,31); +} + + +vuint32mf2_t test___riscv_vid_v_u32mf2_m(vbool64_t mask,size_t vl) +{ + return __riscv_vid_v_u32mf2_m(mask,31); +} + + +vuint32m1_t test___riscv_vid_v_u32m1_m(vbool32_t mask,size_t vl) +{ + return __riscv_vid_v_u32m1_m(mask,31); +} + + +vuint32m2_t test___riscv_vid_v_u32m2_m(vbool16_t mask,size_t vl) +{ + return __riscv_vid_v_u32m2_m(mask,31); +} + + +vuint32m4_t test___riscv_vid_v_u32m4_m(vbool8_t mask,size_t vl) +{ + return __riscv_vid_v_u32m4_m(mask,31); +} + + +vuint32m8_t test___riscv_vid_v_u32m8_m(vbool4_t mask,size_t vl) +{ + return __riscv_vid_v_u32m8_m(mask,31); +} + + +vuint64m1_t test___riscv_vid_v_u64m1_m(vbool64_t mask,size_t vl) +{ + return __riscv_vid_v_u64m1_m(mask,31); +} + + +vuint64m2_t test___riscv_vid_v_u64m2_m(vbool32_t mask,size_t vl) +{ + return __riscv_vid_v_u64m2_m(mask,31); +} + + +vuint64m4_t test___riscv_vid_v_u64m4_m(vbool16_t mask,size_t vl) +{ + return __riscv_vid_v_u64m4_m(mask,31); +} + + +vuint64m8_t test___riscv_vid_v_u64m8_m(vbool8_t mask,size_t vl) +{ + return __riscv_vid_v_u64m8_m(mask,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vid_v_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vid_v_m-3.c new file mode 100644 index 00000000000..496fa6d9160 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vid_v_m-3.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vid_v_u8mf8_m(vbool64_t mask,size_t vl) +{ + return __riscv_vid_v_u8mf8_m(mask,32); +} + + +vuint8mf4_t test___riscv_vid_v_u8mf4_m(vbool32_t mask,size_t vl) +{ + return __riscv_vid_v_u8mf4_m(mask,32); +} + + +vuint8mf2_t test___riscv_vid_v_u8mf2_m(vbool16_t mask,size_t vl) +{ + return __riscv_vid_v_u8mf2_m(mask,32); +} + + +vuint8m1_t test___riscv_vid_v_u8m1_m(vbool8_t mask,size_t vl) +{ + return __riscv_vid_v_u8m1_m(mask,32); +} + + +vuint8m2_t test___riscv_vid_v_u8m2_m(vbool4_t mask,size_t vl) +{ + return __riscv_vid_v_u8m2_m(mask,32); +} + + +vuint8m4_t test___riscv_vid_v_u8m4_m(vbool2_t mask,size_t vl) +{ + return __riscv_vid_v_u8m4_m(mask,32); +} + + +vuint8m8_t test___riscv_vid_v_u8m8_m(vbool1_t mask,size_t vl) +{ + return __riscv_vid_v_u8m8_m(mask,32); +} + + +vuint16mf4_t test___riscv_vid_v_u16mf4_m(vbool64_t mask,size_t vl) +{ + return __riscv_vid_v_u16mf4_m(mask,32); +} + + +vuint16mf2_t test___riscv_vid_v_u16mf2_m(vbool32_t mask,size_t vl) +{ + return __riscv_vid_v_u16mf2_m(mask,32); +} + + +vuint16m1_t test___riscv_vid_v_u16m1_m(vbool16_t mask,size_t vl) +{ + return __riscv_vid_v_u16m1_m(mask,32); +} + + +vuint16m2_t test___riscv_vid_v_u16m2_m(vbool8_t mask,size_t vl) +{ + return __riscv_vid_v_u16m2_m(mask,32); +} + + +vuint16m4_t test___riscv_vid_v_u16m4_m(vbool4_t mask,size_t vl) +{ + return __riscv_vid_v_u16m4_m(mask,32); +} + + +vuint16m8_t test___riscv_vid_v_u16m8_m(vbool2_t mask,size_t vl) +{ + return __riscv_vid_v_u16m8_m(mask,32); +} + + +vuint32mf2_t test___riscv_vid_v_u32mf2_m(vbool64_t mask,size_t vl) +{ + return __riscv_vid_v_u32mf2_m(mask,32); +} + + +vuint32m1_t test___riscv_vid_v_u32m1_m(vbool32_t mask,size_t vl) +{ + return __riscv_vid_v_u32m1_m(mask,32); +} + + +vuint32m2_t test___riscv_vid_v_u32m2_m(vbool16_t mask,size_t vl) +{ + return __riscv_vid_v_u32m2_m(mask,32); +} + + +vuint32m4_t test___riscv_vid_v_u32m4_m(vbool8_t mask,size_t vl) +{ + return __riscv_vid_v_u32m4_m(mask,32); +} + + +vuint32m8_t test___riscv_vid_v_u32m8_m(vbool4_t mask,size_t vl) +{ + return __riscv_vid_v_u32m8_m(mask,32); +} + + +vuint64m1_t test___riscv_vid_v_u64m1_m(vbool64_t mask,size_t vl) +{ + return __riscv_vid_v_u64m1_m(mask,32); +} + + +vuint64m2_t test___riscv_vid_v_u64m2_m(vbool32_t mask,size_t vl) +{ + return __riscv_vid_v_u64m2_m(mask,32); +} + + +vuint64m4_t test___riscv_vid_v_u64m4_m(vbool16_t mask,size_t vl) +{ + return __riscv_vid_v_u64m4_m(mask,32); +} + + +vuint64m8_t test___riscv_vid_v_u64m8_m(vbool8_t mask,size_t vl) +{ + return __riscv_vid_v_u64m8_m(mask,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vid_v_mu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vid_v_mu-1.c new file mode 100644 index 00000000000..ab53192383c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vid_v_mu-1.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vid_v_u8mf8_mu(vbool64_t mask,vuint8mf8_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8mf8_mu(mask,maskedoff,vl); +} + + +vuint8mf4_t test___riscv_vid_v_u8mf4_mu(vbool32_t mask,vuint8mf4_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8mf4_mu(mask,maskedoff,vl); +} + + +vuint8mf2_t test___riscv_vid_v_u8mf2_mu(vbool16_t mask,vuint8mf2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8mf2_mu(mask,maskedoff,vl); +} + + +vuint8m1_t test___riscv_vid_v_u8m1_mu(vbool8_t mask,vuint8m1_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8m1_mu(mask,maskedoff,vl); +} + + +vuint8m2_t test___riscv_vid_v_u8m2_mu(vbool4_t mask,vuint8m2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8m2_mu(mask,maskedoff,vl); +} + + +vuint8m4_t test___riscv_vid_v_u8m4_mu(vbool2_t mask,vuint8m4_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8m4_mu(mask,maskedoff,vl); +} + + +vuint8m8_t test___riscv_vid_v_u8m8_mu(vbool1_t mask,vuint8m8_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8m8_mu(mask,maskedoff,vl); +} + + +vuint16mf4_t test___riscv_vid_v_u16mf4_mu(vbool64_t mask,vuint16mf4_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u16mf4_mu(mask,maskedoff,vl); +} + + +vuint16mf2_t test___riscv_vid_v_u16mf2_mu(vbool32_t mask,vuint16mf2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u16mf2_mu(mask,maskedoff,vl); +} + + +vuint16m1_t test___riscv_vid_v_u16m1_mu(vbool16_t mask,vuint16m1_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u16m1_mu(mask,maskedoff,vl); +} + + +vuint16m2_t test___riscv_vid_v_u16m2_mu(vbool8_t mask,vuint16m2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u16m2_mu(mask,maskedoff,vl); +} + + +vuint16m4_t test___riscv_vid_v_u16m4_mu(vbool4_t mask,vuint16m4_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u16m4_mu(mask,maskedoff,vl); +} + + +vuint16m8_t test___riscv_vid_v_u16m8_mu(vbool2_t mask,vuint16m8_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u16m8_mu(mask,maskedoff,vl); +} + + +vuint32mf2_t test___riscv_vid_v_u32mf2_mu(vbool64_t mask,vuint32mf2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u32mf2_mu(mask,maskedoff,vl); +} + + +vuint32m1_t test___riscv_vid_v_u32m1_mu(vbool32_t mask,vuint32m1_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u32m1_mu(mask,maskedoff,vl); +} + + +vuint32m2_t test___riscv_vid_v_u32m2_mu(vbool16_t mask,vuint32m2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u32m2_mu(mask,maskedoff,vl); +} + + +vuint32m4_t test___riscv_vid_v_u32m4_mu(vbool8_t mask,vuint32m4_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u32m4_mu(mask,maskedoff,vl); +} + + +vuint32m8_t test___riscv_vid_v_u32m8_mu(vbool4_t mask,vuint32m8_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u32m8_mu(mask,maskedoff,vl); +} + + +vuint64m1_t test___riscv_vid_v_u64m1_mu(vbool64_t mask,vuint64m1_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u64m1_mu(mask,maskedoff,vl); +} + + +vuint64m2_t test___riscv_vid_v_u64m2_mu(vbool32_t mask,vuint64m2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u64m2_mu(mask,maskedoff,vl); +} + + +vuint64m4_t test___riscv_vid_v_u64m4_mu(vbool16_t mask,vuint64m4_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u64m4_mu(mask,maskedoff,vl); +} + + +vuint64m8_t test___riscv_vid_v_u64m8_mu(vbool8_t mask,vuint64m8_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u64m8_mu(mask,maskedoff,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vid_v_mu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vid_v_mu-2.c new file mode 100644 index 00000000000..b18976080a9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vid_v_mu-2.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vid_v_u8mf8_mu(vbool64_t mask,vuint8mf8_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8mf8_mu(mask,maskedoff,31); +} + + +vuint8mf4_t test___riscv_vid_v_u8mf4_mu(vbool32_t mask,vuint8mf4_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8mf4_mu(mask,maskedoff,31); +} + + +vuint8mf2_t test___riscv_vid_v_u8mf2_mu(vbool16_t mask,vuint8mf2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8mf2_mu(mask,maskedoff,31); +} + + +vuint8m1_t test___riscv_vid_v_u8m1_mu(vbool8_t mask,vuint8m1_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8m1_mu(mask,maskedoff,31); +} + + +vuint8m2_t test___riscv_vid_v_u8m2_mu(vbool4_t mask,vuint8m2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8m2_mu(mask,maskedoff,31); +} + + +vuint8m4_t test___riscv_vid_v_u8m4_mu(vbool2_t mask,vuint8m4_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8m4_mu(mask,maskedoff,31); +} + + +vuint8m8_t test___riscv_vid_v_u8m8_mu(vbool1_t mask,vuint8m8_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8m8_mu(mask,maskedoff,31); +} + + +vuint16mf4_t test___riscv_vid_v_u16mf4_mu(vbool64_t mask,vuint16mf4_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u16mf4_mu(mask,maskedoff,31); +} + + +vuint16mf2_t test___riscv_vid_v_u16mf2_mu(vbool32_t mask,vuint16mf2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u16mf2_mu(mask,maskedoff,31); +} + + +vuint16m1_t test___riscv_vid_v_u16m1_mu(vbool16_t mask,vuint16m1_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u16m1_mu(mask,maskedoff,31); +} + + +vuint16m2_t test___riscv_vid_v_u16m2_mu(vbool8_t mask,vuint16m2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u16m2_mu(mask,maskedoff,31); +} + + +vuint16m4_t test___riscv_vid_v_u16m4_mu(vbool4_t mask,vuint16m4_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u16m4_mu(mask,maskedoff,31); +} + + +vuint16m8_t test___riscv_vid_v_u16m8_mu(vbool2_t mask,vuint16m8_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u16m8_mu(mask,maskedoff,31); +} + + +vuint32mf2_t test___riscv_vid_v_u32mf2_mu(vbool64_t mask,vuint32mf2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u32mf2_mu(mask,maskedoff,31); +} + + +vuint32m1_t test___riscv_vid_v_u32m1_mu(vbool32_t mask,vuint32m1_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u32m1_mu(mask,maskedoff,31); +} + + +vuint32m2_t test___riscv_vid_v_u32m2_mu(vbool16_t mask,vuint32m2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u32m2_mu(mask,maskedoff,31); +} + + +vuint32m4_t test___riscv_vid_v_u32m4_mu(vbool8_t mask,vuint32m4_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u32m4_mu(mask,maskedoff,31); +} + + +vuint32m8_t test___riscv_vid_v_u32m8_mu(vbool4_t mask,vuint32m8_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u32m8_mu(mask,maskedoff,31); +} + + +vuint64m1_t test___riscv_vid_v_u64m1_mu(vbool64_t mask,vuint64m1_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u64m1_mu(mask,maskedoff,31); +} + + +vuint64m2_t test___riscv_vid_v_u64m2_mu(vbool32_t mask,vuint64m2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u64m2_mu(mask,maskedoff,31); +} + + +vuint64m4_t test___riscv_vid_v_u64m4_mu(vbool16_t mask,vuint64m4_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u64m4_mu(mask,maskedoff,31); +} + + +vuint64m8_t test___riscv_vid_v_u64m8_mu(vbool8_t mask,vuint64m8_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u64m8_mu(mask,maskedoff,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vid_v_mu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vid_v_mu-3.c new file mode 100644 index 00000000000..84741eda832 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vid_v_mu-3.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vid_v_u8mf8_mu(vbool64_t mask,vuint8mf8_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8mf8_mu(mask,maskedoff,32); +} + + +vuint8mf4_t test___riscv_vid_v_u8mf4_mu(vbool32_t mask,vuint8mf4_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8mf4_mu(mask,maskedoff,32); +} + + +vuint8mf2_t test___riscv_vid_v_u8mf2_mu(vbool16_t mask,vuint8mf2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8mf2_mu(mask,maskedoff,32); +} + + +vuint8m1_t test___riscv_vid_v_u8m1_mu(vbool8_t mask,vuint8m1_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8m1_mu(mask,maskedoff,32); +} + + +vuint8m2_t test___riscv_vid_v_u8m2_mu(vbool4_t mask,vuint8m2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8m2_mu(mask,maskedoff,32); +} + + +vuint8m4_t test___riscv_vid_v_u8m4_mu(vbool2_t mask,vuint8m4_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8m4_mu(mask,maskedoff,32); +} + + +vuint8m8_t test___riscv_vid_v_u8m8_mu(vbool1_t mask,vuint8m8_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8m8_mu(mask,maskedoff,32); +} + + +vuint16mf4_t test___riscv_vid_v_u16mf4_mu(vbool64_t mask,vuint16mf4_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u16mf4_mu(mask,maskedoff,32); +} + + +vuint16mf2_t test___riscv_vid_v_u16mf2_mu(vbool32_t mask,vuint16mf2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u16mf2_mu(mask,maskedoff,32); +} + + +vuint16m1_t test___riscv_vid_v_u16m1_mu(vbool16_t mask,vuint16m1_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u16m1_mu(mask,maskedoff,32); +} + + +vuint16m2_t test___riscv_vid_v_u16m2_mu(vbool8_t mask,vuint16m2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u16m2_mu(mask,maskedoff,32); +} + + +vuint16m4_t test___riscv_vid_v_u16m4_mu(vbool4_t mask,vuint16m4_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u16m4_mu(mask,maskedoff,32); +} + + +vuint16m8_t test___riscv_vid_v_u16m8_mu(vbool2_t mask,vuint16m8_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u16m8_mu(mask,maskedoff,32); +} + + +vuint32mf2_t test___riscv_vid_v_u32mf2_mu(vbool64_t mask,vuint32mf2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u32mf2_mu(mask,maskedoff,32); +} + + +vuint32m1_t test___riscv_vid_v_u32m1_mu(vbool32_t mask,vuint32m1_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u32m1_mu(mask,maskedoff,32); +} + + +vuint32m2_t test___riscv_vid_v_u32m2_mu(vbool16_t mask,vuint32m2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u32m2_mu(mask,maskedoff,32); +} + + +vuint32m4_t test___riscv_vid_v_u32m4_mu(vbool8_t mask,vuint32m4_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u32m4_mu(mask,maskedoff,32); +} + + +vuint32m8_t test___riscv_vid_v_u32m8_mu(vbool4_t mask,vuint32m8_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u32m8_mu(mask,maskedoff,32); +} + + +vuint64m1_t test___riscv_vid_v_u64m1_mu(vbool64_t mask,vuint64m1_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u64m1_mu(mask,maskedoff,32); +} + + +vuint64m2_t test___riscv_vid_v_u64m2_mu(vbool32_t mask,vuint64m2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u64m2_mu(mask,maskedoff,32); +} + + +vuint64m4_t test___riscv_vid_v_u64m4_mu(vbool16_t mask,vuint64m4_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u64m4_mu(mask,maskedoff,32); +} + + +vuint64m8_t test___riscv_vid_v_u64m8_mu(vbool8_t mask,vuint64m8_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u64m8_mu(mask,maskedoff,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vid_v_tu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vid_v_tu-1.c new file mode 100644 index 00000000000..4b0f6887a77 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vid_v_tu-1.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vid_v_u8mf8_tu(vuint8mf8_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8mf8_tu(maskedoff,vl); +} + + +vuint8mf4_t test___riscv_vid_v_u8mf4_tu(vuint8mf4_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8mf4_tu(maskedoff,vl); +} + + +vuint8mf2_t test___riscv_vid_v_u8mf2_tu(vuint8mf2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8mf2_tu(maskedoff,vl); +} + + +vuint8m1_t test___riscv_vid_v_u8m1_tu(vuint8m1_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8m1_tu(maskedoff,vl); +} + + +vuint8m2_t test___riscv_vid_v_u8m2_tu(vuint8m2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8m2_tu(maskedoff,vl); +} + + +vuint8m4_t test___riscv_vid_v_u8m4_tu(vuint8m4_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8m4_tu(maskedoff,vl); +} + + +vuint8m8_t test___riscv_vid_v_u8m8_tu(vuint8m8_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8m8_tu(maskedoff,vl); +} + + +vuint16mf4_t test___riscv_vid_v_u16mf4_tu(vuint16mf4_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u16mf4_tu(maskedoff,vl); +} + + +vuint16mf2_t test___riscv_vid_v_u16mf2_tu(vuint16mf2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u16mf2_tu(maskedoff,vl); +} + + +vuint16m1_t test___riscv_vid_v_u16m1_tu(vuint16m1_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u16m1_tu(maskedoff,vl); +} + + +vuint16m2_t test___riscv_vid_v_u16m2_tu(vuint16m2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u16m2_tu(maskedoff,vl); +} + + +vuint16m4_t test___riscv_vid_v_u16m4_tu(vuint16m4_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u16m4_tu(maskedoff,vl); +} + + +vuint16m8_t test___riscv_vid_v_u16m8_tu(vuint16m8_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u16m8_tu(maskedoff,vl); +} + + +vuint32mf2_t test___riscv_vid_v_u32mf2_tu(vuint32mf2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u32mf2_tu(maskedoff,vl); +} + + +vuint32m1_t test___riscv_vid_v_u32m1_tu(vuint32m1_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u32m1_tu(maskedoff,vl); +} + + +vuint32m2_t test___riscv_vid_v_u32m2_tu(vuint32m2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u32m2_tu(maskedoff,vl); +} + + +vuint32m4_t test___riscv_vid_v_u32m4_tu(vuint32m4_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u32m4_tu(maskedoff,vl); +} + + +vuint32m8_t test___riscv_vid_v_u32m8_tu(vuint32m8_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u32m8_tu(maskedoff,vl); +} + + +vuint64m1_t test___riscv_vid_v_u64m1_tu(vuint64m1_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u64m1_tu(maskedoff,vl); +} + + +vuint64m2_t test___riscv_vid_v_u64m2_tu(vuint64m2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u64m2_tu(maskedoff,vl); +} + + +vuint64m4_t test___riscv_vid_v_u64m4_tu(vuint64m4_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u64m4_tu(maskedoff,vl); +} + + +vuint64m8_t test___riscv_vid_v_u64m8_tu(vuint64m8_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u64m8_tu(maskedoff,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vid_v_tu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vid_v_tu-2.c new file mode 100644 index 00000000000..b2b61013dc6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vid_v_tu-2.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vid_v_u8mf8_tu(vuint8mf8_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8mf8_tu(maskedoff,31); +} + + +vuint8mf4_t test___riscv_vid_v_u8mf4_tu(vuint8mf4_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8mf4_tu(maskedoff,31); +} + + +vuint8mf2_t test___riscv_vid_v_u8mf2_tu(vuint8mf2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8mf2_tu(maskedoff,31); +} + + +vuint8m1_t test___riscv_vid_v_u8m1_tu(vuint8m1_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8m1_tu(maskedoff,31); +} + + +vuint8m2_t test___riscv_vid_v_u8m2_tu(vuint8m2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8m2_tu(maskedoff,31); +} + + +vuint8m4_t test___riscv_vid_v_u8m4_tu(vuint8m4_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8m4_tu(maskedoff,31); +} + + +vuint8m8_t test___riscv_vid_v_u8m8_tu(vuint8m8_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8m8_tu(maskedoff,31); +} + + +vuint16mf4_t test___riscv_vid_v_u16mf4_tu(vuint16mf4_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u16mf4_tu(maskedoff,31); +} + + +vuint16mf2_t test___riscv_vid_v_u16mf2_tu(vuint16mf2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u16mf2_tu(maskedoff,31); +} + + +vuint16m1_t test___riscv_vid_v_u16m1_tu(vuint16m1_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u16m1_tu(maskedoff,31); +} + + +vuint16m2_t test___riscv_vid_v_u16m2_tu(vuint16m2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u16m2_tu(maskedoff,31); +} + + +vuint16m4_t test___riscv_vid_v_u16m4_tu(vuint16m4_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u16m4_tu(maskedoff,31); +} + + +vuint16m8_t test___riscv_vid_v_u16m8_tu(vuint16m8_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u16m8_tu(maskedoff,31); +} + + +vuint32mf2_t test___riscv_vid_v_u32mf2_tu(vuint32mf2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u32mf2_tu(maskedoff,31); +} + + +vuint32m1_t test___riscv_vid_v_u32m1_tu(vuint32m1_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u32m1_tu(maskedoff,31); +} + + +vuint32m2_t test___riscv_vid_v_u32m2_tu(vuint32m2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u32m2_tu(maskedoff,31); +} + + +vuint32m4_t test___riscv_vid_v_u32m4_tu(vuint32m4_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u32m4_tu(maskedoff,31); +} + + +vuint32m8_t test___riscv_vid_v_u32m8_tu(vuint32m8_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u32m8_tu(maskedoff,31); +} + + +vuint64m1_t test___riscv_vid_v_u64m1_tu(vuint64m1_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u64m1_tu(maskedoff,31); +} + + +vuint64m2_t test___riscv_vid_v_u64m2_tu(vuint64m2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u64m2_tu(maskedoff,31); +} + + +vuint64m4_t test___riscv_vid_v_u64m4_tu(vuint64m4_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u64m4_tu(maskedoff,31); +} + + +vuint64m8_t test___riscv_vid_v_u64m8_tu(vuint64m8_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u64m8_tu(maskedoff,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vid_v_tu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vid_v_tu-3.c new file mode 100644 index 00000000000..cb33afdffab --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vid_v_tu-3.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vid_v_u8mf8_tu(vuint8mf8_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8mf8_tu(maskedoff,32); +} + + +vuint8mf4_t test___riscv_vid_v_u8mf4_tu(vuint8mf4_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8mf4_tu(maskedoff,32); +} + + +vuint8mf2_t test___riscv_vid_v_u8mf2_tu(vuint8mf2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8mf2_tu(maskedoff,32); +} + + +vuint8m1_t test___riscv_vid_v_u8m1_tu(vuint8m1_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8m1_tu(maskedoff,32); +} + + +vuint8m2_t test___riscv_vid_v_u8m2_tu(vuint8m2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8m2_tu(maskedoff,32); +} + + +vuint8m4_t test___riscv_vid_v_u8m4_tu(vuint8m4_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8m4_tu(maskedoff,32); +} + + +vuint8m8_t test___riscv_vid_v_u8m8_tu(vuint8m8_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8m8_tu(maskedoff,32); +} + + +vuint16mf4_t test___riscv_vid_v_u16mf4_tu(vuint16mf4_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u16mf4_tu(maskedoff,32); +} + + +vuint16mf2_t test___riscv_vid_v_u16mf2_tu(vuint16mf2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u16mf2_tu(maskedoff,32); +} + + +vuint16m1_t test___riscv_vid_v_u16m1_tu(vuint16m1_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u16m1_tu(maskedoff,32); +} + + +vuint16m2_t test___riscv_vid_v_u16m2_tu(vuint16m2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u16m2_tu(maskedoff,32); +} + + +vuint16m4_t test___riscv_vid_v_u16m4_tu(vuint16m4_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u16m4_tu(maskedoff,32); +} + + +vuint16m8_t test___riscv_vid_v_u16m8_tu(vuint16m8_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u16m8_tu(maskedoff,32); +} + + +vuint32mf2_t test___riscv_vid_v_u32mf2_tu(vuint32mf2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u32mf2_tu(maskedoff,32); +} + + +vuint32m1_t test___riscv_vid_v_u32m1_tu(vuint32m1_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u32m1_tu(maskedoff,32); +} + + +vuint32m2_t test___riscv_vid_v_u32m2_tu(vuint32m2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u32m2_tu(maskedoff,32); +} + + +vuint32m4_t test___riscv_vid_v_u32m4_tu(vuint32m4_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u32m4_tu(maskedoff,32); +} + + +vuint32m8_t test___riscv_vid_v_u32m8_tu(vuint32m8_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u32m8_tu(maskedoff,32); +} + + +vuint64m1_t test___riscv_vid_v_u64m1_tu(vuint64m1_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u64m1_tu(maskedoff,32); +} + + +vuint64m2_t test___riscv_vid_v_u64m2_tu(vuint64m2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u64m2_tu(maskedoff,32); +} + + +vuint64m4_t test___riscv_vid_v_u64m4_tu(vuint64m4_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u64m4_tu(maskedoff,32); +} + + +vuint64m8_t test___riscv_vid_v_u64m8_tu(vuint64m8_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u64m8_tu(maskedoff,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vid_v_tum-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vid_v_tum-1.c new file mode 100644 index 00000000000..17492ac6fd3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vid_v_tum-1.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vid_v_u8mf8_tum(vbool64_t mask,vuint8mf8_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8mf8_tum(mask,maskedoff,vl); +} + + +vuint8mf4_t test___riscv_vid_v_u8mf4_tum(vbool32_t mask,vuint8mf4_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8mf4_tum(mask,maskedoff,vl); +} + + +vuint8mf2_t test___riscv_vid_v_u8mf2_tum(vbool16_t mask,vuint8mf2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8mf2_tum(mask,maskedoff,vl); +} + + +vuint8m1_t test___riscv_vid_v_u8m1_tum(vbool8_t mask,vuint8m1_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8m1_tum(mask,maskedoff,vl); +} + + +vuint8m2_t test___riscv_vid_v_u8m2_tum(vbool4_t mask,vuint8m2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8m2_tum(mask,maskedoff,vl); +} + + +vuint8m4_t test___riscv_vid_v_u8m4_tum(vbool2_t mask,vuint8m4_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8m4_tum(mask,maskedoff,vl); +} + + +vuint8m8_t test___riscv_vid_v_u8m8_tum(vbool1_t mask,vuint8m8_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8m8_tum(mask,maskedoff,vl); +} + + +vuint16mf4_t test___riscv_vid_v_u16mf4_tum(vbool64_t mask,vuint16mf4_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u16mf4_tum(mask,maskedoff,vl); +} + + +vuint16mf2_t test___riscv_vid_v_u16mf2_tum(vbool32_t mask,vuint16mf2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u16mf2_tum(mask,maskedoff,vl); +} + + +vuint16m1_t test___riscv_vid_v_u16m1_tum(vbool16_t mask,vuint16m1_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u16m1_tum(mask,maskedoff,vl); +} + + +vuint16m2_t test___riscv_vid_v_u16m2_tum(vbool8_t mask,vuint16m2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u16m2_tum(mask,maskedoff,vl); +} + + +vuint16m4_t test___riscv_vid_v_u16m4_tum(vbool4_t mask,vuint16m4_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u16m4_tum(mask,maskedoff,vl); +} + + +vuint16m8_t test___riscv_vid_v_u16m8_tum(vbool2_t mask,vuint16m8_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u16m8_tum(mask,maskedoff,vl); +} + + +vuint32mf2_t test___riscv_vid_v_u32mf2_tum(vbool64_t mask,vuint32mf2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u32mf2_tum(mask,maskedoff,vl); +} + + +vuint32m1_t test___riscv_vid_v_u32m1_tum(vbool32_t mask,vuint32m1_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u32m1_tum(mask,maskedoff,vl); +} + + +vuint32m2_t test___riscv_vid_v_u32m2_tum(vbool16_t mask,vuint32m2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u32m2_tum(mask,maskedoff,vl); +} + + +vuint32m4_t test___riscv_vid_v_u32m4_tum(vbool8_t mask,vuint32m4_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u32m4_tum(mask,maskedoff,vl); +} + + +vuint32m8_t test___riscv_vid_v_u32m8_tum(vbool4_t mask,vuint32m8_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u32m8_tum(mask,maskedoff,vl); +} + + +vuint64m1_t test___riscv_vid_v_u64m1_tum(vbool64_t mask,vuint64m1_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u64m1_tum(mask,maskedoff,vl); +} + + +vuint64m2_t test___riscv_vid_v_u64m2_tum(vbool32_t mask,vuint64m2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u64m2_tum(mask,maskedoff,vl); +} + + +vuint64m4_t test___riscv_vid_v_u64m4_tum(vbool16_t mask,vuint64m4_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u64m4_tum(mask,maskedoff,vl); +} + + +vuint64m8_t test___riscv_vid_v_u64m8_tum(vbool8_t mask,vuint64m8_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u64m8_tum(mask,maskedoff,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vid_v_tum-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vid_v_tum-2.c new file mode 100644 index 00000000000..958707454a9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vid_v_tum-2.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vid_v_u8mf8_tum(vbool64_t mask,vuint8mf8_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8mf8_tum(mask,maskedoff,31); +} + + +vuint8mf4_t test___riscv_vid_v_u8mf4_tum(vbool32_t mask,vuint8mf4_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8mf4_tum(mask,maskedoff,31); +} + + +vuint8mf2_t test___riscv_vid_v_u8mf2_tum(vbool16_t mask,vuint8mf2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8mf2_tum(mask,maskedoff,31); +} + + +vuint8m1_t test___riscv_vid_v_u8m1_tum(vbool8_t mask,vuint8m1_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8m1_tum(mask,maskedoff,31); +} + + +vuint8m2_t test___riscv_vid_v_u8m2_tum(vbool4_t mask,vuint8m2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8m2_tum(mask,maskedoff,31); +} + + +vuint8m4_t test___riscv_vid_v_u8m4_tum(vbool2_t mask,vuint8m4_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8m4_tum(mask,maskedoff,31); +} + + +vuint8m8_t test___riscv_vid_v_u8m8_tum(vbool1_t mask,vuint8m8_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8m8_tum(mask,maskedoff,31); +} + + +vuint16mf4_t test___riscv_vid_v_u16mf4_tum(vbool64_t mask,vuint16mf4_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u16mf4_tum(mask,maskedoff,31); +} + + +vuint16mf2_t test___riscv_vid_v_u16mf2_tum(vbool32_t mask,vuint16mf2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u16mf2_tum(mask,maskedoff,31); +} + + +vuint16m1_t test___riscv_vid_v_u16m1_tum(vbool16_t mask,vuint16m1_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u16m1_tum(mask,maskedoff,31); +} + + +vuint16m2_t test___riscv_vid_v_u16m2_tum(vbool8_t mask,vuint16m2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u16m2_tum(mask,maskedoff,31); +} + + +vuint16m4_t test___riscv_vid_v_u16m4_tum(vbool4_t mask,vuint16m4_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u16m4_tum(mask,maskedoff,31); +} + + +vuint16m8_t test___riscv_vid_v_u16m8_tum(vbool2_t mask,vuint16m8_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u16m8_tum(mask,maskedoff,31); +} + + +vuint32mf2_t test___riscv_vid_v_u32mf2_tum(vbool64_t mask,vuint32mf2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u32mf2_tum(mask,maskedoff,31); +} + + +vuint32m1_t test___riscv_vid_v_u32m1_tum(vbool32_t mask,vuint32m1_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u32m1_tum(mask,maskedoff,31); +} + + +vuint32m2_t test___riscv_vid_v_u32m2_tum(vbool16_t mask,vuint32m2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u32m2_tum(mask,maskedoff,31); +} + + +vuint32m4_t test___riscv_vid_v_u32m4_tum(vbool8_t mask,vuint32m4_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u32m4_tum(mask,maskedoff,31); +} + + +vuint32m8_t test___riscv_vid_v_u32m8_tum(vbool4_t mask,vuint32m8_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u32m8_tum(mask,maskedoff,31); +} + + +vuint64m1_t test___riscv_vid_v_u64m1_tum(vbool64_t mask,vuint64m1_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u64m1_tum(mask,maskedoff,31); +} + + +vuint64m2_t test___riscv_vid_v_u64m2_tum(vbool32_t mask,vuint64m2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u64m2_tum(mask,maskedoff,31); +} + + +vuint64m4_t test___riscv_vid_v_u64m4_tum(vbool16_t mask,vuint64m4_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u64m4_tum(mask,maskedoff,31); +} + + +vuint64m8_t test___riscv_vid_v_u64m8_tum(vbool8_t mask,vuint64m8_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u64m8_tum(mask,maskedoff,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vid_v_tum-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vid_v_tum-3.c new file mode 100644 index 00000000000..5bea2a89404 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vid_v_tum-3.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vid_v_u8mf8_tum(vbool64_t mask,vuint8mf8_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8mf8_tum(mask,maskedoff,32); +} + + +vuint8mf4_t test___riscv_vid_v_u8mf4_tum(vbool32_t mask,vuint8mf4_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8mf4_tum(mask,maskedoff,32); +} + + +vuint8mf2_t test___riscv_vid_v_u8mf2_tum(vbool16_t mask,vuint8mf2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8mf2_tum(mask,maskedoff,32); +} + + +vuint8m1_t test___riscv_vid_v_u8m1_tum(vbool8_t mask,vuint8m1_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8m1_tum(mask,maskedoff,32); +} + + +vuint8m2_t test___riscv_vid_v_u8m2_tum(vbool4_t mask,vuint8m2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8m2_tum(mask,maskedoff,32); +} + + +vuint8m4_t test___riscv_vid_v_u8m4_tum(vbool2_t mask,vuint8m4_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8m4_tum(mask,maskedoff,32); +} + + +vuint8m8_t test___riscv_vid_v_u8m8_tum(vbool1_t mask,vuint8m8_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8m8_tum(mask,maskedoff,32); +} + + +vuint16mf4_t test___riscv_vid_v_u16mf4_tum(vbool64_t mask,vuint16mf4_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u16mf4_tum(mask,maskedoff,32); +} + + +vuint16mf2_t test___riscv_vid_v_u16mf2_tum(vbool32_t mask,vuint16mf2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u16mf2_tum(mask,maskedoff,32); +} + + +vuint16m1_t test___riscv_vid_v_u16m1_tum(vbool16_t mask,vuint16m1_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u16m1_tum(mask,maskedoff,32); +} + + +vuint16m2_t test___riscv_vid_v_u16m2_tum(vbool8_t mask,vuint16m2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u16m2_tum(mask,maskedoff,32); +} + + +vuint16m4_t test___riscv_vid_v_u16m4_tum(vbool4_t mask,vuint16m4_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u16m4_tum(mask,maskedoff,32); +} + + +vuint16m8_t test___riscv_vid_v_u16m8_tum(vbool2_t mask,vuint16m8_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u16m8_tum(mask,maskedoff,32); +} + + +vuint32mf2_t test___riscv_vid_v_u32mf2_tum(vbool64_t mask,vuint32mf2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u32mf2_tum(mask,maskedoff,32); +} + + +vuint32m1_t test___riscv_vid_v_u32m1_tum(vbool32_t mask,vuint32m1_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u32m1_tum(mask,maskedoff,32); +} + + +vuint32m2_t test___riscv_vid_v_u32m2_tum(vbool16_t mask,vuint32m2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u32m2_tum(mask,maskedoff,32); +} + + +vuint32m4_t test___riscv_vid_v_u32m4_tum(vbool8_t mask,vuint32m4_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u32m4_tum(mask,maskedoff,32); +} + + +vuint32m8_t test___riscv_vid_v_u32m8_tum(vbool4_t mask,vuint32m8_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u32m8_tum(mask,maskedoff,32); +} + + +vuint64m1_t test___riscv_vid_v_u64m1_tum(vbool64_t mask,vuint64m1_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u64m1_tum(mask,maskedoff,32); +} + + +vuint64m2_t test___riscv_vid_v_u64m2_tum(vbool32_t mask,vuint64m2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u64m2_tum(mask,maskedoff,32); +} + + +vuint64m4_t test___riscv_vid_v_u64m4_tum(vbool16_t mask,vuint64m4_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u64m4_tum(mask,maskedoff,32); +} + + +vuint64m8_t test___riscv_vid_v_u64m8_tum(vbool8_t mask,vuint64m8_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u64m8_tum(mask,maskedoff,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vid_v_tumu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vid_v_tumu-1.c new file mode 100644 index 00000000000..dec9c9ea3c5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vid_v_tumu-1.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vid_v_u8mf8_tumu(vbool64_t mask,vuint8mf8_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8mf8_tumu(mask,maskedoff,vl); +} + + +vuint8mf4_t test___riscv_vid_v_u8mf4_tumu(vbool32_t mask,vuint8mf4_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8mf4_tumu(mask,maskedoff,vl); +} + + +vuint8mf2_t test___riscv_vid_v_u8mf2_tumu(vbool16_t mask,vuint8mf2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8mf2_tumu(mask,maskedoff,vl); +} + + +vuint8m1_t test___riscv_vid_v_u8m1_tumu(vbool8_t mask,vuint8m1_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8m1_tumu(mask,maskedoff,vl); +} + + +vuint8m2_t test___riscv_vid_v_u8m2_tumu(vbool4_t mask,vuint8m2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8m2_tumu(mask,maskedoff,vl); +} + + +vuint8m4_t test___riscv_vid_v_u8m4_tumu(vbool2_t mask,vuint8m4_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8m4_tumu(mask,maskedoff,vl); +} + + +vuint8m8_t test___riscv_vid_v_u8m8_tumu(vbool1_t mask,vuint8m8_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8m8_tumu(mask,maskedoff,vl); +} + + +vuint16mf4_t test___riscv_vid_v_u16mf4_tumu(vbool64_t mask,vuint16mf4_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u16mf4_tumu(mask,maskedoff,vl); +} + + +vuint16mf2_t test___riscv_vid_v_u16mf2_tumu(vbool32_t mask,vuint16mf2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u16mf2_tumu(mask,maskedoff,vl); +} + + +vuint16m1_t test___riscv_vid_v_u16m1_tumu(vbool16_t mask,vuint16m1_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u16m1_tumu(mask,maskedoff,vl); +} + + +vuint16m2_t test___riscv_vid_v_u16m2_tumu(vbool8_t mask,vuint16m2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u16m2_tumu(mask,maskedoff,vl); +} + + +vuint16m4_t test___riscv_vid_v_u16m4_tumu(vbool4_t mask,vuint16m4_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u16m4_tumu(mask,maskedoff,vl); +} + + +vuint16m8_t test___riscv_vid_v_u16m8_tumu(vbool2_t mask,vuint16m8_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u16m8_tumu(mask,maskedoff,vl); +} + + +vuint32mf2_t test___riscv_vid_v_u32mf2_tumu(vbool64_t mask,vuint32mf2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u32mf2_tumu(mask,maskedoff,vl); +} + + +vuint32m1_t test___riscv_vid_v_u32m1_tumu(vbool32_t mask,vuint32m1_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u32m1_tumu(mask,maskedoff,vl); +} + + +vuint32m2_t test___riscv_vid_v_u32m2_tumu(vbool16_t mask,vuint32m2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u32m2_tumu(mask,maskedoff,vl); +} + + +vuint32m4_t test___riscv_vid_v_u32m4_tumu(vbool8_t mask,vuint32m4_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u32m4_tumu(mask,maskedoff,vl); +} + + +vuint32m8_t test___riscv_vid_v_u32m8_tumu(vbool4_t mask,vuint32m8_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u32m8_tumu(mask,maskedoff,vl); +} + + +vuint64m1_t test___riscv_vid_v_u64m1_tumu(vbool64_t mask,vuint64m1_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u64m1_tumu(mask,maskedoff,vl); +} + + +vuint64m2_t test___riscv_vid_v_u64m2_tumu(vbool32_t mask,vuint64m2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u64m2_tumu(mask,maskedoff,vl); +} + + +vuint64m4_t test___riscv_vid_v_u64m4_tumu(vbool16_t mask,vuint64m4_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u64m4_tumu(mask,maskedoff,vl); +} + + +vuint64m8_t test___riscv_vid_v_u64m8_tumu(vbool8_t mask,vuint64m8_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u64m8_tumu(mask,maskedoff,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vid_v_tumu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vid_v_tumu-2.c new file mode 100644 index 00000000000..969c16005f1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vid_v_tumu-2.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vid_v_u8mf8_tumu(vbool64_t mask,vuint8mf8_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8mf8_tumu(mask,maskedoff,31); +} + + +vuint8mf4_t test___riscv_vid_v_u8mf4_tumu(vbool32_t mask,vuint8mf4_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8mf4_tumu(mask,maskedoff,31); +} + + +vuint8mf2_t test___riscv_vid_v_u8mf2_tumu(vbool16_t mask,vuint8mf2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8mf2_tumu(mask,maskedoff,31); +} + + +vuint8m1_t test___riscv_vid_v_u8m1_tumu(vbool8_t mask,vuint8m1_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8m1_tumu(mask,maskedoff,31); +} + + +vuint8m2_t test___riscv_vid_v_u8m2_tumu(vbool4_t mask,vuint8m2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8m2_tumu(mask,maskedoff,31); +} + + +vuint8m4_t test___riscv_vid_v_u8m4_tumu(vbool2_t mask,vuint8m4_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8m4_tumu(mask,maskedoff,31); +} + + +vuint8m8_t test___riscv_vid_v_u8m8_tumu(vbool1_t mask,vuint8m8_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8m8_tumu(mask,maskedoff,31); +} + + +vuint16mf4_t test___riscv_vid_v_u16mf4_tumu(vbool64_t mask,vuint16mf4_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u16mf4_tumu(mask,maskedoff,31); +} + + +vuint16mf2_t test___riscv_vid_v_u16mf2_tumu(vbool32_t mask,vuint16mf2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u16mf2_tumu(mask,maskedoff,31); +} + + +vuint16m1_t test___riscv_vid_v_u16m1_tumu(vbool16_t mask,vuint16m1_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u16m1_tumu(mask,maskedoff,31); +} + + +vuint16m2_t test___riscv_vid_v_u16m2_tumu(vbool8_t mask,vuint16m2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u16m2_tumu(mask,maskedoff,31); +} + + +vuint16m4_t test___riscv_vid_v_u16m4_tumu(vbool4_t mask,vuint16m4_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u16m4_tumu(mask,maskedoff,31); +} + + +vuint16m8_t test___riscv_vid_v_u16m8_tumu(vbool2_t mask,vuint16m8_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u16m8_tumu(mask,maskedoff,31); +} + + +vuint32mf2_t test___riscv_vid_v_u32mf2_tumu(vbool64_t mask,vuint32mf2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u32mf2_tumu(mask,maskedoff,31); +} + + +vuint32m1_t test___riscv_vid_v_u32m1_tumu(vbool32_t mask,vuint32m1_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u32m1_tumu(mask,maskedoff,31); +} + + +vuint32m2_t test___riscv_vid_v_u32m2_tumu(vbool16_t mask,vuint32m2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u32m2_tumu(mask,maskedoff,31); +} + + +vuint32m4_t test___riscv_vid_v_u32m4_tumu(vbool8_t mask,vuint32m4_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u32m4_tumu(mask,maskedoff,31); +} + + +vuint32m8_t test___riscv_vid_v_u32m8_tumu(vbool4_t mask,vuint32m8_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u32m8_tumu(mask,maskedoff,31); +} + + +vuint64m1_t test___riscv_vid_v_u64m1_tumu(vbool64_t mask,vuint64m1_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u64m1_tumu(mask,maskedoff,31); +} + + +vuint64m2_t test___riscv_vid_v_u64m2_tumu(vbool32_t mask,vuint64m2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u64m2_tumu(mask,maskedoff,31); +} + + +vuint64m4_t test___riscv_vid_v_u64m4_tumu(vbool16_t mask,vuint64m4_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u64m4_tumu(mask,maskedoff,31); +} + + +vuint64m8_t test___riscv_vid_v_u64m8_tumu(vbool8_t mask,vuint64m8_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u64m8_tumu(mask,maskedoff,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vid_v_tumu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vid_v_tumu-3.c new file mode 100644 index 00000000000..60e8b26bac0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vid_v_tumu-3.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_vid_v_u8mf8_tumu(vbool64_t mask,vuint8mf8_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8mf8_tumu(mask,maskedoff,32); +} + + +vuint8mf4_t test___riscv_vid_v_u8mf4_tumu(vbool32_t mask,vuint8mf4_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8mf4_tumu(mask,maskedoff,32); +} + + +vuint8mf2_t test___riscv_vid_v_u8mf2_tumu(vbool16_t mask,vuint8mf2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8mf2_tumu(mask,maskedoff,32); +} + + +vuint8m1_t test___riscv_vid_v_u8m1_tumu(vbool8_t mask,vuint8m1_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8m1_tumu(mask,maskedoff,32); +} + + +vuint8m2_t test___riscv_vid_v_u8m2_tumu(vbool4_t mask,vuint8m2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8m2_tumu(mask,maskedoff,32); +} + + +vuint8m4_t test___riscv_vid_v_u8m4_tumu(vbool2_t mask,vuint8m4_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8m4_tumu(mask,maskedoff,32); +} + + +vuint8m8_t test___riscv_vid_v_u8m8_tumu(vbool1_t mask,vuint8m8_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u8m8_tumu(mask,maskedoff,32); +} + + +vuint16mf4_t test___riscv_vid_v_u16mf4_tumu(vbool64_t mask,vuint16mf4_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u16mf4_tumu(mask,maskedoff,32); +} + + +vuint16mf2_t test___riscv_vid_v_u16mf2_tumu(vbool32_t mask,vuint16mf2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u16mf2_tumu(mask,maskedoff,32); +} + + +vuint16m1_t test___riscv_vid_v_u16m1_tumu(vbool16_t mask,vuint16m1_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u16m1_tumu(mask,maskedoff,32); +} + + +vuint16m2_t test___riscv_vid_v_u16m2_tumu(vbool8_t mask,vuint16m2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u16m2_tumu(mask,maskedoff,32); +} + + +vuint16m4_t test___riscv_vid_v_u16m4_tumu(vbool4_t mask,vuint16m4_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u16m4_tumu(mask,maskedoff,32); +} + + +vuint16m8_t test___riscv_vid_v_u16m8_tumu(vbool2_t mask,vuint16m8_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u16m8_tumu(mask,maskedoff,32); +} + + +vuint32mf2_t test___riscv_vid_v_u32mf2_tumu(vbool64_t mask,vuint32mf2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u32mf2_tumu(mask,maskedoff,32); +} + + +vuint32m1_t test___riscv_vid_v_u32m1_tumu(vbool32_t mask,vuint32m1_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u32m1_tumu(mask,maskedoff,32); +} + + +vuint32m2_t test___riscv_vid_v_u32m2_tumu(vbool16_t mask,vuint32m2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u32m2_tumu(mask,maskedoff,32); +} + + +vuint32m4_t test___riscv_vid_v_u32m4_tumu(vbool8_t mask,vuint32m4_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u32m4_tumu(mask,maskedoff,32); +} + + +vuint32m8_t test___riscv_vid_v_u32m8_tumu(vbool4_t mask,vuint32m8_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u32m8_tumu(mask,maskedoff,32); +} + + +vuint64m1_t test___riscv_vid_v_u64m1_tumu(vbool64_t mask,vuint64m1_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u64m1_tumu(mask,maskedoff,32); +} + + +vuint64m2_t test___riscv_vid_v_u64m2_tumu(vbool32_t mask,vuint64m2_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u64m2_tumu(mask,maskedoff,32); +} + + +vuint64m4_t test___riscv_vid_v_u64m4_tumu(vbool16_t mask,vuint64m4_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u64m4_tumu(mask,maskedoff,32); +} + + +vuint64m8_t test___riscv_vid_v_u64m8_tumu(vbool8_t mask,vuint64m8_t maskedoff,size_t vl) +{ + return __riscv_vid_v_u64m8_tumu(mask,maskedoff,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vid\.v\s+v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/viota_m_m-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/viota_m_m-1.c new file mode 100644 index 00000000000..d2dc22bc2de --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/viota_m_m-1.c @@ -0,0 +1,314 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_viota_m_u8mf8(vbool64_t op1,size_t vl) +{ + return __riscv_viota_m_u8mf8(op1,vl); +} + + +vuint8mf4_t test___riscv_viota_m_u8mf4(vbool32_t op1,size_t vl) +{ + return __riscv_viota_m_u8mf4(op1,vl); +} + + +vuint8mf2_t test___riscv_viota_m_u8mf2(vbool16_t op1,size_t vl) +{ + return __riscv_viota_m_u8mf2(op1,vl); +} + + +vuint8m1_t test___riscv_viota_m_u8m1(vbool8_t op1,size_t vl) +{ + return __riscv_viota_m_u8m1(op1,vl); +} + + +vuint8m2_t test___riscv_viota_m_u8m2(vbool4_t op1,size_t vl) +{ + return __riscv_viota_m_u8m2(op1,vl); +} + + +vuint8m4_t test___riscv_viota_m_u8m4(vbool2_t op1,size_t vl) +{ + return __riscv_viota_m_u8m4(op1,vl); +} + + +vuint8m8_t test___riscv_viota_m_u8m8(vbool1_t op1,size_t vl) +{ + return __riscv_viota_m_u8m8(op1,vl); +} + + +vuint16mf4_t test___riscv_viota_m_u16mf4(vbool64_t op1,size_t vl) +{ + return __riscv_viota_m_u16mf4(op1,vl); +} + + +vuint16mf2_t test___riscv_viota_m_u16mf2(vbool32_t op1,size_t vl) +{ + return __riscv_viota_m_u16mf2(op1,vl); +} + + +vuint16m1_t test___riscv_viota_m_u16m1(vbool16_t op1,size_t vl) +{ + return __riscv_viota_m_u16m1(op1,vl); +} + + +vuint16m2_t test___riscv_viota_m_u16m2(vbool8_t op1,size_t vl) +{ + return __riscv_viota_m_u16m2(op1,vl); +} + + +vuint16m4_t test___riscv_viota_m_u16m4(vbool4_t op1,size_t vl) +{ + return __riscv_viota_m_u16m4(op1,vl); +} + + +vuint16m8_t test___riscv_viota_m_u16m8(vbool2_t op1,size_t vl) +{ + return __riscv_viota_m_u16m8(op1,vl); +} + + +vuint32mf2_t test___riscv_viota_m_u32mf2(vbool64_t op1,size_t vl) +{ + return __riscv_viota_m_u32mf2(op1,vl); +} + + +vuint32m1_t test___riscv_viota_m_u32m1(vbool32_t op1,size_t vl) +{ + return __riscv_viota_m_u32m1(op1,vl); +} + + +vuint32m2_t test___riscv_viota_m_u32m2(vbool16_t op1,size_t vl) +{ + return __riscv_viota_m_u32m2(op1,vl); +} + + +vuint32m4_t test___riscv_viota_m_u32m4(vbool8_t op1,size_t vl) +{ + return __riscv_viota_m_u32m4(op1,vl); +} + + +vuint32m8_t test___riscv_viota_m_u32m8(vbool4_t op1,size_t vl) +{ + return __riscv_viota_m_u32m8(op1,vl); +} + + +vuint64m1_t test___riscv_viota_m_u64m1(vbool64_t op1,size_t vl) +{ + return __riscv_viota_m_u64m1(op1,vl); +} + + +vuint64m2_t test___riscv_viota_m_u64m2(vbool32_t op1,size_t vl) +{ + return __riscv_viota_m_u64m2(op1,vl); +} + + +vuint64m4_t test___riscv_viota_m_u64m4(vbool16_t op1,size_t vl) +{ + return __riscv_viota_m_u64m4(op1,vl); +} + + +vuint64m8_t test___riscv_viota_m_u64m8(vbool8_t op1,size_t vl) +{ + return __riscv_viota_m_u64m8(op1,vl); +} + + +vuint8mf8_t test___riscv_viota_m_u8mf8_m(vbool64_t mask,vbool64_t op1,size_t vl) +{ + return __riscv_viota_m_u8mf8_m(mask,op1,vl); +} + + +vuint8mf4_t test___riscv_viota_m_u8mf4_m(vbool32_t mask,vbool32_t op1,size_t vl) +{ + return __riscv_viota_m_u8mf4_m(mask,op1,vl); +} + + +vuint8mf2_t test___riscv_viota_m_u8mf2_m(vbool16_t mask,vbool16_t op1,size_t vl) +{ + return __riscv_viota_m_u8mf2_m(mask,op1,vl); +} + + +vuint8m1_t test___riscv_viota_m_u8m1_m(vbool8_t mask,vbool8_t op1,size_t vl) +{ + return __riscv_viota_m_u8m1_m(mask,op1,vl); +} + + +vuint8m2_t test___riscv_viota_m_u8m2_m(vbool4_t mask,vbool4_t op1,size_t vl) +{ + return __riscv_viota_m_u8m2_m(mask,op1,vl); +} + + +vuint8m4_t test___riscv_viota_m_u8m4_m(vbool2_t mask,vbool2_t op1,size_t vl) +{ + return __riscv_viota_m_u8m4_m(mask,op1,vl); +} + + +vuint8m8_t test___riscv_viota_m_u8m8_m(vbool1_t mask,vbool1_t op1,size_t vl) +{ + return __riscv_viota_m_u8m8_m(mask,op1,vl); +} + + +vuint16mf4_t test___riscv_viota_m_u16mf4_m(vbool64_t mask,vbool64_t op1,size_t vl) +{ + return __riscv_viota_m_u16mf4_m(mask,op1,vl); +} + + +vuint16mf2_t test___riscv_viota_m_u16mf2_m(vbool32_t mask,vbool32_t op1,size_t vl) +{ + return __riscv_viota_m_u16mf2_m(mask,op1,vl); +} + + +vuint16m1_t test___riscv_viota_m_u16m1_m(vbool16_t mask,vbool16_t op1,size_t vl) +{ + return __riscv_viota_m_u16m1_m(mask,op1,vl); +} + + +vuint16m2_t test___riscv_viota_m_u16m2_m(vbool8_t mask,vbool8_t op1,size_t vl) +{ + return __riscv_viota_m_u16m2_m(mask,op1,vl); +} + + +vuint16m4_t test___riscv_viota_m_u16m4_m(vbool4_t mask,vbool4_t op1,size_t vl) +{ + return __riscv_viota_m_u16m4_m(mask,op1,vl); +} + + +vuint16m8_t test___riscv_viota_m_u16m8_m(vbool2_t mask,vbool2_t op1,size_t vl) +{ + return __riscv_viota_m_u16m8_m(mask,op1,vl); +} + + +vuint32mf2_t test___riscv_viota_m_u32mf2_m(vbool64_t mask,vbool64_t op1,size_t vl) +{ + return __riscv_viota_m_u32mf2_m(mask,op1,vl); +} + + +vuint32m1_t test___riscv_viota_m_u32m1_m(vbool32_t mask,vbool32_t op1,size_t vl) +{ + return __riscv_viota_m_u32m1_m(mask,op1,vl); +} + + +vuint32m2_t test___riscv_viota_m_u32m2_m(vbool16_t mask,vbool16_t op1,size_t vl) +{ + return __riscv_viota_m_u32m2_m(mask,op1,vl); +} + + +vuint32m4_t test___riscv_viota_m_u32m4_m(vbool8_t mask,vbool8_t op1,size_t vl) +{ + return __riscv_viota_m_u32m4_m(mask,op1,vl); +} + + +vuint32m8_t test___riscv_viota_m_u32m8_m(vbool4_t mask,vbool4_t op1,size_t vl) +{ + return __riscv_viota_m_u32m8_m(mask,op1,vl); +} + + +vuint64m1_t test___riscv_viota_m_u64m1_m(vbool64_t mask,vbool64_t op1,size_t vl) +{ + return __riscv_viota_m_u64m1_m(mask,op1,vl); +} + + +vuint64m2_t test___riscv_viota_m_u64m2_m(vbool32_t mask,vbool32_t op1,size_t vl) +{ + return __riscv_viota_m_u64m2_m(mask,op1,vl); +} + + +vuint64m4_t test___riscv_viota_m_u64m4_m(vbool16_t mask,vbool16_t op1,size_t vl) +{ + return __riscv_viota_m_u64m4_m(mask,op1,vl); +} + + +vuint64m8_t test___riscv_viota_m_u64m8_m(vbool8_t mask,vbool8_t op1,size_t vl) +{ + return __riscv_viota_m_u64m8_m(mask,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/viota_m_m-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/viota_m_m-2.c new file mode 100644 index 00000000000..202e3f85b1d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/viota_m_m-2.c @@ -0,0 +1,314 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_viota_m_u8mf8(vbool64_t op1,size_t vl) +{ + return __riscv_viota_m_u8mf8(op1,31); +} + + +vuint8mf4_t test___riscv_viota_m_u8mf4(vbool32_t op1,size_t vl) +{ + return __riscv_viota_m_u8mf4(op1,31); +} + + +vuint8mf2_t test___riscv_viota_m_u8mf2(vbool16_t op1,size_t vl) +{ + return __riscv_viota_m_u8mf2(op1,31); +} + + +vuint8m1_t test___riscv_viota_m_u8m1(vbool8_t op1,size_t vl) +{ + return __riscv_viota_m_u8m1(op1,31); +} + + +vuint8m2_t test___riscv_viota_m_u8m2(vbool4_t op1,size_t vl) +{ + return __riscv_viota_m_u8m2(op1,31); +} + + +vuint8m4_t test___riscv_viota_m_u8m4(vbool2_t op1,size_t vl) +{ + return __riscv_viota_m_u8m4(op1,31); +} + + +vuint8m8_t test___riscv_viota_m_u8m8(vbool1_t op1,size_t vl) +{ + return __riscv_viota_m_u8m8(op1,31); +} + + +vuint16mf4_t test___riscv_viota_m_u16mf4(vbool64_t op1,size_t vl) +{ + return __riscv_viota_m_u16mf4(op1,31); +} + + +vuint16mf2_t test___riscv_viota_m_u16mf2(vbool32_t op1,size_t vl) +{ + return __riscv_viota_m_u16mf2(op1,31); +} + + +vuint16m1_t test___riscv_viota_m_u16m1(vbool16_t op1,size_t vl) +{ + return __riscv_viota_m_u16m1(op1,31); +} + + +vuint16m2_t test___riscv_viota_m_u16m2(vbool8_t op1,size_t vl) +{ + return __riscv_viota_m_u16m2(op1,31); +} + + +vuint16m4_t test___riscv_viota_m_u16m4(vbool4_t op1,size_t vl) +{ + return __riscv_viota_m_u16m4(op1,31); +} + + +vuint16m8_t test___riscv_viota_m_u16m8(vbool2_t op1,size_t vl) +{ + return __riscv_viota_m_u16m8(op1,31); +} + + +vuint32mf2_t test___riscv_viota_m_u32mf2(vbool64_t op1,size_t vl) +{ + return __riscv_viota_m_u32mf2(op1,31); +} + + +vuint32m1_t test___riscv_viota_m_u32m1(vbool32_t op1,size_t vl) +{ + return __riscv_viota_m_u32m1(op1,31); +} + + +vuint32m2_t test___riscv_viota_m_u32m2(vbool16_t op1,size_t vl) +{ + return __riscv_viota_m_u32m2(op1,31); +} + + +vuint32m4_t test___riscv_viota_m_u32m4(vbool8_t op1,size_t vl) +{ + return __riscv_viota_m_u32m4(op1,31); +} + + +vuint32m8_t test___riscv_viota_m_u32m8(vbool4_t op1,size_t vl) +{ + return __riscv_viota_m_u32m8(op1,31); +} + + +vuint64m1_t test___riscv_viota_m_u64m1(vbool64_t op1,size_t vl) +{ + return __riscv_viota_m_u64m1(op1,31); +} + + +vuint64m2_t test___riscv_viota_m_u64m2(vbool32_t op1,size_t vl) +{ + return __riscv_viota_m_u64m2(op1,31); +} + + +vuint64m4_t test___riscv_viota_m_u64m4(vbool16_t op1,size_t vl) +{ + return __riscv_viota_m_u64m4(op1,31); +} + + +vuint64m8_t test___riscv_viota_m_u64m8(vbool8_t op1,size_t vl) +{ + return __riscv_viota_m_u64m8(op1,31); +} + + +vuint8mf8_t test___riscv_viota_m_u8mf8_m(vbool64_t mask,vbool64_t op1,size_t vl) +{ + return __riscv_viota_m_u8mf8_m(mask,op1,31); +} + + +vuint8mf4_t test___riscv_viota_m_u8mf4_m(vbool32_t mask,vbool32_t op1,size_t vl) +{ + return __riscv_viota_m_u8mf4_m(mask,op1,31); +} + + +vuint8mf2_t test___riscv_viota_m_u8mf2_m(vbool16_t mask,vbool16_t op1,size_t vl) +{ + return __riscv_viota_m_u8mf2_m(mask,op1,31); +} + + +vuint8m1_t test___riscv_viota_m_u8m1_m(vbool8_t mask,vbool8_t op1,size_t vl) +{ + return __riscv_viota_m_u8m1_m(mask,op1,31); +} + + +vuint8m2_t test___riscv_viota_m_u8m2_m(vbool4_t mask,vbool4_t op1,size_t vl) +{ + return __riscv_viota_m_u8m2_m(mask,op1,31); +} + + +vuint8m4_t test___riscv_viota_m_u8m4_m(vbool2_t mask,vbool2_t op1,size_t vl) +{ + return __riscv_viota_m_u8m4_m(mask,op1,31); +} + + +vuint8m8_t test___riscv_viota_m_u8m8_m(vbool1_t mask,vbool1_t op1,size_t vl) +{ + return __riscv_viota_m_u8m8_m(mask,op1,31); +} + + +vuint16mf4_t test___riscv_viota_m_u16mf4_m(vbool64_t mask,vbool64_t op1,size_t vl) +{ + return __riscv_viota_m_u16mf4_m(mask,op1,31); +} + + +vuint16mf2_t test___riscv_viota_m_u16mf2_m(vbool32_t mask,vbool32_t op1,size_t vl) +{ + return __riscv_viota_m_u16mf2_m(mask,op1,31); +} + + +vuint16m1_t test___riscv_viota_m_u16m1_m(vbool16_t mask,vbool16_t op1,size_t vl) +{ + return __riscv_viota_m_u16m1_m(mask,op1,31); +} + + +vuint16m2_t test___riscv_viota_m_u16m2_m(vbool8_t mask,vbool8_t op1,size_t vl) +{ + return __riscv_viota_m_u16m2_m(mask,op1,31); +} + + +vuint16m4_t test___riscv_viota_m_u16m4_m(vbool4_t mask,vbool4_t op1,size_t vl) +{ + return __riscv_viota_m_u16m4_m(mask,op1,31); +} + + +vuint16m8_t test___riscv_viota_m_u16m8_m(vbool2_t mask,vbool2_t op1,size_t vl) +{ + return __riscv_viota_m_u16m8_m(mask,op1,31); +} + + +vuint32mf2_t test___riscv_viota_m_u32mf2_m(vbool64_t mask,vbool64_t op1,size_t vl) +{ + return __riscv_viota_m_u32mf2_m(mask,op1,31); +} + + +vuint32m1_t test___riscv_viota_m_u32m1_m(vbool32_t mask,vbool32_t op1,size_t vl) +{ + return __riscv_viota_m_u32m1_m(mask,op1,31); +} + + +vuint32m2_t test___riscv_viota_m_u32m2_m(vbool16_t mask,vbool16_t op1,size_t vl) +{ + return __riscv_viota_m_u32m2_m(mask,op1,31); +} + + +vuint32m4_t test___riscv_viota_m_u32m4_m(vbool8_t mask,vbool8_t op1,size_t vl) +{ + return __riscv_viota_m_u32m4_m(mask,op1,31); +} + + +vuint32m8_t test___riscv_viota_m_u32m8_m(vbool4_t mask,vbool4_t op1,size_t vl) +{ + return __riscv_viota_m_u32m8_m(mask,op1,31); +} + + +vuint64m1_t test___riscv_viota_m_u64m1_m(vbool64_t mask,vbool64_t op1,size_t vl) +{ + return __riscv_viota_m_u64m1_m(mask,op1,31); +} + + +vuint64m2_t test___riscv_viota_m_u64m2_m(vbool32_t mask,vbool32_t op1,size_t vl) +{ + return __riscv_viota_m_u64m2_m(mask,op1,31); +} + + +vuint64m4_t test___riscv_viota_m_u64m4_m(vbool16_t mask,vbool16_t op1,size_t vl) +{ + return __riscv_viota_m_u64m4_m(mask,op1,31); +} + + +vuint64m8_t test___riscv_viota_m_u64m8_m(vbool8_t mask,vbool8_t op1,size_t vl) +{ + return __riscv_viota_m_u64m8_m(mask,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/viota_m_m-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/viota_m_m-3.c new file mode 100644 index 00000000000..653d95b2d83 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/viota_m_m-3.c @@ -0,0 +1,314 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_viota_m_u8mf8(vbool64_t op1,size_t vl) +{ + return __riscv_viota_m_u8mf8(op1,32); +} + + +vuint8mf4_t test___riscv_viota_m_u8mf4(vbool32_t op1,size_t vl) +{ + return __riscv_viota_m_u8mf4(op1,32); +} + + +vuint8mf2_t test___riscv_viota_m_u8mf2(vbool16_t op1,size_t vl) +{ + return __riscv_viota_m_u8mf2(op1,32); +} + + +vuint8m1_t test___riscv_viota_m_u8m1(vbool8_t op1,size_t vl) +{ + return __riscv_viota_m_u8m1(op1,32); +} + + +vuint8m2_t test___riscv_viota_m_u8m2(vbool4_t op1,size_t vl) +{ + return __riscv_viota_m_u8m2(op1,32); +} + + +vuint8m4_t test___riscv_viota_m_u8m4(vbool2_t op1,size_t vl) +{ + return __riscv_viota_m_u8m4(op1,32); +} + + +vuint8m8_t test___riscv_viota_m_u8m8(vbool1_t op1,size_t vl) +{ + return __riscv_viota_m_u8m8(op1,32); +} + + +vuint16mf4_t test___riscv_viota_m_u16mf4(vbool64_t op1,size_t vl) +{ + return __riscv_viota_m_u16mf4(op1,32); +} + + +vuint16mf2_t test___riscv_viota_m_u16mf2(vbool32_t op1,size_t vl) +{ + return __riscv_viota_m_u16mf2(op1,32); +} + + +vuint16m1_t test___riscv_viota_m_u16m1(vbool16_t op1,size_t vl) +{ + return __riscv_viota_m_u16m1(op1,32); +} + + +vuint16m2_t test___riscv_viota_m_u16m2(vbool8_t op1,size_t vl) +{ + return __riscv_viota_m_u16m2(op1,32); +} + + +vuint16m4_t test___riscv_viota_m_u16m4(vbool4_t op1,size_t vl) +{ + return __riscv_viota_m_u16m4(op1,32); +} + + +vuint16m8_t test___riscv_viota_m_u16m8(vbool2_t op1,size_t vl) +{ + return __riscv_viota_m_u16m8(op1,32); +} + + +vuint32mf2_t test___riscv_viota_m_u32mf2(vbool64_t op1,size_t vl) +{ + return __riscv_viota_m_u32mf2(op1,32); +} + + +vuint32m1_t test___riscv_viota_m_u32m1(vbool32_t op1,size_t vl) +{ + return __riscv_viota_m_u32m1(op1,32); +} + + +vuint32m2_t test___riscv_viota_m_u32m2(vbool16_t op1,size_t vl) +{ + return __riscv_viota_m_u32m2(op1,32); +} + + +vuint32m4_t test___riscv_viota_m_u32m4(vbool8_t op1,size_t vl) +{ + return __riscv_viota_m_u32m4(op1,32); +} + + +vuint32m8_t test___riscv_viota_m_u32m8(vbool4_t op1,size_t vl) +{ + return __riscv_viota_m_u32m8(op1,32); +} + + +vuint64m1_t test___riscv_viota_m_u64m1(vbool64_t op1,size_t vl) +{ + return __riscv_viota_m_u64m1(op1,32); +} + + +vuint64m2_t test___riscv_viota_m_u64m2(vbool32_t op1,size_t vl) +{ + return __riscv_viota_m_u64m2(op1,32); +} + + +vuint64m4_t test___riscv_viota_m_u64m4(vbool16_t op1,size_t vl) +{ + return __riscv_viota_m_u64m4(op1,32); +} + + +vuint64m8_t test___riscv_viota_m_u64m8(vbool8_t op1,size_t vl) +{ + return __riscv_viota_m_u64m8(op1,32); +} + + +vuint8mf8_t test___riscv_viota_m_u8mf8_m(vbool64_t mask,vbool64_t op1,size_t vl) +{ + return __riscv_viota_m_u8mf8_m(mask,op1,32); +} + + +vuint8mf4_t test___riscv_viota_m_u8mf4_m(vbool32_t mask,vbool32_t op1,size_t vl) +{ + return __riscv_viota_m_u8mf4_m(mask,op1,32); +} + + +vuint8mf2_t test___riscv_viota_m_u8mf2_m(vbool16_t mask,vbool16_t op1,size_t vl) +{ + return __riscv_viota_m_u8mf2_m(mask,op1,32); +} + + +vuint8m1_t test___riscv_viota_m_u8m1_m(vbool8_t mask,vbool8_t op1,size_t vl) +{ + return __riscv_viota_m_u8m1_m(mask,op1,32); +} + + +vuint8m2_t test___riscv_viota_m_u8m2_m(vbool4_t mask,vbool4_t op1,size_t vl) +{ + return __riscv_viota_m_u8m2_m(mask,op1,32); +} + + +vuint8m4_t test___riscv_viota_m_u8m4_m(vbool2_t mask,vbool2_t op1,size_t vl) +{ + return __riscv_viota_m_u8m4_m(mask,op1,32); +} + + +vuint8m8_t test___riscv_viota_m_u8m8_m(vbool1_t mask,vbool1_t op1,size_t vl) +{ + return __riscv_viota_m_u8m8_m(mask,op1,32); +} + + +vuint16mf4_t test___riscv_viota_m_u16mf4_m(vbool64_t mask,vbool64_t op1,size_t vl) +{ + return __riscv_viota_m_u16mf4_m(mask,op1,32); +} + + +vuint16mf2_t test___riscv_viota_m_u16mf2_m(vbool32_t mask,vbool32_t op1,size_t vl) +{ + return __riscv_viota_m_u16mf2_m(mask,op1,32); +} + + +vuint16m1_t test___riscv_viota_m_u16m1_m(vbool16_t mask,vbool16_t op1,size_t vl) +{ + return __riscv_viota_m_u16m1_m(mask,op1,32); +} + + +vuint16m2_t test___riscv_viota_m_u16m2_m(vbool8_t mask,vbool8_t op1,size_t vl) +{ + return __riscv_viota_m_u16m2_m(mask,op1,32); +} + + +vuint16m4_t test___riscv_viota_m_u16m4_m(vbool4_t mask,vbool4_t op1,size_t vl) +{ + return __riscv_viota_m_u16m4_m(mask,op1,32); +} + + +vuint16m8_t test___riscv_viota_m_u16m8_m(vbool2_t mask,vbool2_t op1,size_t vl) +{ + return __riscv_viota_m_u16m8_m(mask,op1,32); +} + + +vuint32mf2_t test___riscv_viota_m_u32mf2_m(vbool64_t mask,vbool64_t op1,size_t vl) +{ + return __riscv_viota_m_u32mf2_m(mask,op1,32); +} + + +vuint32m1_t test___riscv_viota_m_u32m1_m(vbool32_t mask,vbool32_t op1,size_t vl) +{ + return __riscv_viota_m_u32m1_m(mask,op1,32); +} + + +vuint32m2_t test___riscv_viota_m_u32m2_m(vbool16_t mask,vbool16_t op1,size_t vl) +{ + return __riscv_viota_m_u32m2_m(mask,op1,32); +} + + +vuint32m4_t test___riscv_viota_m_u32m4_m(vbool8_t mask,vbool8_t op1,size_t vl) +{ + return __riscv_viota_m_u32m4_m(mask,op1,32); +} + + +vuint32m8_t test___riscv_viota_m_u32m8_m(vbool4_t mask,vbool4_t op1,size_t vl) +{ + return __riscv_viota_m_u32m8_m(mask,op1,32); +} + + +vuint64m1_t test___riscv_viota_m_u64m1_m(vbool64_t mask,vbool64_t op1,size_t vl) +{ + return __riscv_viota_m_u64m1_m(mask,op1,32); +} + + +vuint64m2_t test___riscv_viota_m_u64m2_m(vbool32_t mask,vbool32_t op1,size_t vl) +{ + return __riscv_viota_m_u64m2_m(mask,op1,32); +} + + +vuint64m4_t test___riscv_viota_m_u64m4_m(vbool16_t mask,vbool16_t op1,size_t vl) +{ + return __riscv_viota_m_u64m4_m(mask,op1,32); +} + + +vuint64m8_t test___riscv_viota_m_u64m8_m(vbool8_t mask,vbool8_t op1,size_t vl) +{ + return __riscv_viota_m_u64m8_m(mask,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/viota_m_mu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/viota_m_mu-1.c new file mode 100644 index 00000000000..d2a2f4e85a7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/viota_m_mu-1.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_viota_m_u8mf8_mu(vbool64_t mask,vuint8mf8_t maskedoff,vbool64_t op1,size_t vl) +{ + return __riscv_viota_m_u8mf8_mu(mask,maskedoff,op1,vl); +} + + +vuint8mf4_t test___riscv_viota_m_u8mf4_mu(vbool32_t mask,vuint8mf4_t maskedoff,vbool32_t op1,size_t vl) +{ + return __riscv_viota_m_u8mf4_mu(mask,maskedoff,op1,vl); +} + + +vuint8mf2_t test___riscv_viota_m_u8mf2_mu(vbool16_t mask,vuint8mf2_t maskedoff,vbool16_t op1,size_t vl) +{ + return __riscv_viota_m_u8mf2_mu(mask,maskedoff,op1,vl); +} + + +vuint8m1_t test___riscv_viota_m_u8m1_mu(vbool8_t mask,vuint8m1_t maskedoff,vbool8_t op1,size_t vl) +{ + return __riscv_viota_m_u8m1_mu(mask,maskedoff,op1,vl); +} + + +vuint8m2_t test___riscv_viota_m_u8m2_mu(vbool4_t mask,vuint8m2_t maskedoff,vbool4_t op1,size_t vl) +{ + return __riscv_viota_m_u8m2_mu(mask,maskedoff,op1,vl); +} + + +vuint8m4_t test___riscv_viota_m_u8m4_mu(vbool2_t mask,vuint8m4_t maskedoff,vbool2_t op1,size_t vl) +{ + return __riscv_viota_m_u8m4_mu(mask,maskedoff,op1,vl); +} + + +vuint8m8_t test___riscv_viota_m_u8m8_mu(vbool1_t mask,vuint8m8_t maskedoff,vbool1_t op1,size_t vl) +{ + return __riscv_viota_m_u8m8_mu(mask,maskedoff,op1,vl); +} + + +vuint16mf4_t test___riscv_viota_m_u16mf4_mu(vbool64_t mask,vuint16mf4_t maskedoff,vbool64_t op1,size_t vl) +{ + return __riscv_viota_m_u16mf4_mu(mask,maskedoff,op1,vl); +} + + +vuint16mf2_t test___riscv_viota_m_u16mf2_mu(vbool32_t mask,vuint16mf2_t maskedoff,vbool32_t op1,size_t vl) +{ + return __riscv_viota_m_u16mf2_mu(mask,maskedoff,op1,vl); +} + + +vuint16m1_t test___riscv_viota_m_u16m1_mu(vbool16_t mask,vuint16m1_t maskedoff,vbool16_t op1,size_t vl) +{ + return __riscv_viota_m_u16m1_mu(mask,maskedoff,op1,vl); +} + + +vuint16m2_t test___riscv_viota_m_u16m2_mu(vbool8_t mask,vuint16m2_t maskedoff,vbool8_t op1,size_t vl) +{ + return __riscv_viota_m_u16m2_mu(mask,maskedoff,op1,vl); +} + + +vuint16m4_t test___riscv_viota_m_u16m4_mu(vbool4_t mask,vuint16m4_t maskedoff,vbool4_t op1,size_t vl) +{ + return __riscv_viota_m_u16m4_mu(mask,maskedoff,op1,vl); +} + + +vuint16m8_t test___riscv_viota_m_u16m8_mu(vbool2_t mask,vuint16m8_t maskedoff,vbool2_t op1,size_t vl) +{ + return __riscv_viota_m_u16m8_mu(mask,maskedoff,op1,vl); +} + + +vuint32mf2_t test___riscv_viota_m_u32mf2_mu(vbool64_t mask,vuint32mf2_t maskedoff,vbool64_t op1,size_t vl) +{ + return __riscv_viota_m_u32mf2_mu(mask,maskedoff,op1,vl); +} + + +vuint32m1_t test___riscv_viota_m_u32m1_mu(vbool32_t mask,vuint32m1_t maskedoff,vbool32_t op1,size_t vl) +{ + return __riscv_viota_m_u32m1_mu(mask,maskedoff,op1,vl); +} + + +vuint32m2_t test___riscv_viota_m_u32m2_mu(vbool16_t mask,vuint32m2_t maskedoff,vbool16_t op1,size_t vl) +{ + return __riscv_viota_m_u32m2_mu(mask,maskedoff,op1,vl); +} + + +vuint32m4_t test___riscv_viota_m_u32m4_mu(vbool8_t mask,vuint32m4_t maskedoff,vbool8_t op1,size_t vl) +{ + return __riscv_viota_m_u32m4_mu(mask,maskedoff,op1,vl); +} + + +vuint32m8_t test___riscv_viota_m_u32m8_mu(vbool4_t mask,vuint32m8_t maskedoff,vbool4_t op1,size_t vl) +{ + return __riscv_viota_m_u32m8_mu(mask,maskedoff,op1,vl); +} + + +vuint64m1_t test___riscv_viota_m_u64m1_mu(vbool64_t mask,vuint64m1_t maskedoff,vbool64_t op1,size_t vl) +{ + return __riscv_viota_m_u64m1_mu(mask,maskedoff,op1,vl); +} + + +vuint64m2_t test___riscv_viota_m_u64m2_mu(vbool32_t mask,vuint64m2_t maskedoff,vbool32_t op1,size_t vl) +{ + return __riscv_viota_m_u64m2_mu(mask,maskedoff,op1,vl); +} + + +vuint64m4_t test___riscv_viota_m_u64m4_mu(vbool16_t mask,vuint64m4_t maskedoff,vbool16_t op1,size_t vl) +{ + return __riscv_viota_m_u64m4_mu(mask,maskedoff,op1,vl); +} + + +vuint64m8_t test___riscv_viota_m_u64m8_mu(vbool8_t mask,vuint64m8_t maskedoff,vbool8_t op1,size_t vl) +{ + return __riscv_viota_m_u64m8_mu(mask,maskedoff,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/viota_m_mu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/viota_m_mu-2.c new file mode 100644 index 00000000000..da2dbc3d397 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/viota_m_mu-2.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_viota_m_u8mf8_mu(vbool64_t mask,vuint8mf8_t maskedoff,vbool64_t op1,size_t vl) +{ + return __riscv_viota_m_u8mf8_mu(mask,maskedoff,op1,31); +} + + +vuint8mf4_t test___riscv_viota_m_u8mf4_mu(vbool32_t mask,vuint8mf4_t maskedoff,vbool32_t op1,size_t vl) +{ + return __riscv_viota_m_u8mf4_mu(mask,maskedoff,op1,31); +} + + +vuint8mf2_t test___riscv_viota_m_u8mf2_mu(vbool16_t mask,vuint8mf2_t maskedoff,vbool16_t op1,size_t vl) +{ + return __riscv_viota_m_u8mf2_mu(mask,maskedoff,op1,31); +} + + +vuint8m1_t test___riscv_viota_m_u8m1_mu(vbool8_t mask,vuint8m1_t maskedoff,vbool8_t op1,size_t vl) +{ + return __riscv_viota_m_u8m1_mu(mask,maskedoff,op1,31); +} + + +vuint8m2_t test___riscv_viota_m_u8m2_mu(vbool4_t mask,vuint8m2_t maskedoff,vbool4_t op1,size_t vl) +{ + return __riscv_viota_m_u8m2_mu(mask,maskedoff,op1,31); +} + + +vuint8m4_t test___riscv_viota_m_u8m4_mu(vbool2_t mask,vuint8m4_t maskedoff,vbool2_t op1,size_t vl) +{ + return __riscv_viota_m_u8m4_mu(mask,maskedoff,op1,31); +} + + +vuint8m8_t test___riscv_viota_m_u8m8_mu(vbool1_t mask,vuint8m8_t maskedoff,vbool1_t op1,size_t vl) +{ + return __riscv_viota_m_u8m8_mu(mask,maskedoff,op1,31); +} + + +vuint16mf4_t test___riscv_viota_m_u16mf4_mu(vbool64_t mask,vuint16mf4_t maskedoff,vbool64_t op1,size_t vl) +{ + return __riscv_viota_m_u16mf4_mu(mask,maskedoff,op1,31); +} + + +vuint16mf2_t test___riscv_viota_m_u16mf2_mu(vbool32_t mask,vuint16mf2_t maskedoff,vbool32_t op1,size_t vl) +{ + return __riscv_viota_m_u16mf2_mu(mask,maskedoff,op1,31); +} + + +vuint16m1_t test___riscv_viota_m_u16m1_mu(vbool16_t mask,vuint16m1_t maskedoff,vbool16_t op1,size_t vl) +{ + return __riscv_viota_m_u16m1_mu(mask,maskedoff,op1,31); +} + + +vuint16m2_t test___riscv_viota_m_u16m2_mu(vbool8_t mask,vuint16m2_t maskedoff,vbool8_t op1,size_t vl) +{ + return __riscv_viota_m_u16m2_mu(mask,maskedoff,op1,31); +} + + +vuint16m4_t test___riscv_viota_m_u16m4_mu(vbool4_t mask,vuint16m4_t maskedoff,vbool4_t op1,size_t vl) +{ + return __riscv_viota_m_u16m4_mu(mask,maskedoff,op1,31); +} + + +vuint16m8_t test___riscv_viota_m_u16m8_mu(vbool2_t mask,vuint16m8_t maskedoff,vbool2_t op1,size_t vl) +{ + return __riscv_viota_m_u16m8_mu(mask,maskedoff,op1,31); +} + + +vuint32mf2_t test___riscv_viota_m_u32mf2_mu(vbool64_t mask,vuint32mf2_t maskedoff,vbool64_t op1,size_t vl) +{ + return __riscv_viota_m_u32mf2_mu(mask,maskedoff,op1,31); +} + + +vuint32m1_t test___riscv_viota_m_u32m1_mu(vbool32_t mask,vuint32m1_t maskedoff,vbool32_t op1,size_t vl) +{ + return __riscv_viota_m_u32m1_mu(mask,maskedoff,op1,31); +} + + +vuint32m2_t test___riscv_viota_m_u32m2_mu(vbool16_t mask,vuint32m2_t maskedoff,vbool16_t op1,size_t vl) +{ + return __riscv_viota_m_u32m2_mu(mask,maskedoff,op1,31); +} + + +vuint32m4_t test___riscv_viota_m_u32m4_mu(vbool8_t mask,vuint32m4_t maskedoff,vbool8_t op1,size_t vl) +{ + return __riscv_viota_m_u32m4_mu(mask,maskedoff,op1,31); +} + + +vuint32m8_t test___riscv_viota_m_u32m8_mu(vbool4_t mask,vuint32m8_t maskedoff,vbool4_t op1,size_t vl) +{ + return __riscv_viota_m_u32m8_mu(mask,maskedoff,op1,31); +} + + +vuint64m1_t test___riscv_viota_m_u64m1_mu(vbool64_t mask,vuint64m1_t maskedoff,vbool64_t op1,size_t vl) +{ + return __riscv_viota_m_u64m1_mu(mask,maskedoff,op1,31); +} + + +vuint64m2_t test___riscv_viota_m_u64m2_mu(vbool32_t mask,vuint64m2_t maskedoff,vbool32_t op1,size_t vl) +{ + return __riscv_viota_m_u64m2_mu(mask,maskedoff,op1,31); +} + + +vuint64m4_t test___riscv_viota_m_u64m4_mu(vbool16_t mask,vuint64m4_t maskedoff,vbool16_t op1,size_t vl) +{ + return __riscv_viota_m_u64m4_mu(mask,maskedoff,op1,31); +} + + +vuint64m8_t test___riscv_viota_m_u64m8_mu(vbool8_t mask,vuint64m8_t maskedoff,vbool8_t op1,size_t vl) +{ + return __riscv_viota_m_u64m8_mu(mask,maskedoff,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/viota_m_mu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/viota_m_mu-3.c new file mode 100644 index 00000000000..7c7c7cdbf02 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/viota_m_mu-3.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_viota_m_u8mf8_mu(vbool64_t mask,vuint8mf8_t maskedoff,vbool64_t op1,size_t vl) +{ + return __riscv_viota_m_u8mf8_mu(mask,maskedoff,op1,32); +} + + +vuint8mf4_t test___riscv_viota_m_u8mf4_mu(vbool32_t mask,vuint8mf4_t maskedoff,vbool32_t op1,size_t vl) +{ + return __riscv_viota_m_u8mf4_mu(mask,maskedoff,op1,32); +} + + +vuint8mf2_t test___riscv_viota_m_u8mf2_mu(vbool16_t mask,vuint8mf2_t maskedoff,vbool16_t op1,size_t vl) +{ + return __riscv_viota_m_u8mf2_mu(mask,maskedoff,op1,32); +} + + +vuint8m1_t test___riscv_viota_m_u8m1_mu(vbool8_t mask,vuint8m1_t maskedoff,vbool8_t op1,size_t vl) +{ + return __riscv_viota_m_u8m1_mu(mask,maskedoff,op1,32); +} + + +vuint8m2_t test___riscv_viota_m_u8m2_mu(vbool4_t mask,vuint8m2_t maskedoff,vbool4_t op1,size_t vl) +{ + return __riscv_viota_m_u8m2_mu(mask,maskedoff,op1,32); +} + + +vuint8m4_t test___riscv_viota_m_u8m4_mu(vbool2_t mask,vuint8m4_t maskedoff,vbool2_t op1,size_t vl) +{ + return __riscv_viota_m_u8m4_mu(mask,maskedoff,op1,32); +} + + +vuint8m8_t test___riscv_viota_m_u8m8_mu(vbool1_t mask,vuint8m8_t maskedoff,vbool1_t op1,size_t vl) +{ + return __riscv_viota_m_u8m8_mu(mask,maskedoff,op1,32); +} + + +vuint16mf4_t test___riscv_viota_m_u16mf4_mu(vbool64_t mask,vuint16mf4_t maskedoff,vbool64_t op1,size_t vl) +{ + return __riscv_viota_m_u16mf4_mu(mask,maskedoff,op1,32); +} + + +vuint16mf2_t test___riscv_viota_m_u16mf2_mu(vbool32_t mask,vuint16mf2_t maskedoff,vbool32_t op1,size_t vl) +{ + return __riscv_viota_m_u16mf2_mu(mask,maskedoff,op1,32); +} + + +vuint16m1_t test___riscv_viota_m_u16m1_mu(vbool16_t mask,vuint16m1_t maskedoff,vbool16_t op1,size_t vl) +{ + return __riscv_viota_m_u16m1_mu(mask,maskedoff,op1,32); +} + + +vuint16m2_t test___riscv_viota_m_u16m2_mu(vbool8_t mask,vuint16m2_t maskedoff,vbool8_t op1,size_t vl) +{ + return __riscv_viota_m_u16m2_mu(mask,maskedoff,op1,32); +} + + +vuint16m4_t test___riscv_viota_m_u16m4_mu(vbool4_t mask,vuint16m4_t maskedoff,vbool4_t op1,size_t vl) +{ + return __riscv_viota_m_u16m4_mu(mask,maskedoff,op1,32); +} + + +vuint16m8_t test___riscv_viota_m_u16m8_mu(vbool2_t mask,vuint16m8_t maskedoff,vbool2_t op1,size_t vl) +{ + return __riscv_viota_m_u16m8_mu(mask,maskedoff,op1,32); +} + + +vuint32mf2_t test___riscv_viota_m_u32mf2_mu(vbool64_t mask,vuint32mf2_t maskedoff,vbool64_t op1,size_t vl) +{ + return __riscv_viota_m_u32mf2_mu(mask,maskedoff,op1,32); +} + + +vuint32m1_t test___riscv_viota_m_u32m1_mu(vbool32_t mask,vuint32m1_t maskedoff,vbool32_t op1,size_t vl) +{ + return __riscv_viota_m_u32m1_mu(mask,maskedoff,op1,32); +} + + +vuint32m2_t test___riscv_viota_m_u32m2_mu(vbool16_t mask,vuint32m2_t maskedoff,vbool16_t op1,size_t vl) +{ + return __riscv_viota_m_u32m2_mu(mask,maskedoff,op1,32); +} + + +vuint32m4_t test___riscv_viota_m_u32m4_mu(vbool8_t mask,vuint32m4_t maskedoff,vbool8_t op1,size_t vl) +{ + return __riscv_viota_m_u32m4_mu(mask,maskedoff,op1,32); +} + + +vuint32m8_t test___riscv_viota_m_u32m8_mu(vbool4_t mask,vuint32m8_t maskedoff,vbool4_t op1,size_t vl) +{ + return __riscv_viota_m_u32m8_mu(mask,maskedoff,op1,32); +} + + +vuint64m1_t test___riscv_viota_m_u64m1_mu(vbool64_t mask,vuint64m1_t maskedoff,vbool64_t op1,size_t vl) +{ + return __riscv_viota_m_u64m1_mu(mask,maskedoff,op1,32); +} + + +vuint64m2_t test___riscv_viota_m_u64m2_mu(vbool32_t mask,vuint64m2_t maskedoff,vbool32_t op1,size_t vl) +{ + return __riscv_viota_m_u64m2_mu(mask,maskedoff,op1,32); +} + + +vuint64m4_t test___riscv_viota_m_u64m4_mu(vbool16_t mask,vuint64m4_t maskedoff,vbool16_t op1,size_t vl) +{ + return __riscv_viota_m_u64m4_mu(mask,maskedoff,op1,32); +} + + +vuint64m8_t test___riscv_viota_m_u64m8_mu(vbool8_t mask,vuint64m8_t maskedoff,vbool8_t op1,size_t vl) +{ + return __riscv_viota_m_u64m8_mu(mask,maskedoff,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/viota_m_tu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/viota_m_tu-1.c new file mode 100644 index 00000000000..16f34848e41 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/viota_m_tu-1.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_viota_m_u8mf8_tu(vuint8mf8_t maskedoff,vbool64_t op1,size_t vl) +{ + return __riscv_viota_m_u8mf8_tu(maskedoff,op1,vl); +} + + +vuint8mf4_t test___riscv_viota_m_u8mf4_tu(vuint8mf4_t maskedoff,vbool32_t op1,size_t vl) +{ + return __riscv_viota_m_u8mf4_tu(maskedoff,op1,vl); +} + + +vuint8mf2_t test___riscv_viota_m_u8mf2_tu(vuint8mf2_t maskedoff,vbool16_t op1,size_t vl) +{ + return __riscv_viota_m_u8mf2_tu(maskedoff,op1,vl); +} + + +vuint8m1_t test___riscv_viota_m_u8m1_tu(vuint8m1_t maskedoff,vbool8_t op1,size_t vl) +{ + return __riscv_viota_m_u8m1_tu(maskedoff,op1,vl); +} + + +vuint8m2_t test___riscv_viota_m_u8m2_tu(vuint8m2_t maskedoff,vbool4_t op1,size_t vl) +{ + return __riscv_viota_m_u8m2_tu(maskedoff,op1,vl); +} + + +vuint8m4_t test___riscv_viota_m_u8m4_tu(vuint8m4_t maskedoff,vbool2_t op1,size_t vl) +{ + return __riscv_viota_m_u8m4_tu(maskedoff,op1,vl); +} + + +vuint8m8_t test___riscv_viota_m_u8m8_tu(vuint8m8_t maskedoff,vbool1_t op1,size_t vl) +{ + return __riscv_viota_m_u8m8_tu(maskedoff,op1,vl); +} + + +vuint16mf4_t test___riscv_viota_m_u16mf4_tu(vuint16mf4_t maskedoff,vbool64_t op1,size_t vl) +{ + return __riscv_viota_m_u16mf4_tu(maskedoff,op1,vl); +} + + +vuint16mf2_t test___riscv_viota_m_u16mf2_tu(vuint16mf2_t maskedoff,vbool32_t op1,size_t vl) +{ + return __riscv_viota_m_u16mf2_tu(maskedoff,op1,vl); +} + + +vuint16m1_t test___riscv_viota_m_u16m1_tu(vuint16m1_t maskedoff,vbool16_t op1,size_t vl) +{ + return __riscv_viota_m_u16m1_tu(maskedoff,op1,vl); +} + + +vuint16m2_t test___riscv_viota_m_u16m2_tu(vuint16m2_t maskedoff,vbool8_t op1,size_t vl) +{ + return __riscv_viota_m_u16m2_tu(maskedoff,op1,vl); +} + + +vuint16m4_t test___riscv_viota_m_u16m4_tu(vuint16m4_t maskedoff,vbool4_t op1,size_t vl) +{ + return __riscv_viota_m_u16m4_tu(maskedoff,op1,vl); +} + + +vuint16m8_t test___riscv_viota_m_u16m8_tu(vuint16m8_t maskedoff,vbool2_t op1,size_t vl) +{ + return __riscv_viota_m_u16m8_tu(maskedoff,op1,vl); +} + + +vuint32mf2_t test___riscv_viota_m_u32mf2_tu(vuint32mf2_t maskedoff,vbool64_t op1,size_t vl) +{ + return __riscv_viota_m_u32mf2_tu(maskedoff,op1,vl); +} + + +vuint32m1_t test___riscv_viota_m_u32m1_tu(vuint32m1_t maskedoff,vbool32_t op1,size_t vl) +{ + return __riscv_viota_m_u32m1_tu(maskedoff,op1,vl); +} + + +vuint32m2_t test___riscv_viota_m_u32m2_tu(vuint32m2_t maskedoff,vbool16_t op1,size_t vl) +{ + return __riscv_viota_m_u32m2_tu(maskedoff,op1,vl); +} + + +vuint32m4_t test___riscv_viota_m_u32m4_tu(vuint32m4_t maskedoff,vbool8_t op1,size_t vl) +{ + return __riscv_viota_m_u32m4_tu(maskedoff,op1,vl); +} + + +vuint32m8_t test___riscv_viota_m_u32m8_tu(vuint32m8_t maskedoff,vbool4_t op1,size_t vl) +{ + return __riscv_viota_m_u32m8_tu(maskedoff,op1,vl); +} + + +vuint64m1_t test___riscv_viota_m_u64m1_tu(vuint64m1_t maskedoff,vbool64_t op1,size_t vl) +{ + return __riscv_viota_m_u64m1_tu(maskedoff,op1,vl); +} + + +vuint64m2_t test___riscv_viota_m_u64m2_tu(vuint64m2_t maskedoff,vbool32_t op1,size_t vl) +{ + return __riscv_viota_m_u64m2_tu(maskedoff,op1,vl); +} + + +vuint64m4_t test___riscv_viota_m_u64m4_tu(vuint64m4_t maskedoff,vbool16_t op1,size_t vl) +{ + return __riscv_viota_m_u64m4_tu(maskedoff,op1,vl); +} + + +vuint64m8_t test___riscv_viota_m_u64m8_tu(vuint64m8_t maskedoff,vbool8_t op1,size_t vl) +{ + return __riscv_viota_m_u64m8_tu(maskedoff,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/viota_m_tu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/viota_m_tu-2.c new file mode 100644 index 00000000000..10990632b49 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/viota_m_tu-2.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_viota_m_u8mf8_tu(vuint8mf8_t maskedoff,vbool64_t op1,size_t vl) +{ + return __riscv_viota_m_u8mf8_tu(maskedoff,op1,31); +} + + +vuint8mf4_t test___riscv_viota_m_u8mf4_tu(vuint8mf4_t maskedoff,vbool32_t op1,size_t vl) +{ + return __riscv_viota_m_u8mf4_tu(maskedoff,op1,31); +} + + +vuint8mf2_t test___riscv_viota_m_u8mf2_tu(vuint8mf2_t maskedoff,vbool16_t op1,size_t vl) +{ + return __riscv_viota_m_u8mf2_tu(maskedoff,op1,31); +} + + +vuint8m1_t test___riscv_viota_m_u8m1_tu(vuint8m1_t maskedoff,vbool8_t op1,size_t vl) +{ + return __riscv_viota_m_u8m1_tu(maskedoff,op1,31); +} + + +vuint8m2_t test___riscv_viota_m_u8m2_tu(vuint8m2_t maskedoff,vbool4_t op1,size_t vl) +{ + return __riscv_viota_m_u8m2_tu(maskedoff,op1,31); +} + + +vuint8m4_t test___riscv_viota_m_u8m4_tu(vuint8m4_t maskedoff,vbool2_t op1,size_t vl) +{ + return __riscv_viota_m_u8m4_tu(maskedoff,op1,31); +} + + +vuint8m8_t test___riscv_viota_m_u8m8_tu(vuint8m8_t maskedoff,vbool1_t op1,size_t vl) +{ + return __riscv_viota_m_u8m8_tu(maskedoff,op1,31); +} + + +vuint16mf4_t test___riscv_viota_m_u16mf4_tu(vuint16mf4_t maskedoff,vbool64_t op1,size_t vl) +{ + return __riscv_viota_m_u16mf4_tu(maskedoff,op1,31); +} + + +vuint16mf2_t test___riscv_viota_m_u16mf2_tu(vuint16mf2_t maskedoff,vbool32_t op1,size_t vl) +{ + return __riscv_viota_m_u16mf2_tu(maskedoff,op1,31); +} + + +vuint16m1_t test___riscv_viota_m_u16m1_tu(vuint16m1_t maskedoff,vbool16_t op1,size_t vl) +{ + return __riscv_viota_m_u16m1_tu(maskedoff,op1,31); +} + + +vuint16m2_t test___riscv_viota_m_u16m2_tu(vuint16m2_t maskedoff,vbool8_t op1,size_t vl) +{ + return __riscv_viota_m_u16m2_tu(maskedoff,op1,31); +} + + +vuint16m4_t test___riscv_viota_m_u16m4_tu(vuint16m4_t maskedoff,vbool4_t op1,size_t vl) +{ + return __riscv_viota_m_u16m4_tu(maskedoff,op1,31); +} + + +vuint16m8_t test___riscv_viota_m_u16m8_tu(vuint16m8_t maskedoff,vbool2_t op1,size_t vl) +{ + return __riscv_viota_m_u16m8_tu(maskedoff,op1,31); +} + + +vuint32mf2_t test___riscv_viota_m_u32mf2_tu(vuint32mf2_t maskedoff,vbool64_t op1,size_t vl) +{ + return __riscv_viota_m_u32mf2_tu(maskedoff,op1,31); +} + + +vuint32m1_t test___riscv_viota_m_u32m1_tu(vuint32m1_t maskedoff,vbool32_t op1,size_t vl) +{ + return __riscv_viota_m_u32m1_tu(maskedoff,op1,31); +} + + +vuint32m2_t test___riscv_viota_m_u32m2_tu(vuint32m2_t maskedoff,vbool16_t op1,size_t vl) +{ + return __riscv_viota_m_u32m2_tu(maskedoff,op1,31); +} + + +vuint32m4_t test___riscv_viota_m_u32m4_tu(vuint32m4_t maskedoff,vbool8_t op1,size_t vl) +{ + return __riscv_viota_m_u32m4_tu(maskedoff,op1,31); +} + + +vuint32m8_t test___riscv_viota_m_u32m8_tu(vuint32m8_t maskedoff,vbool4_t op1,size_t vl) +{ + return __riscv_viota_m_u32m8_tu(maskedoff,op1,31); +} + + +vuint64m1_t test___riscv_viota_m_u64m1_tu(vuint64m1_t maskedoff,vbool64_t op1,size_t vl) +{ + return __riscv_viota_m_u64m1_tu(maskedoff,op1,31); +} + + +vuint64m2_t test___riscv_viota_m_u64m2_tu(vuint64m2_t maskedoff,vbool32_t op1,size_t vl) +{ + return __riscv_viota_m_u64m2_tu(maskedoff,op1,31); +} + + +vuint64m4_t test___riscv_viota_m_u64m4_tu(vuint64m4_t maskedoff,vbool16_t op1,size_t vl) +{ + return __riscv_viota_m_u64m4_tu(maskedoff,op1,31); +} + + +vuint64m8_t test___riscv_viota_m_u64m8_tu(vuint64m8_t maskedoff,vbool8_t op1,size_t vl) +{ + return __riscv_viota_m_u64m8_tu(maskedoff,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/viota_m_tu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/viota_m_tu-3.c new file mode 100644 index 00000000000..261fcbcf6c8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/viota_m_tu-3.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_viota_m_u8mf8_tu(vuint8mf8_t maskedoff,vbool64_t op1,size_t vl) +{ + return __riscv_viota_m_u8mf8_tu(maskedoff,op1,32); +} + + +vuint8mf4_t test___riscv_viota_m_u8mf4_tu(vuint8mf4_t maskedoff,vbool32_t op1,size_t vl) +{ + return __riscv_viota_m_u8mf4_tu(maskedoff,op1,32); +} + + +vuint8mf2_t test___riscv_viota_m_u8mf2_tu(vuint8mf2_t maskedoff,vbool16_t op1,size_t vl) +{ + return __riscv_viota_m_u8mf2_tu(maskedoff,op1,32); +} + + +vuint8m1_t test___riscv_viota_m_u8m1_tu(vuint8m1_t maskedoff,vbool8_t op1,size_t vl) +{ + return __riscv_viota_m_u8m1_tu(maskedoff,op1,32); +} + + +vuint8m2_t test___riscv_viota_m_u8m2_tu(vuint8m2_t maskedoff,vbool4_t op1,size_t vl) +{ + return __riscv_viota_m_u8m2_tu(maskedoff,op1,32); +} + + +vuint8m4_t test___riscv_viota_m_u8m4_tu(vuint8m4_t maskedoff,vbool2_t op1,size_t vl) +{ + return __riscv_viota_m_u8m4_tu(maskedoff,op1,32); +} + + +vuint8m8_t test___riscv_viota_m_u8m8_tu(vuint8m8_t maskedoff,vbool1_t op1,size_t vl) +{ + return __riscv_viota_m_u8m8_tu(maskedoff,op1,32); +} + + +vuint16mf4_t test___riscv_viota_m_u16mf4_tu(vuint16mf4_t maskedoff,vbool64_t op1,size_t vl) +{ + return __riscv_viota_m_u16mf4_tu(maskedoff,op1,32); +} + + +vuint16mf2_t test___riscv_viota_m_u16mf2_tu(vuint16mf2_t maskedoff,vbool32_t op1,size_t vl) +{ + return __riscv_viota_m_u16mf2_tu(maskedoff,op1,32); +} + + +vuint16m1_t test___riscv_viota_m_u16m1_tu(vuint16m1_t maskedoff,vbool16_t op1,size_t vl) +{ + return __riscv_viota_m_u16m1_tu(maskedoff,op1,32); +} + + +vuint16m2_t test___riscv_viota_m_u16m2_tu(vuint16m2_t maskedoff,vbool8_t op1,size_t vl) +{ + return __riscv_viota_m_u16m2_tu(maskedoff,op1,32); +} + + +vuint16m4_t test___riscv_viota_m_u16m4_tu(vuint16m4_t maskedoff,vbool4_t op1,size_t vl) +{ + return __riscv_viota_m_u16m4_tu(maskedoff,op1,32); +} + + +vuint16m8_t test___riscv_viota_m_u16m8_tu(vuint16m8_t maskedoff,vbool2_t op1,size_t vl) +{ + return __riscv_viota_m_u16m8_tu(maskedoff,op1,32); +} + + +vuint32mf2_t test___riscv_viota_m_u32mf2_tu(vuint32mf2_t maskedoff,vbool64_t op1,size_t vl) +{ + return __riscv_viota_m_u32mf2_tu(maskedoff,op1,32); +} + + +vuint32m1_t test___riscv_viota_m_u32m1_tu(vuint32m1_t maskedoff,vbool32_t op1,size_t vl) +{ + return __riscv_viota_m_u32m1_tu(maskedoff,op1,32); +} + + +vuint32m2_t test___riscv_viota_m_u32m2_tu(vuint32m2_t maskedoff,vbool16_t op1,size_t vl) +{ + return __riscv_viota_m_u32m2_tu(maskedoff,op1,32); +} + + +vuint32m4_t test___riscv_viota_m_u32m4_tu(vuint32m4_t maskedoff,vbool8_t op1,size_t vl) +{ + return __riscv_viota_m_u32m4_tu(maskedoff,op1,32); +} + + +vuint32m8_t test___riscv_viota_m_u32m8_tu(vuint32m8_t maskedoff,vbool4_t op1,size_t vl) +{ + return __riscv_viota_m_u32m8_tu(maskedoff,op1,32); +} + + +vuint64m1_t test___riscv_viota_m_u64m1_tu(vuint64m1_t maskedoff,vbool64_t op1,size_t vl) +{ + return __riscv_viota_m_u64m1_tu(maskedoff,op1,32); +} + + +vuint64m2_t test___riscv_viota_m_u64m2_tu(vuint64m2_t maskedoff,vbool32_t op1,size_t vl) +{ + return __riscv_viota_m_u64m2_tu(maskedoff,op1,32); +} + + +vuint64m4_t test___riscv_viota_m_u64m4_tu(vuint64m4_t maskedoff,vbool16_t op1,size_t vl) +{ + return __riscv_viota_m_u64m4_tu(maskedoff,op1,32); +} + + +vuint64m8_t test___riscv_viota_m_u64m8_tu(vuint64m8_t maskedoff,vbool8_t op1,size_t vl) +{ + return __riscv_viota_m_u64m8_tu(maskedoff,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/viota_m_tum-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/viota_m_tum-1.c new file mode 100644 index 00000000000..54bb8c52f8e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/viota_m_tum-1.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_viota_m_u8mf8_tum(vbool64_t mask,vuint8mf8_t maskedoff,vbool64_t op1,size_t vl) +{ + return __riscv_viota_m_u8mf8_tum(mask,maskedoff,op1,vl); +} + + +vuint8mf4_t test___riscv_viota_m_u8mf4_tum(vbool32_t mask,vuint8mf4_t maskedoff,vbool32_t op1,size_t vl) +{ + return __riscv_viota_m_u8mf4_tum(mask,maskedoff,op1,vl); +} + + +vuint8mf2_t test___riscv_viota_m_u8mf2_tum(vbool16_t mask,vuint8mf2_t maskedoff,vbool16_t op1,size_t vl) +{ + return __riscv_viota_m_u8mf2_tum(mask,maskedoff,op1,vl); +} + + +vuint8m1_t test___riscv_viota_m_u8m1_tum(vbool8_t mask,vuint8m1_t maskedoff,vbool8_t op1,size_t vl) +{ + return __riscv_viota_m_u8m1_tum(mask,maskedoff,op1,vl); +} + + +vuint8m2_t test___riscv_viota_m_u8m2_tum(vbool4_t mask,vuint8m2_t maskedoff,vbool4_t op1,size_t vl) +{ + return __riscv_viota_m_u8m2_tum(mask,maskedoff,op1,vl); +} + + +vuint8m4_t test___riscv_viota_m_u8m4_tum(vbool2_t mask,vuint8m4_t maskedoff,vbool2_t op1,size_t vl) +{ + return __riscv_viota_m_u8m4_tum(mask,maskedoff,op1,vl); +} + + +vuint8m8_t test___riscv_viota_m_u8m8_tum(vbool1_t mask,vuint8m8_t maskedoff,vbool1_t op1,size_t vl) +{ + return __riscv_viota_m_u8m8_tum(mask,maskedoff,op1,vl); +} + + +vuint16mf4_t test___riscv_viota_m_u16mf4_tum(vbool64_t mask,vuint16mf4_t maskedoff,vbool64_t op1,size_t vl) +{ + return __riscv_viota_m_u16mf4_tum(mask,maskedoff,op1,vl); +} + + +vuint16mf2_t test___riscv_viota_m_u16mf2_tum(vbool32_t mask,vuint16mf2_t maskedoff,vbool32_t op1,size_t vl) +{ + return __riscv_viota_m_u16mf2_tum(mask,maskedoff,op1,vl); +} + + +vuint16m1_t test___riscv_viota_m_u16m1_tum(vbool16_t mask,vuint16m1_t maskedoff,vbool16_t op1,size_t vl) +{ + return __riscv_viota_m_u16m1_tum(mask,maskedoff,op1,vl); +} + + +vuint16m2_t test___riscv_viota_m_u16m2_tum(vbool8_t mask,vuint16m2_t maskedoff,vbool8_t op1,size_t vl) +{ + return __riscv_viota_m_u16m2_tum(mask,maskedoff,op1,vl); +} + + +vuint16m4_t test___riscv_viota_m_u16m4_tum(vbool4_t mask,vuint16m4_t maskedoff,vbool4_t op1,size_t vl) +{ + return __riscv_viota_m_u16m4_tum(mask,maskedoff,op1,vl); +} + + +vuint16m8_t test___riscv_viota_m_u16m8_tum(vbool2_t mask,vuint16m8_t maskedoff,vbool2_t op1,size_t vl) +{ + return __riscv_viota_m_u16m8_tum(mask,maskedoff,op1,vl); +} + + +vuint32mf2_t test___riscv_viota_m_u32mf2_tum(vbool64_t mask,vuint32mf2_t maskedoff,vbool64_t op1,size_t vl) +{ + return __riscv_viota_m_u32mf2_tum(mask,maskedoff,op1,vl); +} + + +vuint32m1_t test___riscv_viota_m_u32m1_tum(vbool32_t mask,vuint32m1_t maskedoff,vbool32_t op1,size_t vl) +{ + return __riscv_viota_m_u32m1_tum(mask,maskedoff,op1,vl); +} + + +vuint32m2_t test___riscv_viota_m_u32m2_tum(vbool16_t mask,vuint32m2_t maskedoff,vbool16_t op1,size_t vl) +{ + return __riscv_viota_m_u32m2_tum(mask,maskedoff,op1,vl); +} + + +vuint32m4_t test___riscv_viota_m_u32m4_tum(vbool8_t mask,vuint32m4_t maskedoff,vbool8_t op1,size_t vl) +{ + return __riscv_viota_m_u32m4_tum(mask,maskedoff,op1,vl); +} + + +vuint32m8_t test___riscv_viota_m_u32m8_tum(vbool4_t mask,vuint32m8_t maskedoff,vbool4_t op1,size_t vl) +{ + return __riscv_viota_m_u32m8_tum(mask,maskedoff,op1,vl); +} + + +vuint64m1_t test___riscv_viota_m_u64m1_tum(vbool64_t mask,vuint64m1_t maskedoff,vbool64_t op1,size_t vl) +{ + return __riscv_viota_m_u64m1_tum(mask,maskedoff,op1,vl); +} + + +vuint64m2_t test___riscv_viota_m_u64m2_tum(vbool32_t mask,vuint64m2_t maskedoff,vbool32_t op1,size_t vl) +{ + return __riscv_viota_m_u64m2_tum(mask,maskedoff,op1,vl); +} + + +vuint64m4_t test___riscv_viota_m_u64m4_tum(vbool16_t mask,vuint64m4_t maskedoff,vbool16_t op1,size_t vl) +{ + return __riscv_viota_m_u64m4_tum(mask,maskedoff,op1,vl); +} + + +vuint64m8_t test___riscv_viota_m_u64m8_tum(vbool8_t mask,vuint64m8_t maskedoff,vbool8_t op1,size_t vl) +{ + return __riscv_viota_m_u64m8_tum(mask,maskedoff,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/viota_m_tum-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/viota_m_tum-2.c new file mode 100644 index 00000000000..85eb3280239 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/viota_m_tum-2.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_viota_m_u8mf8_tum(vbool64_t mask,vuint8mf8_t maskedoff,vbool64_t op1,size_t vl) +{ + return __riscv_viota_m_u8mf8_tum(mask,maskedoff,op1,31); +} + + +vuint8mf4_t test___riscv_viota_m_u8mf4_tum(vbool32_t mask,vuint8mf4_t maskedoff,vbool32_t op1,size_t vl) +{ + return __riscv_viota_m_u8mf4_tum(mask,maskedoff,op1,31); +} + + +vuint8mf2_t test___riscv_viota_m_u8mf2_tum(vbool16_t mask,vuint8mf2_t maskedoff,vbool16_t op1,size_t vl) +{ + return __riscv_viota_m_u8mf2_tum(mask,maskedoff,op1,31); +} + + +vuint8m1_t test___riscv_viota_m_u8m1_tum(vbool8_t mask,vuint8m1_t maskedoff,vbool8_t op1,size_t vl) +{ + return __riscv_viota_m_u8m1_tum(mask,maskedoff,op1,31); +} + + +vuint8m2_t test___riscv_viota_m_u8m2_tum(vbool4_t mask,vuint8m2_t maskedoff,vbool4_t op1,size_t vl) +{ + return __riscv_viota_m_u8m2_tum(mask,maskedoff,op1,31); +} + + +vuint8m4_t test___riscv_viota_m_u8m4_tum(vbool2_t mask,vuint8m4_t maskedoff,vbool2_t op1,size_t vl) +{ + return __riscv_viota_m_u8m4_tum(mask,maskedoff,op1,31); +} + + +vuint8m8_t test___riscv_viota_m_u8m8_tum(vbool1_t mask,vuint8m8_t maskedoff,vbool1_t op1,size_t vl) +{ + return __riscv_viota_m_u8m8_tum(mask,maskedoff,op1,31); +} + + +vuint16mf4_t test___riscv_viota_m_u16mf4_tum(vbool64_t mask,vuint16mf4_t maskedoff,vbool64_t op1,size_t vl) +{ + return __riscv_viota_m_u16mf4_tum(mask,maskedoff,op1,31); +} + + +vuint16mf2_t test___riscv_viota_m_u16mf2_tum(vbool32_t mask,vuint16mf2_t maskedoff,vbool32_t op1,size_t vl) +{ + return __riscv_viota_m_u16mf2_tum(mask,maskedoff,op1,31); +} + + +vuint16m1_t test___riscv_viota_m_u16m1_tum(vbool16_t mask,vuint16m1_t maskedoff,vbool16_t op1,size_t vl) +{ + return __riscv_viota_m_u16m1_tum(mask,maskedoff,op1,31); +} + + +vuint16m2_t test___riscv_viota_m_u16m2_tum(vbool8_t mask,vuint16m2_t maskedoff,vbool8_t op1,size_t vl) +{ + return __riscv_viota_m_u16m2_tum(mask,maskedoff,op1,31); +} + + +vuint16m4_t test___riscv_viota_m_u16m4_tum(vbool4_t mask,vuint16m4_t maskedoff,vbool4_t op1,size_t vl) +{ + return __riscv_viota_m_u16m4_tum(mask,maskedoff,op1,31); +} + + +vuint16m8_t test___riscv_viota_m_u16m8_tum(vbool2_t mask,vuint16m8_t maskedoff,vbool2_t op1,size_t vl) +{ + return __riscv_viota_m_u16m8_tum(mask,maskedoff,op1,31); +} + + +vuint32mf2_t test___riscv_viota_m_u32mf2_tum(vbool64_t mask,vuint32mf2_t maskedoff,vbool64_t op1,size_t vl) +{ + return __riscv_viota_m_u32mf2_tum(mask,maskedoff,op1,31); +} + + +vuint32m1_t test___riscv_viota_m_u32m1_tum(vbool32_t mask,vuint32m1_t maskedoff,vbool32_t op1,size_t vl) +{ + return __riscv_viota_m_u32m1_tum(mask,maskedoff,op1,31); +} + + +vuint32m2_t test___riscv_viota_m_u32m2_tum(vbool16_t mask,vuint32m2_t maskedoff,vbool16_t op1,size_t vl) +{ + return __riscv_viota_m_u32m2_tum(mask,maskedoff,op1,31); +} + + +vuint32m4_t test___riscv_viota_m_u32m4_tum(vbool8_t mask,vuint32m4_t maskedoff,vbool8_t op1,size_t vl) +{ + return __riscv_viota_m_u32m4_tum(mask,maskedoff,op1,31); +} + + +vuint32m8_t test___riscv_viota_m_u32m8_tum(vbool4_t mask,vuint32m8_t maskedoff,vbool4_t op1,size_t vl) +{ + return __riscv_viota_m_u32m8_tum(mask,maskedoff,op1,31); +} + + +vuint64m1_t test___riscv_viota_m_u64m1_tum(vbool64_t mask,vuint64m1_t maskedoff,vbool64_t op1,size_t vl) +{ + return __riscv_viota_m_u64m1_tum(mask,maskedoff,op1,31); +} + + +vuint64m2_t test___riscv_viota_m_u64m2_tum(vbool32_t mask,vuint64m2_t maskedoff,vbool32_t op1,size_t vl) +{ + return __riscv_viota_m_u64m2_tum(mask,maskedoff,op1,31); +} + + +vuint64m4_t test___riscv_viota_m_u64m4_tum(vbool16_t mask,vuint64m4_t maskedoff,vbool16_t op1,size_t vl) +{ + return __riscv_viota_m_u64m4_tum(mask,maskedoff,op1,31); +} + + +vuint64m8_t test___riscv_viota_m_u64m8_tum(vbool8_t mask,vuint64m8_t maskedoff,vbool8_t op1,size_t vl) +{ + return __riscv_viota_m_u64m8_tum(mask,maskedoff,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/viota_m_tum-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/viota_m_tum-3.c new file mode 100644 index 00000000000..e6a305e4f32 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/viota_m_tum-3.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_viota_m_u8mf8_tum(vbool64_t mask,vuint8mf8_t maskedoff,vbool64_t op1,size_t vl) +{ + return __riscv_viota_m_u8mf8_tum(mask,maskedoff,op1,32); +} + + +vuint8mf4_t test___riscv_viota_m_u8mf4_tum(vbool32_t mask,vuint8mf4_t maskedoff,vbool32_t op1,size_t vl) +{ + return __riscv_viota_m_u8mf4_tum(mask,maskedoff,op1,32); +} + + +vuint8mf2_t test___riscv_viota_m_u8mf2_tum(vbool16_t mask,vuint8mf2_t maskedoff,vbool16_t op1,size_t vl) +{ + return __riscv_viota_m_u8mf2_tum(mask,maskedoff,op1,32); +} + + +vuint8m1_t test___riscv_viota_m_u8m1_tum(vbool8_t mask,vuint8m1_t maskedoff,vbool8_t op1,size_t vl) +{ + return __riscv_viota_m_u8m1_tum(mask,maskedoff,op1,32); +} + + +vuint8m2_t test___riscv_viota_m_u8m2_tum(vbool4_t mask,vuint8m2_t maskedoff,vbool4_t op1,size_t vl) +{ + return __riscv_viota_m_u8m2_tum(mask,maskedoff,op1,32); +} + + +vuint8m4_t test___riscv_viota_m_u8m4_tum(vbool2_t mask,vuint8m4_t maskedoff,vbool2_t op1,size_t vl) +{ + return __riscv_viota_m_u8m4_tum(mask,maskedoff,op1,32); +} + + +vuint8m8_t test___riscv_viota_m_u8m8_tum(vbool1_t mask,vuint8m8_t maskedoff,vbool1_t op1,size_t vl) +{ + return __riscv_viota_m_u8m8_tum(mask,maskedoff,op1,32); +} + + +vuint16mf4_t test___riscv_viota_m_u16mf4_tum(vbool64_t mask,vuint16mf4_t maskedoff,vbool64_t op1,size_t vl) +{ + return __riscv_viota_m_u16mf4_tum(mask,maskedoff,op1,32); +} + + +vuint16mf2_t test___riscv_viota_m_u16mf2_tum(vbool32_t mask,vuint16mf2_t maskedoff,vbool32_t op1,size_t vl) +{ + return __riscv_viota_m_u16mf2_tum(mask,maskedoff,op1,32); +} + + +vuint16m1_t test___riscv_viota_m_u16m1_tum(vbool16_t mask,vuint16m1_t maskedoff,vbool16_t op1,size_t vl) +{ + return __riscv_viota_m_u16m1_tum(mask,maskedoff,op1,32); +} + + +vuint16m2_t test___riscv_viota_m_u16m2_tum(vbool8_t mask,vuint16m2_t maskedoff,vbool8_t op1,size_t vl) +{ + return __riscv_viota_m_u16m2_tum(mask,maskedoff,op1,32); +} + + +vuint16m4_t test___riscv_viota_m_u16m4_tum(vbool4_t mask,vuint16m4_t maskedoff,vbool4_t op1,size_t vl) +{ + return __riscv_viota_m_u16m4_tum(mask,maskedoff,op1,32); +} + + +vuint16m8_t test___riscv_viota_m_u16m8_tum(vbool2_t mask,vuint16m8_t maskedoff,vbool2_t op1,size_t vl) +{ + return __riscv_viota_m_u16m8_tum(mask,maskedoff,op1,32); +} + + +vuint32mf2_t test___riscv_viota_m_u32mf2_tum(vbool64_t mask,vuint32mf2_t maskedoff,vbool64_t op1,size_t vl) +{ + return __riscv_viota_m_u32mf2_tum(mask,maskedoff,op1,32); +} + + +vuint32m1_t test___riscv_viota_m_u32m1_tum(vbool32_t mask,vuint32m1_t maskedoff,vbool32_t op1,size_t vl) +{ + return __riscv_viota_m_u32m1_tum(mask,maskedoff,op1,32); +} + + +vuint32m2_t test___riscv_viota_m_u32m2_tum(vbool16_t mask,vuint32m2_t maskedoff,vbool16_t op1,size_t vl) +{ + return __riscv_viota_m_u32m2_tum(mask,maskedoff,op1,32); +} + + +vuint32m4_t test___riscv_viota_m_u32m4_tum(vbool8_t mask,vuint32m4_t maskedoff,vbool8_t op1,size_t vl) +{ + return __riscv_viota_m_u32m4_tum(mask,maskedoff,op1,32); +} + + +vuint32m8_t test___riscv_viota_m_u32m8_tum(vbool4_t mask,vuint32m8_t maskedoff,vbool4_t op1,size_t vl) +{ + return __riscv_viota_m_u32m8_tum(mask,maskedoff,op1,32); +} + + +vuint64m1_t test___riscv_viota_m_u64m1_tum(vbool64_t mask,vuint64m1_t maskedoff,vbool64_t op1,size_t vl) +{ + return __riscv_viota_m_u64m1_tum(mask,maskedoff,op1,32); +} + + +vuint64m2_t test___riscv_viota_m_u64m2_tum(vbool32_t mask,vuint64m2_t maskedoff,vbool32_t op1,size_t vl) +{ + return __riscv_viota_m_u64m2_tum(mask,maskedoff,op1,32); +} + + +vuint64m4_t test___riscv_viota_m_u64m4_tum(vbool16_t mask,vuint64m4_t maskedoff,vbool16_t op1,size_t vl) +{ + return __riscv_viota_m_u64m4_tum(mask,maskedoff,op1,32); +} + + +vuint64m8_t test___riscv_viota_m_u64m8_tum(vbool8_t mask,vuint64m8_t maskedoff,vbool8_t op1,size_t vl) +{ + return __riscv_viota_m_u64m8_tum(mask,maskedoff,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/viota_m_tumu-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/viota_m_tumu-1.c new file mode 100644 index 00000000000..1b7a610ea88 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/viota_m_tumu-1.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_viota_m_u8mf8_tumu(vbool64_t mask,vuint8mf8_t maskedoff,vbool64_t op1,size_t vl) +{ + return __riscv_viota_m_u8mf8_tumu(mask,maskedoff,op1,vl); +} + + +vuint8mf4_t test___riscv_viota_m_u8mf4_tumu(vbool32_t mask,vuint8mf4_t maskedoff,vbool32_t op1,size_t vl) +{ + return __riscv_viota_m_u8mf4_tumu(mask,maskedoff,op1,vl); +} + + +vuint8mf2_t test___riscv_viota_m_u8mf2_tumu(vbool16_t mask,vuint8mf2_t maskedoff,vbool16_t op1,size_t vl) +{ + return __riscv_viota_m_u8mf2_tumu(mask,maskedoff,op1,vl); +} + + +vuint8m1_t test___riscv_viota_m_u8m1_tumu(vbool8_t mask,vuint8m1_t maskedoff,vbool8_t op1,size_t vl) +{ + return __riscv_viota_m_u8m1_tumu(mask,maskedoff,op1,vl); +} + + +vuint8m2_t test___riscv_viota_m_u8m2_tumu(vbool4_t mask,vuint8m2_t maskedoff,vbool4_t op1,size_t vl) +{ + return __riscv_viota_m_u8m2_tumu(mask,maskedoff,op1,vl); +} + + +vuint8m4_t test___riscv_viota_m_u8m4_tumu(vbool2_t mask,vuint8m4_t maskedoff,vbool2_t op1,size_t vl) +{ + return __riscv_viota_m_u8m4_tumu(mask,maskedoff,op1,vl); +} + + +vuint8m8_t test___riscv_viota_m_u8m8_tumu(vbool1_t mask,vuint8m8_t maskedoff,vbool1_t op1,size_t vl) +{ + return __riscv_viota_m_u8m8_tumu(mask,maskedoff,op1,vl); +} + + +vuint16mf4_t test___riscv_viota_m_u16mf4_tumu(vbool64_t mask,vuint16mf4_t maskedoff,vbool64_t op1,size_t vl) +{ + return __riscv_viota_m_u16mf4_tumu(mask,maskedoff,op1,vl); +} + + +vuint16mf2_t test___riscv_viota_m_u16mf2_tumu(vbool32_t mask,vuint16mf2_t maskedoff,vbool32_t op1,size_t vl) +{ + return __riscv_viota_m_u16mf2_tumu(mask,maskedoff,op1,vl); +} + + +vuint16m1_t test___riscv_viota_m_u16m1_tumu(vbool16_t mask,vuint16m1_t maskedoff,vbool16_t op1,size_t vl) +{ + return __riscv_viota_m_u16m1_tumu(mask,maskedoff,op1,vl); +} + + +vuint16m2_t test___riscv_viota_m_u16m2_tumu(vbool8_t mask,vuint16m2_t maskedoff,vbool8_t op1,size_t vl) +{ + return __riscv_viota_m_u16m2_tumu(mask,maskedoff,op1,vl); +} + + +vuint16m4_t test___riscv_viota_m_u16m4_tumu(vbool4_t mask,vuint16m4_t maskedoff,vbool4_t op1,size_t vl) +{ + return __riscv_viota_m_u16m4_tumu(mask,maskedoff,op1,vl); +} + + +vuint16m8_t test___riscv_viota_m_u16m8_tumu(vbool2_t mask,vuint16m8_t maskedoff,vbool2_t op1,size_t vl) +{ + return __riscv_viota_m_u16m8_tumu(mask,maskedoff,op1,vl); +} + + +vuint32mf2_t test___riscv_viota_m_u32mf2_tumu(vbool64_t mask,vuint32mf2_t maskedoff,vbool64_t op1,size_t vl) +{ + return __riscv_viota_m_u32mf2_tumu(mask,maskedoff,op1,vl); +} + + +vuint32m1_t test___riscv_viota_m_u32m1_tumu(vbool32_t mask,vuint32m1_t maskedoff,vbool32_t op1,size_t vl) +{ + return __riscv_viota_m_u32m1_tumu(mask,maskedoff,op1,vl); +} + + +vuint32m2_t test___riscv_viota_m_u32m2_tumu(vbool16_t mask,vuint32m2_t maskedoff,vbool16_t op1,size_t vl) +{ + return __riscv_viota_m_u32m2_tumu(mask,maskedoff,op1,vl); +} + + +vuint32m4_t test___riscv_viota_m_u32m4_tumu(vbool8_t mask,vuint32m4_t maskedoff,vbool8_t op1,size_t vl) +{ + return __riscv_viota_m_u32m4_tumu(mask,maskedoff,op1,vl); +} + + +vuint32m8_t test___riscv_viota_m_u32m8_tumu(vbool4_t mask,vuint32m8_t maskedoff,vbool4_t op1,size_t vl) +{ + return __riscv_viota_m_u32m8_tumu(mask,maskedoff,op1,vl); +} + + +vuint64m1_t test___riscv_viota_m_u64m1_tumu(vbool64_t mask,vuint64m1_t maskedoff,vbool64_t op1,size_t vl) +{ + return __riscv_viota_m_u64m1_tumu(mask,maskedoff,op1,vl); +} + + +vuint64m2_t test___riscv_viota_m_u64m2_tumu(vbool32_t mask,vuint64m2_t maskedoff,vbool32_t op1,size_t vl) +{ + return __riscv_viota_m_u64m2_tumu(mask,maskedoff,op1,vl); +} + + +vuint64m4_t test___riscv_viota_m_u64m4_tumu(vbool16_t mask,vuint64m4_t maskedoff,vbool16_t op1,size_t vl) +{ + return __riscv_viota_m_u64m4_tumu(mask,maskedoff,op1,vl); +} + + +vuint64m8_t test___riscv_viota_m_u64m8_tumu(vbool8_t mask,vuint64m8_t maskedoff,vbool8_t op1,size_t vl) +{ + return __riscv_viota_m_u64m8_tumu(mask,maskedoff,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/viota_m_tumu-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/viota_m_tumu-2.c new file mode 100644 index 00000000000..41a20e3bc73 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/viota_m_tumu-2.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_viota_m_u8mf8_tumu(vbool64_t mask,vuint8mf8_t maskedoff,vbool64_t op1,size_t vl) +{ + return __riscv_viota_m_u8mf8_tumu(mask,maskedoff,op1,31); +} + + +vuint8mf4_t test___riscv_viota_m_u8mf4_tumu(vbool32_t mask,vuint8mf4_t maskedoff,vbool32_t op1,size_t vl) +{ + return __riscv_viota_m_u8mf4_tumu(mask,maskedoff,op1,31); +} + + +vuint8mf2_t test___riscv_viota_m_u8mf2_tumu(vbool16_t mask,vuint8mf2_t maskedoff,vbool16_t op1,size_t vl) +{ + return __riscv_viota_m_u8mf2_tumu(mask,maskedoff,op1,31); +} + + +vuint8m1_t test___riscv_viota_m_u8m1_tumu(vbool8_t mask,vuint8m1_t maskedoff,vbool8_t op1,size_t vl) +{ + return __riscv_viota_m_u8m1_tumu(mask,maskedoff,op1,31); +} + + +vuint8m2_t test___riscv_viota_m_u8m2_tumu(vbool4_t mask,vuint8m2_t maskedoff,vbool4_t op1,size_t vl) +{ + return __riscv_viota_m_u8m2_tumu(mask,maskedoff,op1,31); +} + + +vuint8m4_t test___riscv_viota_m_u8m4_tumu(vbool2_t mask,vuint8m4_t maskedoff,vbool2_t op1,size_t vl) +{ + return __riscv_viota_m_u8m4_tumu(mask,maskedoff,op1,31); +} + + +vuint8m8_t test___riscv_viota_m_u8m8_tumu(vbool1_t mask,vuint8m8_t maskedoff,vbool1_t op1,size_t vl) +{ + return __riscv_viota_m_u8m8_tumu(mask,maskedoff,op1,31); +} + + +vuint16mf4_t test___riscv_viota_m_u16mf4_tumu(vbool64_t mask,vuint16mf4_t maskedoff,vbool64_t op1,size_t vl) +{ + return __riscv_viota_m_u16mf4_tumu(mask,maskedoff,op1,31); +} + + +vuint16mf2_t test___riscv_viota_m_u16mf2_tumu(vbool32_t mask,vuint16mf2_t maskedoff,vbool32_t op1,size_t vl) +{ + return __riscv_viota_m_u16mf2_tumu(mask,maskedoff,op1,31); +} + + +vuint16m1_t test___riscv_viota_m_u16m1_tumu(vbool16_t mask,vuint16m1_t maskedoff,vbool16_t op1,size_t vl) +{ + return __riscv_viota_m_u16m1_tumu(mask,maskedoff,op1,31); +} + + +vuint16m2_t test___riscv_viota_m_u16m2_tumu(vbool8_t mask,vuint16m2_t maskedoff,vbool8_t op1,size_t vl) +{ + return __riscv_viota_m_u16m2_tumu(mask,maskedoff,op1,31); +} + + +vuint16m4_t test___riscv_viota_m_u16m4_tumu(vbool4_t mask,vuint16m4_t maskedoff,vbool4_t op1,size_t vl) +{ + return __riscv_viota_m_u16m4_tumu(mask,maskedoff,op1,31); +} + + +vuint16m8_t test___riscv_viota_m_u16m8_tumu(vbool2_t mask,vuint16m8_t maskedoff,vbool2_t op1,size_t vl) +{ + return __riscv_viota_m_u16m8_tumu(mask,maskedoff,op1,31); +} + + +vuint32mf2_t test___riscv_viota_m_u32mf2_tumu(vbool64_t mask,vuint32mf2_t maskedoff,vbool64_t op1,size_t vl) +{ + return __riscv_viota_m_u32mf2_tumu(mask,maskedoff,op1,31); +} + + +vuint32m1_t test___riscv_viota_m_u32m1_tumu(vbool32_t mask,vuint32m1_t maskedoff,vbool32_t op1,size_t vl) +{ + return __riscv_viota_m_u32m1_tumu(mask,maskedoff,op1,31); +} + + +vuint32m2_t test___riscv_viota_m_u32m2_tumu(vbool16_t mask,vuint32m2_t maskedoff,vbool16_t op1,size_t vl) +{ + return __riscv_viota_m_u32m2_tumu(mask,maskedoff,op1,31); +} + + +vuint32m4_t test___riscv_viota_m_u32m4_tumu(vbool8_t mask,vuint32m4_t maskedoff,vbool8_t op1,size_t vl) +{ + return __riscv_viota_m_u32m4_tumu(mask,maskedoff,op1,31); +} + + +vuint32m8_t test___riscv_viota_m_u32m8_tumu(vbool4_t mask,vuint32m8_t maskedoff,vbool4_t op1,size_t vl) +{ + return __riscv_viota_m_u32m8_tumu(mask,maskedoff,op1,31); +} + + +vuint64m1_t test___riscv_viota_m_u64m1_tumu(vbool64_t mask,vuint64m1_t maskedoff,vbool64_t op1,size_t vl) +{ + return __riscv_viota_m_u64m1_tumu(mask,maskedoff,op1,31); +} + + +vuint64m2_t test___riscv_viota_m_u64m2_tumu(vbool32_t mask,vuint64m2_t maskedoff,vbool32_t op1,size_t vl) +{ + return __riscv_viota_m_u64m2_tumu(mask,maskedoff,op1,31); +} + + +vuint64m4_t test___riscv_viota_m_u64m4_tumu(vbool16_t mask,vuint64m4_t maskedoff,vbool16_t op1,size_t vl) +{ + return __riscv_viota_m_u64m4_tumu(mask,maskedoff,op1,31); +} + + +vuint64m8_t test___riscv_viota_m_u64m8_tumu(vbool8_t mask,vuint64m8_t maskedoff,vbool8_t op1,size_t vl) +{ + return __riscv_viota_m_u64m8_tumu(mask,maskedoff,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/viota_m_tumu-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/viota_m_tumu-3.c new file mode 100644 index 00000000000..b84509c8764 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/viota_m_tumu-3.c @@ -0,0 +1,160 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vuint8mf8_t test___riscv_viota_m_u8mf8_tumu(vbool64_t mask,vuint8mf8_t maskedoff,vbool64_t op1,size_t vl) +{ + return __riscv_viota_m_u8mf8_tumu(mask,maskedoff,op1,32); +} + + +vuint8mf4_t test___riscv_viota_m_u8mf4_tumu(vbool32_t mask,vuint8mf4_t maskedoff,vbool32_t op1,size_t vl) +{ + return __riscv_viota_m_u8mf4_tumu(mask,maskedoff,op1,32); +} + + +vuint8mf2_t test___riscv_viota_m_u8mf2_tumu(vbool16_t mask,vuint8mf2_t maskedoff,vbool16_t op1,size_t vl) +{ + return __riscv_viota_m_u8mf2_tumu(mask,maskedoff,op1,32); +} + + +vuint8m1_t test___riscv_viota_m_u8m1_tumu(vbool8_t mask,vuint8m1_t maskedoff,vbool8_t op1,size_t vl) +{ + return __riscv_viota_m_u8m1_tumu(mask,maskedoff,op1,32); +} + + +vuint8m2_t test___riscv_viota_m_u8m2_tumu(vbool4_t mask,vuint8m2_t maskedoff,vbool4_t op1,size_t vl) +{ + return __riscv_viota_m_u8m2_tumu(mask,maskedoff,op1,32); +} + + +vuint8m4_t test___riscv_viota_m_u8m4_tumu(vbool2_t mask,vuint8m4_t maskedoff,vbool2_t op1,size_t vl) +{ + return __riscv_viota_m_u8m4_tumu(mask,maskedoff,op1,32); +} + + +vuint8m8_t test___riscv_viota_m_u8m8_tumu(vbool1_t mask,vuint8m8_t maskedoff,vbool1_t op1,size_t vl) +{ + return __riscv_viota_m_u8m8_tumu(mask,maskedoff,op1,32); +} + + +vuint16mf4_t test___riscv_viota_m_u16mf4_tumu(vbool64_t mask,vuint16mf4_t maskedoff,vbool64_t op1,size_t vl) +{ + return __riscv_viota_m_u16mf4_tumu(mask,maskedoff,op1,32); +} + + +vuint16mf2_t test___riscv_viota_m_u16mf2_tumu(vbool32_t mask,vuint16mf2_t maskedoff,vbool32_t op1,size_t vl) +{ + return __riscv_viota_m_u16mf2_tumu(mask,maskedoff,op1,32); +} + + +vuint16m1_t test___riscv_viota_m_u16m1_tumu(vbool16_t mask,vuint16m1_t maskedoff,vbool16_t op1,size_t vl) +{ + return __riscv_viota_m_u16m1_tumu(mask,maskedoff,op1,32); +} + + +vuint16m2_t test___riscv_viota_m_u16m2_tumu(vbool8_t mask,vuint16m2_t maskedoff,vbool8_t op1,size_t vl) +{ + return __riscv_viota_m_u16m2_tumu(mask,maskedoff,op1,32); +} + + +vuint16m4_t test___riscv_viota_m_u16m4_tumu(vbool4_t mask,vuint16m4_t maskedoff,vbool4_t op1,size_t vl) +{ + return __riscv_viota_m_u16m4_tumu(mask,maskedoff,op1,32); +} + + +vuint16m8_t test___riscv_viota_m_u16m8_tumu(vbool2_t mask,vuint16m8_t maskedoff,vbool2_t op1,size_t vl) +{ + return __riscv_viota_m_u16m8_tumu(mask,maskedoff,op1,32); +} + + +vuint32mf2_t test___riscv_viota_m_u32mf2_tumu(vbool64_t mask,vuint32mf2_t maskedoff,vbool64_t op1,size_t vl) +{ + return __riscv_viota_m_u32mf2_tumu(mask,maskedoff,op1,32); +} + + +vuint32m1_t test___riscv_viota_m_u32m1_tumu(vbool32_t mask,vuint32m1_t maskedoff,vbool32_t op1,size_t vl) +{ + return __riscv_viota_m_u32m1_tumu(mask,maskedoff,op1,32); +} + + +vuint32m2_t test___riscv_viota_m_u32m2_tumu(vbool16_t mask,vuint32m2_t maskedoff,vbool16_t op1,size_t vl) +{ + return __riscv_viota_m_u32m2_tumu(mask,maskedoff,op1,32); +} + + +vuint32m4_t test___riscv_viota_m_u32m4_tumu(vbool8_t mask,vuint32m4_t maskedoff,vbool8_t op1,size_t vl) +{ + return __riscv_viota_m_u32m4_tumu(mask,maskedoff,op1,32); +} + + +vuint32m8_t test___riscv_viota_m_u32m8_tumu(vbool4_t mask,vuint32m8_t maskedoff,vbool4_t op1,size_t vl) +{ + return __riscv_viota_m_u32m8_tumu(mask,maskedoff,op1,32); +} + + +vuint64m1_t test___riscv_viota_m_u64m1_tumu(vbool64_t mask,vuint64m1_t maskedoff,vbool64_t op1,size_t vl) +{ + return __riscv_viota_m_u64m1_tumu(mask,maskedoff,op1,32); +} + + +vuint64m2_t test___riscv_viota_m_u64m2_tumu(vbool32_t mask,vuint64m2_t maskedoff,vbool32_t op1,size_t vl) +{ + return __riscv_viota_m_u64m2_tumu(mask,maskedoff,op1,32); +} + + +vuint64m4_t test___riscv_viota_m_u64m4_tumu(vbool16_t mask,vuint64m4_t maskedoff,vbool16_t op1,size_t vl) +{ + return __riscv_viota_m_u64m4_tumu(mask,maskedoff,op1,32); +} + + +vuint64m8_t test___riscv_viota_m_u64m8_tumu(vbool8_t mask,vuint64m8_t maskedoff,vbool8_t op1,size_t vl) +{ + return __riscv_viota_m_u64m8_tumu(mask,maskedoff,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+viota\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t} 1 } } */ -- 2.36.1