From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtpbgau2.qq.com (smtpbgau2.qq.com [54.206.34.216]) by sourceware.org (Postfix) with ESMTPS id C8ABE3858D33 for ; Thu, 16 Feb 2023 03:42:06 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org C8ABE3858D33 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp76t1676518920t0492qxn Received: from server1.localdomain ( [58.60.1.22]) by bizesmtp.qq.com (ESMTP) with id ; Thu, 16 Feb 2023 11:41:59 +0800 (CST) X-QQ-SSF: 01400000000000E0M000000A0000000 X-QQ-FEAT: D2GZf6M6C/gRa4KzJBDFwi++BVJodjjZ6i39ssGcb7dmM5sZygy6XT7oIP9xq 7d/ehzzmj93xi3eNxhrYgD+vvsCVNPg36cdsQ/TQf5d2HT048qAZEixO1NFL30urx4cGNwX 6tAZO+N7mNaLngocqtPA3BY0mKMlKKCMfmFRPXvgp7B0TavUztO4ZvNmrK408qK17UkPrxr viJ/Dd2SqEZwhEPDgJAhqJu56URxdSg9V6+GM8NKBs38CeQJSRYYpWN4rhaszqdbKGSiPqr bnvJm531i5uhZ9yt2B99Zj+LAdE2b1NJF5WglVrgUL58kelN8Fwp4RdZfzZ5sG2+yBZxrR/ vZsjdYC4XPwEpenRDoxjrv3O2/04DNx4t1MrR9RvyaYB6+sdQ4= X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, Ju-Zhe Zhong Subject: [PATCH] RISC-V: Add vm* C++ api tests Date: Thu, 16 Feb 2023 11:41:58 +0800 Message-Id: <20230216034158.17684-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,RCVD_IN_BARRACUDACENTRAL,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Ju-Zhe Zhong gcc/testsuite/ChangeLog: * g++.target/riscv/rvv/base/vmand_mm-1.C: New test. * g++.target/riscv/rvv/base/vmand_mm-2.C: New test. * g++.target/riscv/rvv/base/vmand_mm-3.C: New test. * g++.target/riscv/rvv/base/vmandn_mm-1.C: New test. * g++.target/riscv/rvv/base/vmandn_mm-2.C: New test. * g++.target/riscv/rvv/base/vmandn_mm-3.C: New test. * g++.target/riscv/rvv/base/vmclr_m_m-1.C: New test. * g++.target/riscv/rvv/base/vmclr_m_m-2.C: New test. * g++.target/riscv/rvv/base/vmclr_m_m-3.C: New test. * g++.target/riscv/rvv/base/vmmv_mm-1.C: New test. * g++.target/riscv/rvv/base/vmmv_mm-2.C: New test. * g++.target/riscv/rvv/base/vmmv_mm-3.C: New test. * g++.target/riscv/rvv/base/vmnand_mm-1.C: New test. * g++.target/riscv/rvv/base/vmnand_mm-2.C: New test. * g++.target/riscv/rvv/base/vmnand_mm-3.C: New test. * g++.target/riscv/rvv/base/vmnor_mm-1.C: New test. * g++.target/riscv/rvv/base/vmnor_mm-2.C: New test. * g++.target/riscv/rvv/base/vmnor_mm-3.C: New test. * g++.target/riscv/rvv/base/vmnot_mm-1.C: New test. * g++.target/riscv/rvv/base/vmnot_mm-2.C: New test. * g++.target/riscv/rvv/base/vmnot_mm-3.C: New test. * g++.target/riscv/rvv/base/vmor_mm-1.C: New test. * g++.target/riscv/rvv/base/vmor_mm-2.C: New test. * g++.target/riscv/rvv/base/vmor_mm-3.C: New test. * g++.target/riscv/rvv/base/vmorn_mm-1.C: New test. * g++.target/riscv/rvv/base/vmorn_mm-2.C: New test. * g++.target/riscv/rvv/base/vmorn_mm-3.C: New test. * g++.target/riscv/rvv/base/vmsbf_m-1.C: New test. * g++.target/riscv/rvv/base/vmsbf_m-2.C: New test. * g++.target/riscv/rvv/base/vmsbf_m-3.C: New test. * g++.target/riscv/rvv/base/vmsbf_m_mu-1.C: New test. * g++.target/riscv/rvv/base/vmsbf_m_mu-2.C: New test. * g++.target/riscv/rvv/base/vmsbf_m_mu-3.C: New test. * g++.target/riscv/rvv/base/vmset_m_m-1.C: New test. * g++.target/riscv/rvv/base/vmset_m_m-2.C: New test. * g++.target/riscv/rvv/base/vmset_m_m-3.C: New test. * g++.target/riscv/rvv/base/vmsif_m-1.C: New test. * g++.target/riscv/rvv/base/vmsif_m-2.C: New test. * g++.target/riscv/rvv/base/vmsif_m-3.C: New test. * g++.target/riscv/rvv/base/vmsif_m_mu-1.C: New test. * g++.target/riscv/rvv/base/vmsif_m_mu-2.C: New test. * g++.target/riscv/rvv/base/vmsif_m_mu-3.C: New test. * g++.target/riscv/rvv/base/vmsof_m-1.C: New test. * g++.target/riscv/rvv/base/vmsof_m-2.C: New test. * g++.target/riscv/rvv/base/vmsof_m-3.C: New test. * g++.target/riscv/rvv/base/vmsof_m_mu-1.C: New test. * g++.target/riscv/rvv/base/vmsof_m_mu-2.C: New test. * g++.target/riscv/rvv/base/vmsof_m_mu-3.C: New test. * g++.target/riscv/rvv/base/vmxnor_mm-1.C: New test. * g++.target/riscv/rvv/base/vmxnor_mm-2.C: New test. * g++.target/riscv/rvv/base/vmxnor_mm-3.C: New test. * g++.target/riscv/rvv/base/vmxor_mm-1.C: New test. * g++.target/riscv/rvv/base/vmxor_mm-2.C: New test. * g++.target/riscv/rvv/base/vmxor_mm-3.C: New test. --- .../g++.target/riscv/rvv/base/vmand_mm-1.C | 55 +++++++++ .../g++.target/riscv/rvv/base/vmand_mm-2.C | 55 +++++++++ .../g++.target/riscv/rvv/base/vmand_mm-3.C | 55 +++++++++ .../g++.target/riscv/rvv/base/vmandn_mm-1.C | 55 +++++++++ .../g++.target/riscv/rvv/base/vmandn_mm-2.C | 55 +++++++++ .../g++.target/riscv/rvv/base/vmandn_mm-3.C | 55 +++++++++ .../g++.target/riscv/rvv/base/vmclr_m_m-1.C | 55 +++++++++ .../g++.target/riscv/rvv/base/vmclr_m_m-2.C | 55 +++++++++ .../g++.target/riscv/rvv/base/vmclr_m_m-3.C | 55 +++++++++ .../g++.target/riscv/rvv/base/vmmv_mm-1.C | 55 +++++++++ .../g++.target/riscv/rvv/base/vmmv_mm-2.C | 55 +++++++++ .../g++.target/riscv/rvv/base/vmmv_mm-3.C | 55 +++++++++ .../g++.target/riscv/rvv/base/vmnand_mm-1.C | 55 +++++++++ .../g++.target/riscv/rvv/base/vmnand_mm-2.C | 55 +++++++++ .../g++.target/riscv/rvv/base/vmnand_mm-3.C | 55 +++++++++ .../g++.target/riscv/rvv/base/vmnor_mm-1.C | 55 +++++++++ .../g++.target/riscv/rvv/base/vmnor_mm-2.C | 55 +++++++++ .../g++.target/riscv/rvv/base/vmnor_mm-3.C | 55 +++++++++ .../g++.target/riscv/rvv/base/vmnot_mm-1.C | 55 +++++++++ .../g++.target/riscv/rvv/base/vmnot_mm-2.C | 55 +++++++++ .../g++.target/riscv/rvv/base/vmnot_mm-3.C | 55 +++++++++ .../g++.target/riscv/rvv/base/vmor_mm-1.C | 55 +++++++++ .../g++.target/riscv/rvv/base/vmor_mm-2.C | 55 +++++++++ .../g++.target/riscv/rvv/base/vmor_mm-3.C | 55 +++++++++ .../g++.target/riscv/rvv/base/vmorn_mm-1.C | 55 +++++++++ .../g++.target/riscv/rvv/base/vmorn_mm-2.C | 55 +++++++++ .../g++.target/riscv/rvv/base/vmorn_mm-3.C | 55 +++++++++ .../g++.target/riscv/rvv/base/vmsbf_m-1.C | 104 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vmsbf_m-2.C | 104 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vmsbf_m-3.C | 104 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vmsbf_m_mu-1.C | 55 +++++++++ .../g++.target/riscv/rvv/base/vmsbf_m_mu-2.C | 55 +++++++++ .../g++.target/riscv/rvv/base/vmsbf_m_mu-3.C | 55 +++++++++ .../g++.target/riscv/rvv/base/vmset_m_m-1.C | 55 +++++++++ .../g++.target/riscv/rvv/base/vmset_m_m-2.C | 55 +++++++++ .../g++.target/riscv/rvv/base/vmset_m_m-3.C | 55 +++++++++ .../g++.target/riscv/rvv/base/vmsif_m-1.C | 104 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vmsif_m-2.C | 104 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vmsif_m-3.C | 104 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vmsif_m_mu-1.C | 55 +++++++++ .../g++.target/riscv/rvv/base/vmsif_m_mu-2.C | 55 +++++++++ .../g++.target/riscv/rvv/base/vmsif_m_mu-3.C | 55 +++++++++ .../g++.target/riscv/rvv/base/vmsof_m-1.C | 104 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vmsof_m-2.C | 104 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vmsof_m-3.C | 104 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vmsof_m_mu-1.C | 55 +++++++++ .../g++.target/riscv/rvv/base/vmsof_m_mu-2.C | 55 +++++++++ .../g++.target/riscv/rvv/base/vmsof_m_mu-3.C | 55 +++++++++ .../g++.target/riscv/rvv/base/vmxnor_mm-1.C | 55 +++++++++ .../g++.target/riscv/rvv/base/vmxnor_mm-2.C | 55 +++++++++ .../g++.target/riscv/rvv/base/vmxnor_mm-3.C | 55 +++++++++ .../g++.target/riscv/rvv/base/vmxor_mm-1.C | 55 +++++++++ .../g++.target/riscv/rvv/base/vmxor_mm-2.C | 55 +++++++++ .../g++.target/riscv/rvv/base/vmxor_mm-3.C | 55 +++++++++ 54 files changed, 3411 insertions(+) create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmand_mm-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmand_mm-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmand_mm-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmandn_mm-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmandn_mm-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmandn_mm-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmclr_m_m-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmclr_m_m-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmclr_m_m-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmmv_mm-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmmv_mm-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmmv_mm-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmnand_mm-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmnand_mm-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmnand_mm-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmnor_mm-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmnor_mm-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmnor_mm-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmnot_mm-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmnot_mm-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmnot_mm-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmor_mm-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmor_mm-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmor_mm-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmorn_mm-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmorn_mm-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmorn_mm-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsbf_m-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsbf_m-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsbf_m-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsbf_m_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsbf_m_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsbf_m_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmset_m_m-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmset_m_m-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmset_m_m-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsif_m-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsif_m-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsif_m-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsif_m_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsif_m_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsif_m_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsof_m-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsof_m-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsof_m-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsof_m_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsof_m_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmsof_m_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmxnor_mm-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmxnor_mm-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmxnor_mm-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmxor_mm-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmxor_mm-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmxor_mm-3.C diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmand_mm-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmand_mm-1.C new file mode 100644 index 00000000000..7bf420fe32f --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmand_mm-1.C @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmand(vbool1_t op1,vbool1_t op2,size_t vl) +{ + return __riscv_vmand(op1,op2,vl); +} + + +vbool2_t test___riscv_vmand(vbool2_t op1,vbool2_t op2,size_t vl) +{ + return __riscv_vmand(op1,op2,vl); +} + + +vbool4_t test___riscv_vmand(vbool4_t op1,vbool4_t op2,size_t vl) +{ + return __riscv_vmand(op1,op2,vl); +} + + +vbool8_t test___riscv_vmand(vbool8_t op1,vbool8_t op2,size_t vl) +{ + return __riscv_vmand(op1,op2,vl); +} + + +vbool16_t test___riscv_vmand(vbool16_t op1,vbool16_t op2,size_t vl) +{ + return __riscv_vmand(op1,op2,vl); +} + + +vbool32_t test___riscv_vmand(vbool32_t op1,vbool32_t op2,size_t vl) +{ + return __riscv_vmand(op1,op2,vl); +} + + +vbool64_t test___riscv_vmand(vbool64_t op1,vbool64_t op2,size_t vl) +{ + return __riscv_vmand(op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmand_mm-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmand_mm-2.C new file mode 100644 index 00000000000..3e4f78e0f6d --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmand_mm-2.C @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmand(vbool1_t op1,vbool1_t op2,size_t vl) +{ + return __riscv_vmand(op1,op2,31); +} + + +vbool2_t test___riscv_vmand(vbool2_t op1,vbool2_t op2,size_t vl) +{ + return __riscv_vmand(op1,op2,31); +} + + +vbool4_t test___riscv_vmand(vbool4_t op1,vbool4_t op2,size_t vl) +{ + return __riscv_vmand(op1,op2,31); +} + + +vbool8_t test___riscv_vmand(vbool8_t op1,vbool8_t op2,size_t vl) +{ + return __riscv_vmand(op1,op2,31); +} + + +vbool16_t test___riscv_vmand(vbool16_t op1,vbool16_t op2,size_t vl) +{ + return __riscv_vmand(op1,op2,31); +} + + +vbool32_t test___riscv_vmand(vbool32_t op1,vbool32_t op2,size_t vl) +{ + return __riscv_vmand(op1,op2,31); +} + + +vbool64_t test___riscv_vmand(vbool64_t op1,vbool64_t op2,size_t vl) +{ + return __riscv_vmand(op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmand_mm-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmand_mm-3.C new file mode 100644 index 00000000000..2f6dcc4d547 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmand_mm-3.C @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmand(vbool1_t op1,vbool1_t op2,size_t vl) +{ + return __riscv_vmand(op1,op2,32); +} + + +vbool2_t test___riscv_vmand(vbool2_t op1,vbool2_t op2,size_t vl) +{ + return __riscv_vmand(op1,op2,32); +} + + +vbool4_t test___riscv_vmand(vbool4_t op1,vbool4_t op2,size_t vl) +{ + return __riscv_vmand(op1,op2,32); +} + + +vbool8_t test___riscv_vmand(vbool8_t op1,vbool8_t op2,size_t vl) +{ + return __riscv_vmand(op1,op2,32); +} + + +vbool16_t test___riscv_vmand(vbool16_t op1,vbool16_t op2,size_t vl) +{ + return __riscv_vmand(op1,op2,32); +} + + +vbool32_t test___riscv_vmand(vbool32_t op1,vbool32_t op2,size_t vl) +{ + return __riscv_vmand(op1,op2,32); +} + + +vbool64_t test___riscv_vmand(vbool64_t op1,vbool64_t op2,size_t vl) +{ + return __riscv_vmand(op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmandn_mm-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmandn_mm-1.C new file mode 100644 index 00000000000..f1a5ef70e83 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmandn_mm-1.C @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmandn(vbool1_t op1,vbool1_t op2,size_t vl) +{ + return __riscv_vmandn(op1,op2,vl); +} + + +vbool2_t test___riscv_vmandn(vbool2_t op1,vbool2_t op2,size_t vl) +{ + return __riscv_vmandn(op1,op2,vl); +} + + +vbool4_t test___riscv_vmandn(vbool4_t op1,vbool4_t op2,size_t vl) +{ + return __riscv_vmandn(op1,op2,vl); +} + + +vbool8_t test___riscv_vmandn(vbool8_t op1,vbool8_t op2,size_t vl) +{ + return __riscv_vmandn(op1,op2,vl); +} + + +vbool16_t test___riscv_vmandn(vbool16_t op1,vbool16_t op2,size_t vl) +{ + return __riscv_vmandn(op1,op2,vl); +} + + +vbool32_t test___riscv_vmandn(vbool32_t op1,vbool32_t op2,size_t vl) +{ + return __riscv_vmandn(op1,op2,vl); +} + + +vbool64_t test___riscv_vmandn(vbool64_t op1,vbool64_t op2,size_t vl) +{ + return __riscv_vmandn(op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmandn_mm-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmandn_mm-2.C new file mode 100644 index 00000000000..073b5d645b6 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmandn_mm-2.C @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmandn(vbool1_t op1,vbool1_t op2,size_t vl) +{ + return __riscv_vmandn(op1,op2,31); +} + + +vbool2_t test___riscv_vmandn(vbool2_t op1,vbool2_t op2,size_t vl) +{ + return __riscv_vmandn(op1,op2,31); +} + + +vbool4_t test___riscv_vmandn(vbool4_t op1,vbool4_t op2,size_t vl) +{ + return __riscv_vmandn(op1,op2,31); +} + + +vbool8_t test___riscv_vmandn(vbool8_t op1,vbool8_t op2,size_t vl) +{ + return __riscv_vmandn(op1,op2,31); +} + + +vbool16_t test___riscv_vmandn(vbool16_t op1,vbool16_t op2,size_t vl) +{ + return __riscv_vmandn(op1,op2,31); +} + + +vbool32_t test___riscv_vmandn(vbool32_t op1,vbool32_t op2,size_t vl) +{ + return __riscv_vmandn(op1,op2,31); +} + + +vbool64_t test___riscv_vmandn(vbool64_t op1,vbool64_t op2,size_t vl) +{ + return __riscv_vmandn(op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmandn_mm-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmandn_mm-3.C new file mode 100644 index 00000000000..710674d714e --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmandn_mm-3.C @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmandn(vbool1_t op1,vbool1_t op2,size_t vl) +{ + return __riscv_vmandn(op1,op2,32); +} + + +vbool2_t test___riscv_vmandn(vbool2_t op1,vbool2_t op2,size_t vl) +{ + return __riscv_vmandn(op1,op2,32); +} + + +vbool4_t test___riscv_vmandn(vbool4_t op1,vbool4_t op2,size_t vl) +{ + return __riscv_vmandn(op1,op2,32); +} + + +vbool8_t test___riscv_vmandn(vbool8_t op1,vbool8_t op2,size_t vl) +{ + return __riscv_vmandn(op1,op2,32); +} + + +vbool16_t test___riscv_vmandn(vbool16_t op1,vbool16_t op2,size_t vl) +{ + return __riscv_vmandn(op1,op2,32); +} + + +vbool32_t test___riscv_vmandn(vbool32_t op1,vbool32_t op2,size_t vl) +{ + return __riscv_vmandn(op1,op2,32); +} + + +vbool64_t test___riscv_vmandn(vbool64_t op1,vbool64_t op2,size_t vl) +{ + return __riscv_vmandn(op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmandn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmclr_m_m-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmclr_m_m-1.C new file mode 100644 index 00000000000..c662c046f88 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmclr_m_m-1.C @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmclr_m_b1(size_t vl) +{ + return __riscv_vmclr_m_b1(vl); +} + + +vbool2_t test___riscv_vmclr_m_b2(size_t vl) +{ + return __riscv_vmclr_m_b2(vl); +} + + +vbool4_t test___riscv_vmclr_m_b4(size_t vl) +{ + return __riscv_vmclr_m_b4(vl); +} + + +vbool8_t test___riscv_vmclr_m_b8(size_t vl) +{ + return __riscv_vmclr_m_b8(vl); +} + + +vbool16_t test___riscv_vmclr_m_b16(size_t vl) +{ + return __riscv_vmclr_m_b16(vl); +} + + +vbool32_t test___riscv_vmclr_m_b32(size_t vl) +{ + return __riscv_vmclr_m_b32(vl); +} + + +vbool64_t test___riscv_vmclr_m_b64(size_t vl) +{ + return __riscv_vmclr_m_b64(vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmclr_m_m-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmclr_m_m-2.C new file mode 100644 index 00000000000..2fdabd45027 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmclr_m_m-2.C @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmclr_m_b1(size_t vl) +{ + return __riscv_vmclr_m_b1(31); +} + + +vbool2_t test___riscv_vmclr_m_b2(size_t vl) +{ + return __riscv_vmclr_m_b2(31); +} + + +vbool4_t test___riscv_vmclr_m_b4(size_t vl) +{ + return __riscv_vmclr_m_b4(31); +} + + +vbool8_t test___riscv_vmclr_m_b8(size_t vl) +{ + return __riscv_vmclr_m_b8(31); +} + + +vbool16_t test___riscv_vmclr_m_b16(size_t vl) +{ + return __riscv_vmclr_m_b16(31); +} + + +vbool32_t test___riscv_vmclr_m_b32(size_t vl) +{ + return __riscv_vmclr_m_b32(31); +} + + +vbool64_t test___riscv_vmclr_m_b64(size_t vl) +{ + return __riscv_vmclr_m_b64(31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmclr_m_m-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmclr_m_m-3.C new file mode 100644 index 00000000000..d816c5fe79a --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmclr_m_m-3.C @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmclr_m_b1(size_t vl) +{ + return __riscv_vmclr_m_b1(32); +} + + +vbool2_t test___riscv_vmclr_m_b2(size_t vl) +{ + return __riscv_vmclr_m_b2(32); +} + + +vbool4_t test___riscv_vmclr_m_b4(size_t vl) +{ + return __riscv_vmclr_m_b4(32); +} + + +vbool8_t test___riscv_vmclr_m_b8(size_t vl) +{ + return __riscv_vmclr_m_b8(32); +} + + +vbool16_t test___riscv_vmclr_m_b16(size_t vl) +{ + return __riscv_vmclr_m_b16(32); +} + + +vbool32_t test___riscv_vmclr_m_b32(size_t vl) +{ + return __riscv_vmclr_m_b32(32); +} + + +vbool64_t test___riscv_vmclr_m_b64(size_t vl) +{ + return __riscv_vmclr_m_b64(32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmclr\.m\s+v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmmv_mm-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmmv_mm-1.C new file mode 100644 index 00000000000..de2a40c17f5 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmmv_mm-1.C @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmmv(vbool1_t op1,size_t vl) +{ + return __riscv_vmmv(op1,vl); +} + + +vbool2_t test___riscv_vmmv(vbool2_t op1,size_t vl) +{ + return __riscv_vmmv(op1,vl); +} + + +vbool4_t test___riscv_vmmv(vbool4_t op1,size_t vl) +{ + return __riscv_vmmv(op1,vl); +} + + +vbool8_t test___riscv_vmmv(vbool8_t op1,size_t vl) +{ + return __riscv_vmmv(op1,vl); +} + + +vbool16_t test___riscv_vmmv(vbool16_t op1,size_t vl) +{ + return __riscv_vmmv(op1,vl); +} + + +vbool32_t test___riscv_vmmv(vbool32_t op1,size_t vl) +{ + return __riscv_vmmv(op1,vl); +} + + +vbool64_t test___riscv_vmmv(vbool64_t op1,size_t vl) +{ + return __riscv_vmmv(op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmmv_mm-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmmv_mm-2.C new file mode 100644 index 00000000000..07d97542327 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmmv_mm-2.C @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmmv(vbool1_t op1,size_t vl) +{ + return __riscv_vmmv(op1,31); +} + + +vbool2_t test___riscv_vmmv(vbool2_t op1,size_t vl) +{ + return __riscv_vmmv(op1,31); +} + + +vbool4_t test___riscv_vmmv(vbool4_t op1,size_t vl) +{ + return __riscv_vmmv(op1,31); +} + + +vbool8_t test___riscv_vmmv(vbool8_t op1,size_t vl) +{ + return __riscv_vmmv(op1,31); +} + + +vbool16_t test___riscv_vmmv(vbool16_t op1,size_t vl) +{ + return __riscv_vmmv(op1,31); +} + + +vbool32_t test___riscv_vmmv(vbool32_t op1,size_t vl) +{ + return __riscv_vmmv(op1,31); +} + + +vbool64_t test___riscv_vmmv(vbool64_t op1,size_t vl) +{ + return __riscv_vmmv(op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmmv_mm-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmmv_mm-3.C new file mode 100644 index 00000000000..7399ebf8fd0 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmmv_mm-3.C @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmmv(vbool1_t op1,size_t vl) +{ + return __riscv_vmmv(op1,32); +} + + +vbool2_t test___riscv_vmmv(vbool2_t op1,size_t vl) +{ + return __riscv_vmmv(op1,32); +} + + +vbool4_t test___riscv_vmmv(vbool4_t op1,size_t vl) +{ + return __riscv_vmmv(op1,32); +} + + +vbool8_t test___riscv_vmmv(vbool8_t op1,size_t vl) +{ + return __riscv_vmmv(op1,32); +} + + +vbool16_t test___riscv_vmmv(vbool16_t op1,size_t vl) +{ + return __riscv_vmmv(op1,32); +} + + +vbool32_t test___riscv_vmmv(vbool32_t op1,size_t vl) +{ + return __riscv_vmmv(op1,32); +} + + +vbool64_t test___riscv_vmmv(vbool64_t op1,size_t vl) +{ + return __riscv_vmmv(op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmmv\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmnand_mm-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmnand_mm-1.C new file mode 100644 index 00000000000..8442780dce1 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmnand_mm-1.C @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmnand(vbool1_t op1,vbool1_t op2,size_t vl) +{ + return __riscv_vmnand(op1,op2,vl); +} + + +vbool2_t test___riscv_vmnand(vbool2_t op1,vbool2_t op2,size_t vl) +{ + return __riscv_vmnand(op1,op2,vl); +} + + +vbool4_t test___riscv_vmnand(vbool4_t op1,vbool4_t op2,size_t vl) +{ + return __riscv_vmnand(op1,op2,vl); +} + + +vbool8_t test___riscv_vmnand(vbool8_t op1,vbool8_t op2,size_t vl) +{ + return __riscv_vmnand(op1,op2,vl); +} + + +vbool16_t test___riscv_vmnand(vbool16_t op1,vbool16_t op2,size_t vl) +{ + return __riscv_vmnand(op1,op2,vl); +} + + +vbool32_t test___riscv_vmnand(vbool32_t op1,vbool32_t op2,size_t vl) +{ + return __riscv_vmnand(op1,op2,vl); +} + + +vbool64_t test___riscv_vmnand(vbool64_t op1,vbool64_t op2,size_t vl) +{ + return __riscv_vmnand(op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmnand_mm-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmnand_mm-2.C new file mode 100644 index 00000000000..6f05b791af6 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmnand_mm-2.C @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmnand(vbool1_t op1,vbool1_t op2,size_t vl) +{ + return __riscv_vmnand(op1,op2,31); +} + + +vbool2_t test___riscv_vmnand(vbool2_t op1,vbool2_t op2,size_t vl) +{ + return __riscv_vmnand(op1,op2,31); +} + + +vbool4_t test___riscv_vmnand(vbool4_t op1,vbool4_t op2,size_t vl) +{ + return __riscv_vmnand(op1,op2,31); +} + + +vbool8_t test___riscv_vmnand(vbool8_t op1,vbool8_t op2,size_t vl) +{ + return __riscv_vmnand(op1,op2,31); +} + + +vbool16_t test___riscv_vmnand(vbool16_t op1,vbool16_t op2,size_t vl) +{ + return __riscv_vmnand(op1,op2,31); +} + + +vbool32_t test___riscv_vmnand(vbool32_t op1,vbool32_t op2,size_t vl) +{ + return __riscv_vmnand(op1,op2,31); +} + + +vbool64_t test___riscv_vmnand(vbool64_t op1,vbool64_t op2,size_t vl) +{ + return __riscv_vmnand(op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmnand_mm-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmnand_mm-3.C new file mode 100644 index 00000000000..154bb00e880 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmnand_mm-3.C @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmnand(vbool1_t op1,vbool1_t op2,size_t vl) +{ + return __riscv_vmnand(op1,op2,32); +} + + +vbool2_t test___riscv_vmnand(vbool2_t op1,vbool2_t op2,size_t vl) +{ + return __riscv_vmnand(op1,op2,32); +} + + +vbool4_t test___riscv_vmnand(vbool4_t op1,vbool4_t op2,size_t vl) +{ + return __riscv_vmnand(op1,op2,32); +} + + +vbool8_t test___riscv_vmnand(vbool8_t op1,vbool8_t op2,size_t vl) +{ + return __riscv_vmnand(op1,op2,32); +} + + +vbool16_t test___riscv_vmnand(vbool16_t op1,vbool16_t op2,size_t vl) +{ + return __riscv_vmnand(op1,op2,32); +} + + +vbool32_t test___riscv_vmnand(vbool32_t op1,vbool32_t op2,size_t vl) +{ + return __riscv_vmnand(op1,op2,32); +} + + +vbool64_t test___riscv_vmnand(vbool64_t op1,vbool64_t op2,size_t vl) +{ + return __riscv_vmnand(op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmnand\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmnor_mm-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmnor_mm-1.C new file mode 100644 index 00000000000..0eedebbd59c --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmnor_mm-1.C @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmnor(vbool1_t op1,vbool1_t op2,size_t vl) +{ + return __riscv_vmnor(op1,op2,vl); +} + + +vbool2_t test___riscv_vmnor(vbool2_t op1,vbool2_t op2,size_t vl) +{ + return __riscv_vmnor(op1,op2,vl); +} + + +vbool4_t test___riscv_vmnor(vbool4_t op1,vbool4_t op2,size_t vl) +{ + return __riscv_vmnor(op1,op2,vl); +} + + +vbool8_t test___riscv_vmnor(vbool8_t op1,vbool8_t op2,size_t vl) +{ + return __riscv_vmnor(op1,op2,vl); +} + + +vbool16_t test___riscv_vmnor(vbool16_t op1,vbool16_t op2,size_t vl) +{ + return __riscv_vmnor(op1,op2,vl); +} + + +vbool32_t test___riscv_vmnor(vbool32_t op1,vbool32_t op2,size_t vl) +{ + return __riscv_vmnor(op1,op2,vl); +} + + +vbool64_t test___riscv_vmnor(vbool64_t op1,vbool64_t op2,size_t vl) +{ + return __riscv_vmnor(op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmnor_mm-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmnor_mm-2.C new file mode 100644 index 00000000000..698a6315679 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmnor_mm-2.C @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmnor(vbool1_t op1,vbool1_t op2,size_t vl) +{ + return __riscv_vmnor(op1,op2,31); +} + + +vbool2_t test___riscv_vmnor(vbool2_t op1,vbool2_t op2,size_t vl) +{ + return __riscv_vmnor(op1,op2,31); +} + + +vbool4_t test___riscv_vmnor(vbool4_t op1,vbool4_t op2,size_t vl) +{ + return __riscv_vmnor(op1,op2,31); +} + + +vbool8_t test___riscv_vmnor(vbool8_t op1,vbool8_t op2,size_t vl) +{ + return __riscv_vmnor(op1,op2,31); +} + + +vbool16_t test___riscv_vmnor(vbool16_t op1,vbool16_t op2,size_t vl) +{ + return __riscv_vmnor(op1,op2,31); +} + + +vbool32_t test___riscv_vmnor(vbool32_t op1,vbool32_t op2,size_t vl) +{ + return __riscv_vmnor(op1,op2,31); +} + + +vbool64_t test___riscv_vmnor(vbool64_t op1,vbool64_t op2,size_t vl) +{ + return __riscv_vmnor(op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmnor_mm-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmnor_mm-3.C new file mode 100644 index 00000000000..128020dcdde --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmnor_mm-3.C @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmnor(vbool1_t op1,vbool1_t op2,size_t vl) +{ + return __riscv_vmnor(op1,op2,32); +} + + +vbool2_t test___riscv_vmnor(vbool2_t op1,vbool2_t op2,size_t vl) +{ + return __riscv_vmnor(op1,op2,32); +} + + +vbool4_t test___riscv_vmnor(vbool4_t op1,vbool4_t op2,size_t vl) +{ + return __riscv_vmnor(op1,op2,32); +} + + +vbool8_t test___riscv_vmnor(vbool8_t op1,vbool8_t op2,size_t vl) +{ + return __riscv_vmnor(op1,op2,32); +} + + +vbool16_t test___riscv_vmnor(vbool16_t op1,vbool16_t op2,size_t vl) +{ + return __riscv_vmnor(op1,op2,32); +} + + +vbool32_t test___riscv_vmnor(vbool32_t op1,vbool32_t op2,size_t vl) +{ + return __riscv_vmnor(op1,op2,32); +} + + +vbool64_t test___riscv_vmnor(vbool64_t op1,vbool64_t op2,size_t vl) +{ + return __riscv_vmnor(op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmnot_mm-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmnot_mm-1.C new file mode 100644 index 00000000000..46380f1f124 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmnot_mm-1.C @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmnot(vbool1_t op1,size_t vl) +{ + return __riscv_vmnot(op1,vl); +} + + +vbool2_t test___riscv_vmnot(vbool2_t op1,size_t vl) +{ + return __riscv_vmnot(op1,vl); +} + + +vbool4_t test___riscv_vmnot(vbool4_t op1,size_t vl) +{ + return __riscv_vmnot(op1,vl); +} + + +vbool8_t test___riscv_vmnot(vbool8_t op1,size_t vl) +{ + return __riscv_vmnot(op1,vl); +} + + +vbool16_t test___riscv_vmnot(vbool16_t op1,size_t vl) +{ + return __riscv_vmnot(op1,vl); +} + + +vbool32_t test___riscv_vmnot(vbool32_t op1,size_t vl) +{ + return __riscv_vmnot(op1,vl); +} + + +vbool64_t test___riscv_vmnot(vbool64_t op1,size_t vl) +{ + return __riscv_vmnot(op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmnot_mm-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmnot_mm-2.C new file mode 100644 index 00000000000..6d3d1855d30 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmnot_mm-2.C @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmnot(vbool1_t op1,size_t vl) +{ + return __riscv_vmnot(op1,31); +} + + +vbool2_t test___riscv_vmnot(vbool2_t op1,size_t vl) +{ + return __riscv_vmnot(op1,31); +} + + +vbool4_t test___riscv_vmnot(vbool4_t op1,size_t vl) +{ + return __riscv_vmnot(op1,31); +} + + +vbool8_t test___riscv_vmnot(vbool8_t op1,size_t vl) +{ + return __riscv_vmnot(op1,31); +} + + +vbool16_t test___riscv_vmnot(vbool16_t op1,size_t vl) +{ + return __riscv_vmnot(op1,31); +} + + +vbool32_t test___riscv_vmnot(vbool32_t op1,size_t vl) +{ + return __riscv_vmnot(op1,31); +} + + +vbool64_t test___riscv_vmnot(vbool64_t op1,size_t vl) +{ + return __riscv_vmnot(op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmnot_mm-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmnot_mm-3.C new file mode 100644 index 00000000000..f9377cf7fab --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmnot_mm-3.C @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmnot(vbool1_t op1,size_t vl) +{ + return __riscv_vmnot(op1,32); +} + + +vbool2_t test___riscv_vmnot(vbool2_t op1,size_t vl) +{ + return __riscv_vmnot(op1,32); +} + + +vbool4_t test___riscv_vmnot(vbool4_t op1,size_t vl) +{ + return __riscv_vmnot(op1,32); +} + + +vbool8_t test___riscv_vmnot(vbool8_t op1,size_t vl) +{ + return __riscv_vmnot(op1,32); +} + + +vbool16_t test___riscv_vmnot(vbool16_t op1,size_t vl) +{ + return __riscv_vmnot(op1,32); +} + + +vbool32_t test___riscv_vmnot(vbool32_t op1,size_t vl) +{ + return __riscv_vmnot(op1,32); +} + + +vbool64_t test___riscv_vmnot(vbool64_t op1,size_t vl) +{ + return __riscv_vmnot(op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmnot\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmor_mm-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmor_mm-1.C new file mode 100644 index 00000000000..a8294a10abb --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmor_mm-1.C @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmor(vbool1_t op1,vbool1_t op2,size_t vl) +{ + return __riscv_vmor(op1,op2,vl); +} + + +vbool2_t test___riscv_vmor(vbool2_t op1,vbool2_t op2,size_t vl) +{ + return __riscv_vmor(op1,op2,vl); +} + + +vbool4_t test___riscv_vmor(vbool4_t op1,vbool4_t op2,size_t vl) +{ + return __riscv_vmor(op1,op2,vl); +} + + +vbool8_t test___riscv_vmor(vbool8_t op1,vbool8_t op2,size_t vl) +{ + return __riscv_vmor(op1,op2,vl); +} + + +vbool16_t test___riscv_vmor(vbool16_t op1,vbool16_t op2,size_t vl) +{ + return __riscv_vmor(op1,op2,vl); +} + + +vbool32_t test___riscv_vmor(vbool32_t op1,vbool32_t op2,size_t vl) +{ + return __riscv_vmor(op1,op2,vl); +} + + +vbool64_t test___riscv_vmor(vbool64_t op1,vbool64_t op2,size_t vl) +{ + return __riscv_vmor(op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmor_mm-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmor_mm-2.C new file mode 100644 index 00000000000..9aee127ea00 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmor_mm-2.C @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmor(vbool1_t op1,vbool1_t op2,size_t vl) +{ + return __riscv_vmor(op1,op2,31); +} + + +vbool2_t test___riscv_vmor(vbool2_t op1,vbool2_t op2,size_t vl) +{ + return __riscv_vmor(op1,op2,31); +} + + +vbool4_t test___riscv_vmor(vbool4_t op1,vbool4_t op2,size_t vl) +{ + return __riscv_vmor(op1,op2,31); +} + + +vbool8_t test___riscv_vmor(vbool8_t op1,vbool8_t op2,size_t vl) +{ + return __riscv_vmor(op1,op2,31); +} + + +vbool16_t test___riscv_vmor(vbool16_t op1,vbool16_t op2,size_t vl) +{ + return __riscv_vmor(op1,op2,31); +} + + +vbool32_t test___riscv_vmor(vbool32_t op1,vbool32_t op2,size_t vl) +{ + return __riscv_vmor(op1,op2,31); +} + + +vbool64_t test___riscv_vmor(vbool64_t op1,vbool64_t op2,size_t vl) +{ + return __riscv_vmor(op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmor_mm-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmor_mm-3.C new file mode 100644 index 00000000000..f04e175e98a --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmor_mm-3.C @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmor(vbool1_t op1,vbool1_t op2,size_t vl) +{ + return __riscv_vmor(op1,op2,32); +} + + +vbool2_t test___riscv_vmor(vbool2_t op1,vbool2_t op2,size_t vl) +{ + return __riscv_vmor(op1,op2,32); +} + + +vbool4_t test___riscv_vmor(vbool4_t op1,vbool4_t op2,size_t vl) +{ + return __riscv_vmor(op1,op2,32); +} + + +vbool8_t test___riscv_vmor(vbool8_t op1,vbool8_t op2,size_t vl) +{ + return __riscv_vmor(op1,op2,32); +} + + +vbool16_t test___riscv_vmor(vbool16_t op1,vbool16_t op2,size_t vl) +{ + return __riscv_vmor(op1,op2,32); +} + + +vbool32_t test___riscv_vmor(vbool32_t op1,vbool32_t op2,size_t vl) +{ + return __riscv_vmor(op1,op2,32); +} + + +vbool64_t test___riscv_vmor(vbool64_t op1,vbool64_t op2,size_t vl) +{ + return __riscv_vmor(op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmorn_mm-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmorn_mm-1.C new file mode 100644 index 00000000000..e43b6e9d67c --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmorn_mm-1.C @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmorn(vbool1_t op1,vbool1_t op2,size_t vl) +{ + return __riscv_vmorn(op1,op2,vl); +} + + +vbool2_t test___riscv_vmorn(vbool2_t op1,vbool2_t op2,size_t vl) +{ + return __riscv_vmorn(op1,op2,vl); +} + + +vbool4_t test___riscv_vmorn(vbool4_t op1,vbool4_t op2,size_t vl) +{ + return __riscv_vmorn(op1,op2,vl); +} + + +vbool8_t test___riscv_vmorn(vbool8_t op1,vbool8_t op2,size_t vl) +{ + return __riscv_vmorn(op1,op2,vl); +} + + +vbool16_t test___riscv_vmorn(vbool16_t op1,vbool16_t op2,size_t vl) +{ + return __riscv_vmorn(op1,op2,vl); +} + + +vbool32_t test___riscv_vmorn(vbool32_t op1,vbool32_t op2,size_t vl) +{ + return __riscv_vmorn(op1,op2,vl); +} + + +vbool64_t test___riscv_vmorn(vbool64_t op1,vbool64_t op2,size_t vl) +{ + return __riscv_vmorn(op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmorn_mm-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmorn_mm-2.C new file mode 100644 index 00000000000..04d38d368da --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmorn_mm-2.C @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmorn(vbool1_t op1,vbool1_t op2,size_t vl) +{ + return __riscv_vmorn(op1,op2,31); +} + + +vbool2_t test___riscv_vmorn(vbool2_t op1,vbool2_t op2,size_t vl) +{ + return __riscv_vmorn(op1,op2,31); +} + + +vbool4_t test___riscv_vmorn(vbool4_t op1,vbool4_t op2,size_t vl) +{ + return __riscv_vmorn(op1,op2,31); +} + + +vbool8_t test___riscv_vmorn(vbool8_t op1,vbool8_t op2,size_t vl) +{ + return __riscv_vmorn(op1,op2,31); +} + + +vbool16_t test___riscv_vmorn(vbool16_t op1,vbool16_t op2,size_t vl) +{ + return __riscv_vmorn(op1,op2,31); +} + + +vbool32_t test___riscv_vmorn(vbool32_t op1,vbool32_t op2,size_t vl) +{ + return __riscv_vmorn(op1,op2,31); +} + + +vbool64_t test___riscv_vmorn(vbool64_t op1,vbool64_t op2,size_t vl) +{ + return __riscv_vmorn(op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmorn_mm-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmorn_mm-3.C new file mode 100644 index 00000000000..ea4c2a4e757 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmorn_mm-3.C @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmorn(vbool1_t op1,vbool1_t op2,size_t vl) +{ + return __riscv_vmorn(op1,op2,32); +} + + +vbool2_t test___riscv_vmorn(vbool2_t op1,vbool2_t op2,size_t vl) +{ + return __riscv_vmorn(op1,op2,32); +} + + +vbool4_t test___riscv_vmorn(vbool4_t op1,vbool4_t op2,size_t vl) +{ + return __riscv_vmorn(op1,op2,32); +} + + +vbool8_t test___riscv_vmorn(vbool8_t op1,vbool8_t op2,size_t vl) +{ + return __riscv_vmorn(op1,op2,32); +} + + +vbool16_t test___riscv_vmorn(vbool16_t op1,vbool16_t op2,size_t vl) +{ + return __riscv_vmorn(op1,op2,32); +} + + +vbool32_t test___riscv_vmorn(vbool32_t op1,vbool32_t op2,size_t vl) +{ + return __riscv_vmorn(op1,op2,32); +} + + +vbool64_t test___riscv_vmorn(vbool64_t op1,vbool64_t op2,size_t vl) +{ + return __riscv_vmorn(op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmorn\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsbf_m-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmsbf_m-1.C new file mode 100644 index 00000000000..aa2a26c7bba --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsbf_m-1.C @@ -0,0 +1,104 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmsbf(vbool1_t op1,size_t vl) +{ + return __riscv_vmsbf(op1,vl); +} + + +vbool2_t test___riscv_vmsbf(vbool2_t op1,size_t vl) +{ + return __riscv_vmsbf(op1,vl); +} + + +vbool4_t test___riscv_vmsbf(vbool4_t op1,size_t vl) +{ + return __riscv_vmsbf(op1,vl); +} + + +vbool8_t test___riscv_vmsbf(vbool8_t op1,size_t vl) +{ + return __riscv_vmsbf(op1,vl); +} + + +vbool16_t test___riscv_vmsbf(vbool16_t op1,size_t vl) +{ + return __riscv_vmsbf(op1,vl); +} + + +vbool32_t test___riscv_vmsbf(vbool32_t op1,size_t vl) +{ + return __riscv_vmsbf(op1,vl); +} + + +vbool64_t test___riscv_vmsbf(vbool64_t op1,size_t vl) +{ + return __riscv_vmsbf(op1,vl); +} + + +vbool1_t test___riscv_vmsbf(vbool1_t mask,vbool1_t op1,size_t vl) +{ + return __riscv_vmsbf(mask,op1,vl); +} + + +vbool2_t test___riscv_vmsbf(vbool2_t mask,vbool2_t op1,size_t vl) +{ + return __riscv_vmsbf(mask,op1,vl); +} + + +vbool4_t test___riscv_vmsbf(vbool4_t mask,vbool4_t op1,size_t vl) +{ + return __riscv_vmsbf(mask,op1,vl); +} + + +vbool8_t test___riscv_vmsbf(vbool8_t mask,vbool8_t op1,size_t vl) +{ + return __riscv_vmsbf(mask,op1,vl); +} + + +vbool16_t test___riscv_vmsbf(vbool16_t mask,vbool16_t op1,size_t vl) +{ + return __riscv_vmsbf(mask,op1,vl); +} + + +vbool32_t test___riscv_vmsbf(vbool32_t mask,vbool32_t op1,size_t vl) +{ + return __riscv_vmsbf(mask,op1,vl); +} + + +vbool64_t test___riscv_vmsbf(vbool64_t mask,vbool64_t op1,size_t vl) +{ + return __riscv_vmsbf(mask,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsbf_m-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmsbf_m-2.C new file mode 100644 index 00000000000..fcfb70b0749 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsbf_m-2.C @@ -0,0 +1,104 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmsbf(vbool1_t op1,size_t vl) +{ + return __riscv_vmsbf(op1,31); +} + + +vbool2_t test___riscv_vmsbf(vbool2_t op1,size_t vl) +{ + return __riscv_vmsbf(op1,31); +} + + +vbool4_t test___riscv_vmsbf(vbool4_t op1,size_t vl) +{ + return __riscv_vmsbf(op1,31); +} + + +vbool8_t test___riscv_vmsbf(vbool8_t op1,size_t vl) +{ + return __riscv_vmsbf(op1,31); +} + + +vbool16_t test___riscv_vmsbf(vbool16_t op1,size_t vl) +{ + return __riscv_vmsbf(op1,31); +} + + +vbool32_t test___riscv_vmsbf(vbool32_t op1,size_t vl) +{ + return __riscv_vmsbf(op1,31); +} + + +vbool64_t test___riscv_vmsbf(vbool64_t op1,size_t vl) +{ + return __riscv_vmsbf(op1,31); +} + + +vbool1_t test___riscv_vmsbf(vbool1_t mask,vbool1_t op1,size_t vl) +{ + return __riscv_vmsbf(mask,op1,31); +} + + +vbool2_t test___riscv_vmsbf(vbool2_t mask,vbool2_t op1,size_t vl) +{ + return __riscv_vmsbf(mask,op1,31); +} + + +vbool4_t test___riscv_vmsbf(vbool4_t mask,vbool4_t op1,size_t vl) +{ + return __riscv_vmsbf(mask,op1,31); +} + + +vbool8_t test___riscv_vmsbf(vbool8_t mask,vbool8_t op1,size_t vl) +{ + return __riscv_vmsbf(mask,op1,31); +} + + +vbool16_t test___riscv_vmsbf(vbool16_t mask,vbool16_t op1,size_t vl) +{ + return __riscv_vmsbf(mask,op1,31); +} + + +vbool32_t test___riscv_vmsbf(vbool32_t mask,vbool32_t op1,size_t vl) +{ + return __riscv_vmsbf(mask,op1,31); +} + + +vbool64_t test___riscv_vmsbf(vbool64_t mask,vbool64_t op1,size_t vl) +{ + return __riscv_vmsbf(mask,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsbf_m-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmsbf_m-3.C new file mode 100644 index 00000000000..4853adba0ef --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsbf_m-3.C @@ -0,0 +1,104 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmsbf(vbool1_t op1,size_t vl) +{ + return __riscv_vmsbf(op1,32); +} + + +vbool2_t test___riscv_vmsbf(vbool2_t op1,size_t vl) +{ + return __riscv_vmsbf(op1,32); +} + + +vbool4_t test___riscv_vmsbf(vbool4_t op1,size_t vl) +{ + return __riscv_vmsbf(op1,32); +} + + +vbool8_t test___riscv_vmsbf(vbool8_t op1,size_t vl) +{ + return __riscv_vmsbf(op1,32); +} + + +vbool16_t test___riscv_vmsbf(vbool16_t op1,size_t vl) +{ + return __riscv_vmsbf(op1,32); +} + + +vbool32_t test___riscv_vmsbf(vbool32_t op1,size_t vl) +{ + return __riscv_vmsbf(op1,32); +} + + +vbool64_t test___riscv_vmsbf(vbool64_t op1,size_t vl) +{ + return __riscv_vmsbf(op1,32); +} + + +vbool1_t test___riscv_vmsbf(vbool1_t mask,vbool1_t op1,size_t vl) +{ + return __riscv_vmsbf(mask,op1,32); +} + + +vbool2_t test___riscv_vmsbf(vbool2_t mask,vbool2_t op1,size_t vl) +{ + return __riscv_vmsbf(mask,op1,32); +} + + +vbool4_t test___riscv_vmsbf(vbool4_t mask,vbool4_t op1,size_t vl) +{ + return __riscv_vmsbf(mask,op1,32); +} + + +vbool8_t test___riscv_vmsbf(vbool8_t mask,vbool8_t op1,size_t vl) +{ + return __riscv_vmsbf(mask,op1,32); +} + + +vbool16_t test___riscv_vmsbf(vbool16_t mask,vbool16_t op1,size_t vl) +{ + return __riscv_vmsbf(mask,op1,32); +} + + +vbool32_t test___riscv_vmsbf(vbool32_t mask,vbool32_t op1,size_t vl) +{ + return __riscv_vmsbf(mask,op1,32); +} + + +vbool64_t test___riscv_vmsbf(vbool64_t mask,vbool64_t op1,size_t vl) +{ + return __riscv_vmsbf(mask,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsbf_m_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmsbf_m_mu-1.C new file mode 100644 index 00000000000..91afabb8d90 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsbf_m_mu-1.C @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmsbf_mu(vbool1_t mask,vbool1_t maskedoff,vbool1_t op1,size_t vl) +{ + return __riscv_vmsbf_mu(mask,maskedoff,op1,vl); +} + + +vbool2_t test___riscv_vmsbf_mu(vbool2_t mask,vbool2_t maskedoff,vbool2_t op1,size_t vl) +{ + return __riscv_vmsbf_mu(mask,maskedoff,op1,vl); +} + + +vbool4_t test___riscv_vmsbf_mu(vbool4_t mask,vbool4_t maskedoff,vbool4_t op1,size_t vl) +{ + return __riscv_vmsbf_mu(mask,maskedoff,op1,vl); +} + + +vbool8_t test___riscv_vmsbf_mu(vbool8_t mask,vbool8_t maskedoff,vbool8_t op1,size_t vl) +{ + return __riscv_vmsbf_mu(mask,maskedoff,op1,vl); +} + + +vbool16_t test___riscv_vmsbf_mu(vbool16_t mask,vbool16_t maskedoff,vbool16_t op1,size_t vl) +{ + return __riscv_vmsbf_mu(mask,maskedoff,op1,vl); +} + + +vbool32_t test___riscv_vmsbf_mu(vbool32_t mask,vbool32_t maskedoff,vbool32_t op1,size_t vl) +{ + return __riscv_vmsbf_mu(mask,maskedoff,op1,vl); +} + + +vbool64_t test___riscv_vmsbf_mu(vbool64_t mask,vbool64_t maskedoff,vbool64_t op1,size_t vl) +{ + return __riscv_vmsbf_mu(mask,maskedoff,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsbf_m_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmsbf_m_mu-2.C new file mode 100644 index 00000000000..f2dff4de9b0 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsbf_m_mu-2.C @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmsbf_mu(vbool1_t mask,vbool1_t maskedoff,vbool1_t op1,size_t vl) +{ + return __riscv_vmsbf_mu(mask,maskedoff,op1,31); +} + + +vbool2_t test___riscv_vmsbf_mu(vbool2_t mask,vbool2_t maskedoff,vbool2_t op1,size_t vl) +{ + return __riscv_vmsbf_mu(mask,maskedoff,op1,31); +} + + +vbool4_t test___riscv_vmsbf_mu(vbool4_t mask,vbool4_t maskedoff,vbool4_t op1,size_t vl) +{ + return __riscv_vmsbf_mu(mask,maskedoff,op1,31); +} + + +vbool8_t test___riscv_vmsbf_mu(vbool8_t mask,vbool8_t maskedoff,vbool8_t op1,size_t vl) +{ + return __riscv_vmsbf_mu(mask,maskedoff,op1,31); +} + + +vbool16_t test___riscv_vmsbf_mu(vbool16_t mask,vbool16_t maskedoff,vbool16_t op1,size_t vl) +{ + return __riscv_vmsbf_mu(mask,maskedoff,op1,31); +} + + +vbool32_t test___riscv_vmsbf_mu(vbool32_t mask,vbool32_t maskedoff,vbool32_t op1,size_t vl) +{ + return __riscv_vmsbf_mu(mask,maskedoff,op1,31); +} + + +vbool64_t test___riscv_vmsbf_mu(vbool64_t mask,vbool64_t maskedoff,vbool64_t op1,size_t vl) +{ + return __riscv_vmsbf_mu(mask,maskedoff,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsbf_m_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmsbf_m_mu-3.C new file mode 100644 index 00000000000..de2b1879202 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsbf_m_mu-3.C @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmsbf_mu(vbool1_t mask,vbool1_t maskedoff,vbool1_t op1,size_t vl) +{ + return __riscv_vmsbf_mu(mask,maskedoff,op1,32); +} + + +vbool2_t test___riscv_vmsbf_mu(vbool2_t mask,vbool2_t maskedoff,vbool2_t op1,size_t vl) +{ + return __riscv_vmsbf_mu(mask,maskedoff,op1,32); +} + + +vbool4_t test___riscv_vmsbf_mu(vbool4_t mask,vbool4_t maskedoff,vbool4_t op1,size_t vl) +{ + return __riscv_vmsbf_mu(mask,maskedoff,op1,32); +} + + +vbool8_t test___riscv_vmsbf_mu(vbool8_t mask,vbool8_t maskedoff,vbool8_t op1,size_t vl) +{ + return __riscv_vmsbf_mu(mask,maskedoff,op1,32); +} + + +vbool16_t test___riscv_vmsbf_mu(vbool16_t mask,vbool16_t maskedoff,vbool16_t op1,size_t vl) +{ + return __riscv_vmsbf_mu(mask,maskedoff,op1,32); +} + + +vbool32_t test___riscv_vmsbf_mu(vbool32_t mask,vbool32_t maskedoff,vbool32_t op1,size_t vl) +{ + return __riscv_vmsbf_mu(mask,maskedoff,op1,32); +} + + +vbool64_t test___riscv_vmsbf_mu(vbool64_t mask,vbool64_t maskedoff,vbool64_t op1,size_t vl) +{ + return __riscv_vmsbf_mu(mask,maskedoff,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsbf\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmset_m_m-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmset_m_m-1.C new file mode 100644 index 00000000000..d97faaa5fdd --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmset_m_m-1.C @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmset_m_b1(size_t vl) +{ + return __riscv_vmset_m_b1(vl); +} + + +vbool2_t test___riscv_vmset_m_b2(size_t vl) +{ + return __riscv_vmset_m_b2(vl); +} + + +vbool4_t test___riscv_vmset_m_b4(size_t vl) +{ + return __riscv_vmset_m_b4(vl); +} + + +vbool8_t test___riscv_vmset_m_b8(size_t vl) +{ + return __riscv_vmset_m_b8(vl); +} + + +vbool16_t test___riscv_vmset_m_b16(size_t vl) +{ + return __riscv_vmset_m_b16(vl); +} + + +vbool32_t test___riscv_vmset_m_b32(size_t vl) +{ + return __riscv_vmset_m_b32(vl); +} + + +vbool64_t test___riscv_vmset_m_b64(size_t vl) +{ + return __riscv_vmset_m_b64(vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmset_m_m-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmset_m_m-2.C new file mode 100644 index 00000000000..494d1862d7f --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmset_m_m-2.C @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmset_m_b1(size_t vl) +{ + return __riscv_vmset_m_b1(31); +} + + +vbool2_t test___riscv_vmset_m_b2(size_t vl) +{ + return __riscv_vmset_m_b2(31); +} + + +vbool4_t test___riscv_vmset_m_b4(size_t vl) +{ + return __riscv_vmset_m_b4(31); +} + + +vbool8_t test___riscv_vmset_m_b8(size_t vl) +{ + return __riscv_vmset_m_b8(31); +} + + +vbool16_t test___riscv_vmset_m_b16(size_t vl) +{ + return __riscv_vmset_m_b16(31); +} + + +vbool32_t test___riscv_vmset_m_b32(size_t vl) +{ + return __riscv_vmset_m_b32(31); +} + + +vbool64_t test___riscv_vmset_m_b64(size_t vl) +{ + return __riscv_vmset_m_b64(31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmset_m_m-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmset_m_m-3.C new file mode 100644 index 00000000000..86756eaa2b9 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmset_m_m-3.C @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmset_m_b1(size_t vl) +{ + return __riscv_vmset_m_b1(32); +} + + +vbool2_t test___riscv_vmset_m_b2(size_t vl) +{ + return __riscv_vmset_m_b2(32); +} + + +vbool4_t test___riscv_vmset_m_b4(size_t vl) +{ + return __riscv_vmset_m_b4(32); +} + + +vbool8_t test___riscv_vmset_m_b8(size_t vl) +{ + return __riscv_vmset_m_b8(32); +} + + +vbool16_t test___riscv_vmset_m_b16(size_t vl) +{ + return __riscv_vmset_m_b16(32); +} + + +vbool32_t test___riscv_vmset_m_b32(size_t vl) +{ + return __riscv_vmset_m_b32(32); +} + + +vbool64_t test___riscv_vmset_m_b64(size_t vl) +{ + return __riscv_vmset_m_b64(32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmset\.m\s+v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsif_m-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmsif_m-1.C new file mode 100644 index 00000000000..08001c1b38a --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsif_m-1.C @@ -0,0 +1,104 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmsif(vbool1_t op1,size_t vl) +{ + return __riscv_vmsif(op1,vl); +} + + +vbool2_t test___riscv_vmsif(vbool2_t op1,size_t vl) +{ + return __riscv_vmsif(op1,vl); +} + + +vbool4_t test___riscv_vmsif(vbool4_t op1,size_t vl) +{ + return __riscv_vmsif(op1,vl); +} + + +vbool8_t test___riscv_vmsif(vbool8_t op1,size_t vl) +{ + return __riscv_vmsif(op1,vl); +} + + +vbool16_t test___riscv_vmsif(vbool16_t op1,size_t vl) +{ + return __riscv_vmsif(op1,vl); +} + + +vbool32_t test___riscv_vmsif(vbool32_t op1,size_t vl) +{ + return __riscv_vmsif(op1,vl); +} + + +vbool64_t test___riscv_vmsif(vbool64_t op1,size_t vl) +{ + return __riscv_vmsif(op1,vl); +} + + +vbool1_t test___riscv_vmsif(vbool1_t mask,vbool1_t op1,size_t vl) +{ + return __riscv_vmsif(mask,op1,vl); +} + + +vbool2_t test___riscv_vmsif(vbool2_t mask,vbool2_t op1,size_t vl) +{ + return __riscv_vmsif(mask,op1,vl); +} + + +vbool4_t test___riscv_vmsif(vbool4_t mask,vbool4_t op1,size_t vl) +{ + return __riscv_vmsif(mask,op1,vl); +} + + +vbool8_t test___riscv_vmsif(vbool8_t mask,vbool8_t op1,size_t vl) +{ + return __riscv_vmsif(mask,op1,vl); +} + + +vbool16_t test___riscv_vmsif(vbool16_t mask,vbool16_t op1,size_t vl) +{ + return __riscv_vmsif(mask,op1,vl); +} + + +vbool32_t test___riscv_vmsif(vbool32_t mask,vbool32_t op1,size_t vl) +{ + return __riscv_vmsif(mask,op1,vl); +} + + +vbool64_t test___riscv_vmsif(vbool64_t mask,vbool64_t op1,size_t vl) +{ + return __riscv_vmsif(mask,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsif_m-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmsif_m-2.C new file mode 100644 index 00000000000..b50d877bb11 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsif_m-2.C @@ -0,0 +1,104 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmsif(vbool1_t op1,size_t vl) +{ + return __riscv_vmsif(op1,31); +} + + +vbool2_t test___riscv_vmsif(vbool2_t op1,size_t vl) +{ + return __riscv_vmsif(op1,31); +} + + +vbool4_t test___riscv_vmsif(vbool4_t op1,size_t vl) +{ + return __riscv_vmsif(op1,31); +} + + +vbool8_t test___riscv_vmsif(vbool8_t op1,size_t vl) +{ + return __riscv_vmsif(op1,31); +} + + +vbool16_t test___riscv_vmsif(vbool16_t op1,size_t vl) +{ + return __riscv_vmsif(op1,31); +} + + +vbool32_t test___riscv_vmsif(vbool32_t op1,size_t vl) +{ + return __riscv_vmsif(op1,31); +} + + +vbool64_t test___riscv_vmsif(vbool64_t op1,size_t vl) +{ + return __riscv_vmsif(op1,31); +} + + +vbool1_t test___riscv_vmsif(vbool1_t mask,vbool1_t op1,size_t vl) +{ + return __riscv_vmsif(mask,op1,31); +} + + +vbool2_t test___riscv_vmsif(vbool2_t mask,vbool2_t op1,size_t vl) +{ + return __riscv_vmsif(mask,op1,31); +} + + +vbool4_t test___riscv_vmsif(vbool4_t mask,vbool4_t op1,size_t vl) +{ + return __riscv_vmsif(mask,op1,31); +} + + +vbool8_t test___riscv_vmsif(vbool8_t mask,vbool8_t op1,size_t vl) +{ + return __riscv_vmsif(mask,op1,31); +} + + +vbool16_t test___riscv_vmsif(vbool16_t mask,vbool16_t op1,size_t vl) +{ + return __riscv_vmsif(mask,op1,31); +} + + +vbool32_t test___riscv_vmsif(vbool32_t mask,vbool32_t op1,size_t vl) +{ + return __riscv_vmsif(mask,op1,31); +} + + +vbool64_t test___riscv_vmsif(vbool64_t mask,vbool64_t op1,size_t vl) +{ + return __riscv_vmsif(mask,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsif_m-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmsif_m-3.C new file mode 100644 index 00000000000..6cdbb8bf20a --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsif_m-3.C @@ -0,0 +1,104 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmsif(vbool1_t op1,size_t vl) +{ + return __riscv_vmsif(op1,32); +} + + +vbool2_t test___riscv_vmsif(vbool2_t op1,size_t vl) +{ + return __riscv_vmsif(op1,32); +} + + +vbool4_t test___riscv_vmsif(vbool4_t op1,size_t vl) +{ + return __riscv_vmsif(op1,32); +} + + +vbool8_t test___riscv_vmsif(vbool8_t op1,size_t vl) +{ + return __riscv_vmsif(op1,32); +} + + +vbool16_t test___riscv_vmsif(vbool16_t op1,size_t vl) +{ + return __riscv_vmsif(op1,32); +} + + +vbool32_t test___riscv_vmsif(vbool32_t op1,size_t vl) +{ + return __riscv_vmsif(op1,32); +} + + +vbool64_t test___riscv_vmsif(vbool64_t op1,size_t vl) +{ + return __riscv_vmsif(op1,32); +} + + +vbool1_t test___riscv_vmsif(vbool1_t mask,vbool1_t op1,size_t vl) +{ + return __riscv_vmsif(mask,op1,32); +} + + +vbool2_t test___riscv_vmsif(vbool2_t mask,vbool2_t op1,size_t vl) +{ + return __riscv_vmsif(mask,op1,32); +} + + +vbool4_t test___riscv_vmsif(vbool4_t mask,vbool4_t op1,size_t vl) +{ + return __riscv_vmsif(mask,op1,32); +} + + +vbool8_t test___riscv_vmsif(vbool8_t mask,vbool8_t op1,size_t vl) +{ + return __riscv_vmsif(mask,op1,32); +} + + +vbool16_t test___riscv_vmsif(vbool16_t mask,vbool16_t op1,size_t vl) +{ + return __riscv_vmsif(mask,op1,32); +} + + +vbool32_t test___riscv_vmsif(vbool32_t mask,vbool32_t op1,size_t vl) +{ + return __riscv_vmsif(mask,op1,32); +} + + +vbool64_t test___riscv_vmsif(vbool64_t mask,vbool64_t op1,size_t vl) +{ + return __riscv_vmsif(mask,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsif_m_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmsif_m_mu-1.C new file mode 100644 index 00000000000..d6b2949b65e --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsif_m_mu-1.C @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmsif_mu(vbool1_t mask,vbool1_t maskedoff,vbool1_t op1,size_t vl) +{ + return __riscv_vmsif_mu(mask,maskedoff,op1,vl); +} + + +vbool2_t test___riscv_vmsif_mu(vbool2_t mask,vbool2_t maskedoff,vbool2_t op1,size_t vl) +{ + return __riscv_vmsif_mu(mask,maskedoff,op1,vl); +} + + +vbool4_t test___riscv_vmsif_mu(vbool4_t mask,vbool4_t maskedoff,vbool4_t op1,size_t vl) +{ + return __riscv_vmsif_mu(mask,maskedoff,op1,vl); +} + + +vbool8_t test___riscv_vmsif_mu(vbool8_t mask,vbool8_t maskedoff,vbool8_t op1,size_t vl) +{ + return __riscv_vmsif_mu(mask,maskedoff,op1,vl); +} + + +vbool16_t test___riscv_vmsif_mu(vbool16_t mask,vbool16_t maskedoff,vbool16_t op1,size_t vl) +{ + return __riscv_vmsif_mu(mask,maskedoff,op1,vl); +} + + +vbool32_t test___riscv_vmsif_mu(vbool32_t mask,vbool32_t maskedoff,vbool32_t op1,size_t vl) +{ + return __riscv_vmsif_mu(mask,maskedoff,op1,vl); +} + + +vbool64_t test___riscv_vmsif_mu(vbool64_t mask,vbool64_t maskedoff,vbool64_t op1,size_t vl) +{ + return __riscv_vmsif_mu(mask,maskedoff,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsif_m_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmsif_m_mu-2.C new file mode 100644 index 00000000000..2a7c313afcf --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsif_m_mu-2.C @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmsif_mu(vbool1_t mask,vbool1_t maskedoff,vbool1_t op1,size_t vl) +{ + return __riscv_vmsif_mu(mask,maskedoff,op1,31); +} + + +vbool2_t test___riscv_vmsif_mu(vbool2_t mask,vbool2_t maskedoff,vbool2_t op1,size_t vl) +{ + return __riscv_vmsif_mu(mask,maskedoff,op1,31); +} + + +vbool4_t test___riscv_vmsif_mu(vbool4_t mask,vbool4_t maskedoff,vbool4_t op1,size_t vl) +{ + return __riscv_vmsif_mu(mask,maskedoff,op1,31); +} + + +vbool8_t test___riscv_vmsif_mu(vbool8_t mask,vbool8_t maskedoff,vbool8_t op1,size_t vl) +{ + return __riscv_vmsif_mu(mask,maskedoff,op1,31); +} + + +vbool16_t test___riscv_vmsif_mu(vbool16_t mask,vbool16_t maskedoff,vbool16_t op1,size_t vl) +{ + return __riscv_vmsif_mu(mask,maskedoff,op1,31); +} + + +vbool32_t test___riscv_vmsif_mu(vbool32_t mask,vbool32_t maskedoff,vbool32_t op1,size_t vl) +{ + return __riscv_vmsif_mu(mask,maskedoff,op1,31); +} + + +vbool64_t test___riscv_vmsif_mu(vbool64_t mask,vbool64_t maskedoff,vbool64_t op1,size_t vl) +{ + return __riscv_vmsif_mu(mask,maskedoff,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsif_m_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmsif_m_mu-3.C new file mode 100644 index 00000000000..5ede0fc00d4 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsif_m_mu-3.C @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmsif_mu(vbool1_t mask,vbool1_t maskedoff,vbool1_t op1,size_t vl) +{ + return __riscv_vmsif_mu(mask,maskedoff,op1,32); +} + + +vbool2_t test___riscv_vmsif_mu(vbool2_t mask,vbool2_t maskedoff,vbool2_t op1,size_t vl) +{ + return __riscv_vmsif_mu(mask,maskedoff,op1,32); +} + + +vbool4_t test___riscv_vmsif_mu(vbool4_t mask,vbool4_t maskedoff,vbool4_t op1,size_t vl) +{ + return __riscv_vmsif_mu(mask,maskedoff,op1,32); +} + + +vbool8_t test___riscv_vmsif_mu(vbool8_t mask,vbool8_t maskedoff,vbool8_t op1,size_t vl) +{ + return __riscv_vmsif_mu(mask,maskedoff,op1,32); +} + + +vbool16_t test___riscv_vmsif_mu(vbool16_t mask,vbool16_t maskedoff,vbool16_t op1,size_t vl) +{ + return __riscv_vmsif_mu(mask,maskedoff,op1,32); +} + + +vbool32_t test___riscv_vmsif_mu(vbool32_t mask,vbool32_t maskedoff,vbool32_t op1,size_t vl) +{ + return __riscv_vmsif_mu(mask,maskedoff,op1,32); +} + + +vbool64_t test___riscv_vmsif_mu(vbool64_t mask,vbool64_t maskedoff,vbool64_t op1,size_t vl) +{ + return __riscv_vmsif_mu(mask,maskedoff,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsif\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsof_m-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmsof_m-1.C new file mode 100644 index 00000000000..1e5ce4c116e --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsof_m-1.C @@ -0,0 +1,104 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmsof(vbool1_t op1,size_t vl) +{ + return __riscv_vmsof(op1,vl); +} + + +vbool2_t test___riscv_vmsof(vbool2_t op1,size_t vl) +{ + return __riscv_vmsof(op1,vl); +} + + +vbool4_t test___riscv_vmsof(vbool4_t op1,size_t vl) +{ + return __riscv_vmsof(op1,vl); +} + + +vbool8_t test___riscv_vmsof(vbool8_t op1,size_t vl) +{ + return __riscv_vmsof(op1,vl); +} + + +vbool16_t test___riscv_vmsof(vbool16_t op1,size_t vl) +{ + return __riscv_vmsof(op1,vl); +} + + +vbool32_t test___riscv_vmsof(vbool32_t op1,size_t vl) +{ + return __riscv_vmsof(op1,vl); +} + + +vbool64_t test___riscv_vmsof(vbool64_t op1,size_t vl) +{ + return __riscv_vmsof(op1,vl); +} + + +vbool1_t test___riscv_vmsof(vbool1_t mask,vbool1_t op1,size_t vl) +{ + return __riscv_vmsof(mask,op1,vl); +} + + +vbool2_t test___riscv_vmsof(vbool2_t mask,vbool2_t op1,size_t vl) +{ + return __riscv_vmsof(mask,op1,vl); +} + + +vbool4_t test___riscv_vmsof(vbool4_t mask,vbool4_t op1,size_t vl) +{ + return __riscv_vmsof(mask,op1,vl); +} + + +vbool8_t test___riscv_vmsof(vbool8_t mask,vbool8_t op1,size_t vl) +{ + return __riscv_vmsof(mask,op1,vl); +} + + +vbool16_t test___riscv_vmsof(vbool16_t mask,vbool16_t op1,size_t vl) +{ + return __riscv_vmsof(mask,op1,vl); +} + + +vbool32_t test___riscv_vmsof(vbool32_t mask,vbool32_t op1,size_t vl) +{ + return __riscv_vmsof(mask,op1,vl); +} + + +vbool64_t test___riscv_vmsof(vbool64_t mask,vbool64_t op1,size_t vl) +{ + return __riscv_vmsof(mask,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsof_m-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmsof_m-2.C new file mode 100644 index 00000000000..810be975b11 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsof_m-2.C @@ -0,0 +1,104 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmsof(vbool1_t op1,size_t vl) +{ + return __riscv_vmsof(op1,31); +} + + +vbool2_t test___riscv_vmsof(vbool2_t op1,size_t vl) +{ + return __riscv_vmsof(op1,31); +} + + +vbool4_t test___riscv_vmsof(vbool4_t op1,size_t vl) +{ + return __riscv_vmsof(op1,31); +} + + +vbool8_t test___riscv_vmsof(vbool8_t op1,size_t vl) +{ + return __riscv_vmsof(op1,31); +} + + +vbool16_t test___riscv_vmsof(vbool16_t op1,size_t vl) +{ + return __riscv_vmsof(op1,31); +} + + +vbool32_t test___riscv_vmsof(vbool32_t op1,size_t vl) +{ + return __riscv_vmsof(op1,31); +} + + +vbool64_t test___riscv_vmsof(vbool64_t op1,size_t vl) +{ + return __riscv_vmsof(op1,31); +} + + +vbool1_t test___riscv_vmsof(vbool1_t mask,vbool1_t op1,size_t vl) +{ + return __riscv_vmsof(mask,op1,31); +} + + +vbool2_t test___riscv_vmsof(vbool2_t mask,vbool2_t op1,size_t vl) +{ + return __riscv_vmsof(mask,op1,31); +} + + +vbool4_t test___riscv_vmsof(vbool4_t mask,vbool4_t op1,size_t vl) +{ + return __riscv_vmsof(mask,op1,31); +} + + +vbool8_t test___riscv_vmsof(vbool8_t mask,vbool8_t op1,size_t vl) +{ + return __riscv_vmsof(mask,op1,31); +} + + +vbool16_t test___riscv_vmsof(vbool16_t mask,vbool16_t op1,size_t vl) +{ + return __riscv_vmsof(mask,op1,31); +} + + +vbool32_t test___riscv_vmsof(vbool32_t mask,vbool32_t op1,size_t vl) +{ + return __riscv_vmsof(mask,op1,31); +} + + +vbool64_t test___riscv_vmsof(vbool64_t mask,vbool64_t op1,size_t vl) +{ + return __riscv_vmsof(mask,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsof_m-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmsof_m-3.C new file mode 100644 index 00000000000..c6bdc8311ed --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsof_m-3.C @@ -0,0 +1,104 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmsof(vbool1_t op1,size_t vl) +{ + return __riscv_vmsof(op1,32); +} + + +vbool2_t test___riscv_vmsof(vbool2_t op1,size_t vl) +{ + return __riscv_vmsof(op1,32); +} + + +vbool4_t test___riscv_vmsof(vbool4_t op1,size_t vl) +{ + return __riscv_vmsof(op1,32); +} + + +vbool8_t test___riscv_vmsof(vbool8_t op1,size_t vl) +{ + return __riscv_vmsof(op1,32); +} + + +vbool16_t test___riscv_vmsof(vbool16_t op1,size_t vl) +{ + return __riscv_vmsof(op1,32); +} + + +vbool32_t test___riscv_vmsof(vbool32_t op1,size_t vl) +{ + return __riscv_vmsof(op1,32); +} + + +vbool64_t test___riscv_vmsof(vbool64_t op1,size_t vl) +{ + return __riscv_vmsof(op1,32); +} + + +vbool1_t test___riscv_vmsof(vbool1_t mask,vbool1_t op1,size_t vl) +{ + return __riscv_vmsof(mask,op1,32); +} + + +vbool2_t test___riscv_vmsof(vbool2_t mask,vbool2_t op1,size_t vl) +{ + return __riscv_vmsof(mask,op1,32); +} + + +vbool4_t test___riscv_vmsof(vbool4_t mask,vbool4_t op1,size_t vl) +{ + return __riscv_vmsof(mask,op1,32); +} + + +vbool8_t test___riscv_vmsof(vbool8_t mask,vbool8_t op1,size_t vl) +{ + return __riscv_vmsof(mask,op1,32); +} + + +vbool16_t test___riscv_vmsof(vbool16_t mask,vbool16_t op1,size_t vl) +{ + return __riscv_vmsof(mask,op1,32); +} + + +vbool32_t test___riscv_vmsof(vbool32_t mask,vbool32_t op1,size_t vl) +{ + return __riscv_vmsof(mask,op1,32); +} + + +vbool64_t test___riscv_vmsof(vbool64_t mask,vbool64_t op1,size_t vl) +{ + return __riscv_vmsof(mask,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsof_m_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmsof_m_mu-1.C new file mode 100644 index 00000000000..6746a0e1314 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsof_m_mu-1.C @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmsof_mu(vbool1_t mask,vbool1_t maskedoff,vbool1_t op1,size_t vl) +{ + return __riscv_vmsof_mu(mask,maskedoff,op1,vl); +} + + +vbool2_t test___riscv_vmsof_mu(vbool2_t mask,vbool2_t maskedoff,vbool2_t op1,size_t vl) +{ + return __riscv_vmsof_mu(mask,maskedoff,op1,vl); +} + + +vbool4_t test___riscv_vmsof_mu(vbool4_t mask,vbool4_t maskedoff,vbool4_t op1,size_t vl) +{ + return __riscv_vmsof_mu(mask,maskedoff,op1,vl); +} + + +vbool8_t test___riscv_vmsof_mu(vbool8_t mask,vbool8_t maskedoff,vbool8_t op1,size_t vl) +{ + return __riscv_vmsof_mu(mask,maskedoff,op1,vl); +} + + +vbool16_t test___riscv_vmsof_mu(vbool16_t mask,vbool16_t maskedoff,vbool16_t op1,size_t vl) +{ + return __riscv_vmsof_mu(mask,maskedoff,op1,vl); +} + + +vbool32_t test___riscv_vmsof_mu(vbool32_t mask,vbool32_t maskedoff,vbool32_t op1,size_t vl) +{ + return __riscv_vmsof_mu(mask,maskedoff,op1,vl); +} + + +vbool64_t test___riscv_vmsof_mu(vbool64_t mask,vbool64_t maskedoff,vbool64_t op1,size_t vl) +{ + return __riscv_vmsof_mu(mask,maskedoff,op1,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsof_m_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmsof_m_mu-2.C new file mode 100644 index 00000000000..4f4183b45cc --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsof_m_mu-2.C @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmsof_mu(vbool1_t mask,vbool1_t maskedoff,vbool1_t op1,size_t vl) +{ + return __riscv_vmsof_mu(mask,maskedoff,op1,31); +} + + +vbool2_t test___riscv_vmsof_mu(vbool2_t mask,vbool2_t maskedoff,vbool2_t op1,size_t vl) +{ + return __riscv_vmsof_mu(mask,maskedoff,op1,31); +} + + +vbool4_t test___riscv_vmsof_mu(vbool4_t mask,vbool4_t maskedoff,vbool4_t op1,size_t vl) +{ + return __riscv_vmsof_mu(mask,maskedoff,op1,31); +} + + +vbool8_t test___riscv_vmsof_mu(vbool8_t mask,vbool8_t maskedoff,vbool8_t op1,size_t vl) +{ + return __riscv_vmsof_mu(mask,maskedoff,op1,31); +} + + +vbool16_t test___riscv_vmsof_mu(vbool16_t mask,vbool16_t maskedoff,vbool16_t op1,size_t vl) +{ + return __riscv_vmsof_mu(mask,maskedoff,op1,31); +} + + +vbool32_t test___riscv_vmsof_mu(vbool32_t mask,vbool32_t maskedoff,vbool32_t op1,size_t vl) +{ + return __riscv_vmsof_mu(mask,maskedoff,op1,31); +} + + +vbool64_t test___riscv_vmsof_mu(vbool64_t mask,vbool64_t maskedoff,vbool64_t op1,size_t vl) +{ + return __riscv_vmsof_mu(mask,maskedoff,op1,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmsof_m_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmsof_m_mu-3.C new file mode 100644 index 00000000000..c1f5657fc65 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmsof_m_mu-3.C @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmsof_mu(vbool1_t mask,vbool1_t maskedoff,vbool1_t op1,size_t vl) +{ + return __riscv_vmsof_mu(mask,maskedoff,op1,32); +} + + +vbool2_t test___riscv_vmsof_mu(vbool2_t mask,vbool2_t maskedoff,vbool2_t op1,size_t vl) +{ + return __riscv_vmsof_mu(mask,maskedoff,op1,32); +} + + +vbool4_t test___riscv_vmsof_mu(vbool4_t mask,vbool4_t maskedoff,vbool4_t op1,size_t vl) +{ + return __riscv_vmsof_mu(mask,maskedoff,op1,32); +} + + +vbool8_t test___riscv_vmsof_mu(vbool8_t mask,vbool8_t maskedoff,vbool8_t op1,size_t vl) +{ + return __riscv_vmsof_mu(mask,maskedoff,op1,32); +} + + +vbool16_t test___riscv_vmsof_mu(vbool16_t mask,vbool16_t maskedoff,vbool16_t op1,size_t vl) +{ + return __riscv_vmsof_mu(mask,maskedoff,op1,32); +} + + +vbool32_t test___riscv_vmsof_mu(vbool32_t mask,vbool32_t maskedoff,vbool32_t op1,size_t vl) +{ + return __riscv_vmsof_mu(mask,maskedoff,op1,32); +} + + +vbool64_t test___riscv_vmsof_mu(vbool64_t mask,vbool64_t maskedoff,vbool64_t op1,size_t vl) +{ + return __riscv_vmsof_mu(mask,maskedoff,op1,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmsof\.m\s+v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmxnor_mm-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmxnor_mm-1.C new file mode 100644 index 00000000000..b2f895619d4 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmxnor_mm-1.C @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmxnor(vbool1_t op1,vbool1_t op2,size_t vl) +{ + return __riscv_vmxnor(op1,op2,vl); +} + + +vbool2_t test___riscv_vmxnor(vbool2_t op1,vbool2_t op2,size_t vl) +{ + return __riscv_vmxnor(op1,op2,vl); +} + + +vbool4_t test___riscv_vmxnor(vbool4_t op1,vbool4_t op2,size_t vl) +{ + return __riscv_vmxnor(op1,op2,vl); +} + + +vbool8_t test___riscv_vmxnor(vbool8_t op1,vbool8_t op2,size_t vl) +{ + return __riscv_vmxnor(op1,op2,vl); +} + + +vbool16_t test___riscv_vmxnor(vbool16_t op1,vbool16_t op2,size_t vl) +{ + return __riscv_vmxnor(op1,op2,vl); +} + + +vbool32_t test___riscv_vmxnor(vbool32_t op1,vbool32_t op2,size_t vl) +{ + return __riscv_vmxnor(op1,op2,vl); +} + + +vbool64_t test___riscv_vmxnor(vbool64_t op1,vbool64_t op2,size_t vl) +{ + return __riscv_vmxnor(op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmxnor_mm-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmxnor_mm-2.C new file mode 100644 index 00000000000..c01e80b05e0 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmxnor_mm-2.C @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmxnor(vbool1_t op1,vbool1_t op2,size_t vl) +{ + return __riscv_vmxnor(op1,op2,31); +} + + +vbool2_t test___riscv_vmxnor(vbool2_t op1,vbool2_t op2,size_t vl) +{ + return __riscv_vmxnor(op1,op2,31); +} + + +vbool4_t test___riscv_vmxnor(vbool4_t op1,vbool4_t op2,size_t vl) +{ + return __riscv_vmxnor(op1,op2,31); +} + + +vbool8_t test___riscv_vmxnor(vbool8_t op1,vbool8_t op2,size_t vl) +{ + return __riscv_vmxnor(op1,op2,31); +} + + +vbool16_t test___riscv_vmxnor(vbool16_t op1,vbool16_t op2,size_t vl) +{ + return __riscv_vmxnor(op1,op2,31); +} + + +vbool32_t test___riscv_vmxnor(vbool32_t op1,vbool32_t op2,size_t vl) +{ + return __riscv_vmxnor(op1,op2,31); +} + + +vbool64_t test___riscv_vmxnor(vbool64_t op1,vbool64_t op2,size_t vl) +{ + return __riscv_vmxnor(op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmxnor_mm-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmxnor_mm-3.C new file mode 100644 index 00000000000..95dfefffbf5 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmxnor_mm-3.C @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmxnor(vbool1_t op1,vbool1_t op2,size_t vl) +{ + return __riscv_vmxnor(op1,op2,32); +} + + +vbool2_t test___riscv_vmxnor(vbool2_t op1,vbool2_t op2,size_t vl) +{ + return __riscv_vmxnor(op1,op2,32); +} + + +vbool4_t test___riscv_vmxnor(vbool4_t op1,vbool4_t op2,size_t vl) +{ + return __riscv_vmxnor(op1,op2,32); +} + + +vbool8_t test___riscv_vmxnor(vbool8_t op1,vbool8_t op2,size_t vl) +{ + return __riscv_vmxnor(op1,op2,32); +} + + +vbool16_t test___riscv_vmxnor(vbool16_t op1,vbool16_t op2,size_t vl) +{ + return __riscv_vmxnor(op1,op2,32); +} + + +vbool32_t test___riscv_vmxnor(vbool32_t op1,vbool32_t op2,size_t vl) +{ + return __riscv_vmxnor(op1,op2,32); +} + + +vbool64_t test___riscv_vmxnor(vbool64_t op1,vbool64_t op2,size_t vl) +{ + return __riscv_vmxnor(op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmxnor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmxor_mm-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmxor_mm-1.C new file mode 100644 index 00000000000..585dc963d3a --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmxor_mm-1.C @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmxor(vbool1_t op1,vbool1_t op2,size_t vl) +{ + return __riscv_vmxor(op1,op2,vl); +} + + +vbool2_t test___riscv_vmxor(vbool2_t op1,vbool2_t op2,size_t vl) +{ + return __riscv_vmxor(op1,op2,vl); +} + + +vbool4_t test___riscv_vmxor(vbool4_t op1,vbool4_t op2,size_t vl) +{ + return __riscv_vmxor(op1,op2,vl); +} + + +vbool8_t test___riscv_vmxor(vbool8_t op1,vbool8_t op2,size_t vl) +{ + return __riscv_vmxor(op1,op2,vl); +} + + +vbool16_t test___riscv_vmxor(vbool16_t op1,vbool16_t op2,size_t vl) +{ + return __riscv_vmxor(op1,op2,vl); +} + + +vbool32_t test___riscv_vmxor(vbool32_t op1,vbool32_t op2,size_t vl) +{ + return __riscv_vmxor(op1,op2,vl); +} + + +vbool64_t test___riscv_vmxor(vbool64_t op1,vbool64_t op2,size_t vl) +{ + return __riscv_vmxor(op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmxor_mm-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmxor_mm-2.C new file mode 100644 index 00000000000..29849aca07f --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmxor_mm-2.C @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmxor(vbool1_t op1,vbool1_t op2,size_t vl) +{ + return __riscv_vmxor(op1,op2,31); +} + + +vbool2_t test___riscv_vmxor(vbool2_t op1,vbool2_t op2,size_t vl) +{ + return __riscv_vmxor(op1,op2,31); +} + + +vbool4_t test___riscv_vmxor(vbool4_t op1,vbool4_t op2,size_t vl) +{ + return __riscv_vmxor(op1,op2,31); +} + + +vbool8_t test___riscv_vmxor(vbool8_t op1,vbool8_t op2,size_t vl) +{ + return __riscv_vmxor(op1,op2,31); +} + + +vbool16_t test___riscv_vmxor(vbool16_t op1,vbool16_t op2,size_t vl) +{ + return __riscv_vmxor(op1,op2,31); +} + + +vbool32_t test___riscv_vmxor(vbool32_t op1,vbool32_t op2,size_t vl) +{ + return __riscv_vmxor(op1,op2,31); +} + + +vbool64_t test___riscv_vmxor(vbool64_t op1,vbool64_t op2,size_t vl) +{ + return __riscv_vmxor(op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vmxor_mm-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vmxor_mm-3.C new file mode 100644 index 00000000000..802ec213179 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vmxor_mm-3.C @@ -0,0 +1,55 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vbool1_t test___riscv_vmxor(vbool1_t op1,vbool1_t op2,size_t vl) +{ + return __riscv_vmxor(op1,op2,32); +} + + +vbool2_t test___riscv_vmxor(vbool2_t op1,vbool2_t op2,size_t vl) +{ + return __riscv_vmxor(op1,op2,32); +} + + +vbool4_t test___riscv_vmxor(vbool4_t op1,vbool4_t op2,size_t vl) +{ + return __riscv_vmxor(op1,op2,32); +} + + +vbool8_t test___riscv_vmxor(vbool8_t op1,vbool8_t op2,size_t vl) +{ + return __riscv_vmxor(op1,op2,32); +} + + +vbool16_t test___riscv_vmxor(vbool16_t op1,vbool16_t op2,size_t vl) +{ + return __riscv_vmxor(op1,op2,32); +} + + +vbool32_t test___riscv_vmxor(vbool32_t op1,vbool32_t op2,size_t vl) +{ + return __riscv_vmxor(op1,op2,32); +} + + +vbool64_t test___riscv_vmxor(vbool64_t op1,vbool64_t op2,size_t vl) +{ + return __riscv_vmxor(op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmxor\.mm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ -- 2.36.1