From: Tejas Belagod <tejas.belagod@arm.com>
To: <gcc-patches@gcc.gnu.org>
Cc: Tejas Belagod <tejas.belagod@arm.com>,
<richard.sandiford@arm.com>, <Richard.Earnshaw@arm.com>
Subject: [PATCH 2/2, GCC12] AArch64: Gate various crypto intrinsics availability based on features
Date: Thu, 16 Feb 2023 06:13:51 +0000 [thread overview]
Message-ID: <20230216061351.25090-2-tejas.belagod@arm.com> (raw)
In-Reply-To: <20230216061351.25090-1-tejas.belagod@arm.com>
The 64-bit variant of PMULL{2} and AES instructions are available if FEAT_AES
is implemented according to the Arm ARM [1]. Similarly FEAT_SHA1 and
FEAT_SHA256 enable the use of SHA1 and SHA256 instruction variants.
This patch fixes arm_neon.h to correctly reflect the feature availability based
on '+aes' and '+sha2' as opposed to the ambiguous catch-all '+crypto'.
[1] Section D17.2.61, C7.2.215
2022-01-11 Tejas Belagod <tejas.belagod@arm.com>
gcc/ChangeLog:
* config/aarch64/arm_neon.h (vmull_p64, vmull_high_p64, vaeseq_u8,
vaesdq_u8, vaesmcq_u8, vaesimcq_u8): Gate under "nothing+aes".
(vsha1*_u32, vsha256*_u32): Gate under "nothing+sha2".
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/acle/pmull64.c: New.
* gcc.target/aarch64/aes-fuse-1.c: Replace '+crypto' with corresponding
feature flag based on the intrinsic.
* gcc.target/aarch64/aes-fuse-2.c: Likewise.
* gcc.target/aarch64/aes_1.c: Likewise.
* gcc.target/aarch64/aes_2.c: Likewise.
* gcc.target/aarch64/aes_xor_combine.c: Likewise.
* gcc.target/aarch64/sha1_1.c: Likewise.
* gcc.target/aarch64/sha256_1.c: Likewise.
* gcc.target/aarch64/target_attr_crypto_ice_1.c: Likewise.
---
gcc/config/aarch64/arm_neon.h | 35 ++++++++++---------
.../gcc.target/aarch64/acle/pmull64.c | 14 ++++++++
gcc/testsuite/gcc.target/aarch64/aes-fuse-1.c | 4 +--
gcc/testsuite/gcc.target/aarch64/aes-fuse-2.c | 4 +--
gcc/testsuite/gcc.target/aarch64/aes_1.c | 2 +-
gcc/testsuite/gcc.target/aarch64/aes_2.c | 4 ++-
.../gcc.target/aarch64/aes_xor_combine.c | 2 +-
gcc/testsuite/gcc.target/aarch64/sha1_1.c | 2 +-
gcc/testsuite/gcc.target/aarch64/sha256_1.c | 2 +-
.../aarch64/target_attr_crypto_ice_1.c | 2 +-
10 files changed, 44 insertions(+), 27 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/aarch64/acle/pmull64.c
diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h
index 85d03c58d2a..695aafd9a5e 100644
--- a/gcc/config/aarch64/arm_neon.h
+++ b/gcc/config/aarch64/arm_neon.h
@@ -10243,7 +10243,7 @@ vqrdmlshs_laneq_s32 (int32_t __a, int32_t __b, int32x4_t __c, const int __d)
#pragma GCC pop_options
#pragma GCC push_options
-#pragma GCC target ("+nothing+crypto")
+#pragma GCC target ("+nothing+aes")
/* vaes */
__extension__ extern __inline uint8x16_t
@@ -10273,6 +10273,22 @@ vaesimcq_u8 (uint8x16_t data)
{
return __builtin_aarch64_crypto_aesimcv16qi_uu (data);
}
+
+__extension__ extern __inline poly128_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vmull_p64 (poly64_t __a, poly64_t __b)
+{
+ return
+ __builtin_aarch64_crypto_pmulldi_ppp (__a, __b);
+}
+
+__extension__ extern __inline poly128_t
+__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
+vmull_high_p64 (poly64x2_t __a, poly64x2_t __b)
+{
+ return __builtin_aarch64_crypto_pmullv2di_ppp (__a, __b);
+}
+
#pragma GCC pop_options
/* vcage */
@@ -23519,7 +23535,7 @@ vrsrad_n_u64 (uint64_t __a, uint64_t __b, const int __c)
}
#pragma GCC push_options
-#pragma GCC target ("+nothing+crypto")
+#pragma GCC target ("+nothing+sha2")
/* vsha1 */
@@ -23596,21 +23612,6 @@ vsha256su1q_u32 (uint32x4_t __tw0_3, uint32x4_t __w8_11, uint32x4_t __w12_15)
__w12_15);
}
-__extension__ extern __inline poly128_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmull_p64 (poly64_t __a, poly64_t __b)
-{
- return
- __builtin_aarch64_crypto_pmulldi_ppp (__a, __b);
-}
-
-__extension__ extern __inline poly128_t
-__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
-vmull_high_p64 (poly64x2_t __a, poly64x2_t __b)
-{
- return __builtin_aarch64_crypto_pmullv2di_ppp (__a, __b);
-}
-
#pragma GCC pop_options
/* vshl */
diff --git a/gcc/testsuite/gcc.target/aarch64/acle/pmull64.c b/gcc/testsuite/gcc.target/aarch64/acle/pmull64.c
new file mode 100644
index 00000000000..6a1e99e2d0d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/acle/pmull64.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=armv8.2-a" } */
+
+#pragma push_options
+#pragma GCC target ("+aes")
+
+#include "arm_neon.h"
+
+int foo (poly64_t a, poly64_t b)
+{
+ return vgetq_lane_s32 (vreinterpretq_s32_p128 (vmull_p64 (a, b)), 0);
+}
+
+/* { dg-final { scan-assembler "\tpmull\tv" } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/aes-fuse-1.c b/gcc/testsuite/gcc.target/aarch64/aes-fuse-1.c
index d7b4f89919d..1b4e10f78db 100644
--- a/gcc/testsuite/gcc.target/aarch64/aes-fuse-1.c
+++ b/gcc/testsuite/gcc.target/aarch64/aes-fuse-1.c
@@ -1,6 +1,6 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -mcpu=cortex-a72+crypto -dp" } */
-/* { dg-additional-options "-march=armv8-a+crypto" { target { aarch64*-*-* } } }*/
+/* { dg-options "-O3 -mcpu=cortex-a72+aes -dp" } */
+/* { dg-additional-options "-march=armv8-a+aes" { target { aarch64*-*-* } } }*/
#include <arm_neon.h>
diff --git a/gcc/testsuite/gcc.target/aarch64/aes-fuse-2.c b/gcc/testsuite/gcc.target/aarch64/aes-fuse-2.c
index dfe01b03a36..4c028b39083 100644
--- a/gcc/testsuite/gcc.target/aarch64/aes-fuse-2.c
+++ b/gcc/testsuite/gcc.target/aarch64/aes-fuse-2.c
@@ -1,6 +1,6 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -mcpu=cortex-a72+crypto -dp" } */
-/* { dg-additional-options "-march=armv8-a+crypto" { target { aarch64*-*-* } } }*/
+/* { dg-options "-O3 -mcpu=cortex-a72+aes -dp" } */
+/* { dg-additional-options "-march=armv8-a+aes" { target { aarch64*-*-* } } }*/
#include <arm_neon.h>
diff --git a/gcc/testsuite/gcc.target/aarch64/aes_1.c b/gcc/testsuite/gcc.target/aarch64/aes_1.c
index 5578e85dab7..754c4ab90e7 100644
--- a/gcc/testsuite/gcc.target/aarch64/aes_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/aes_1.c
@@ -1,6 +1,6 @@
/* { dg-do compile } */
-/* { dg-options "-march=armv8-a+crypto" } */
+/* { dg-options "-march=armv8-a+aes" } */
#include "arm_neon.h"
diff --git a/gcc/testsuite/gcc.target/aarch64/aes_2.c b/gcc/testsuite/gcc.target/aarch64/aes_2.c
index 70f113fb5ab..442c1006706 100644
--- a/gcc/testsuite/gcc.target/aarch64/aes_2.c
+++ b/gcc/testsuite/gcc.target/aarch64/aes_2.c
@@ -1,6 +1,6 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -march=armv8-a+crypto" } */
+/* { dg-options "-O3 -march=armv8-a+aes" } */
#include "arm_neon.h"
@@ -76,4 +76,6 @@ test7 (uint8x16_t a, uint8x16_t b)
return result;
}
/* { dg-final { scan-assembler-not "mov" } } */
+/* { dg-final { scan-assembler "aesd\tv" } } */
+/* { dg-final { scan-assembler "aese\tv" } } */
diff --git a/gcc/testsuite/gcc.target/aarch64/aes_xor_combine.c b/gcc/testsuite/gcc.target/aarch64/aes_xor_combine.c
index 833e9b3073b..ee0f0e99856 100644
--- a/gcc/testsuite/gcc.target/aarch64/aes_xor_combine.c
+++ b/gcc/testsuite/gcc.target/aarch64/aes_xor_combine.c
@@ -1,5 +1,5 @@
/* { dg-do compile } */
-/* { dg-options "-O3 -mcpu=cortex-a55+crypto" } */
+/* { dg-options "-O3 -mcpu=cortex-a55+aes" } */
#include <arm_neon.h>
#define AESE(r, v, key) (r = vaeseq_u8 ((v), (key)));
diff --git a/gcc/testsuite/gcc.target/aarch64/sha1_1.c b/gcc/testsuite/gcc.target/aarch64/sha1_1.c
index e208fe7d93f..ba56c04a118 100644
--- a/gcc/testsuite/gcc.target/aarch64/sha1_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/sha1_1.c
@@ -1,6 +1,6 @@
/* { dg-do compile } */
-/* { dg-options "-march=armv8-a+crypto" } */
+/* { dg-options "-march=armv8-a+sha2" } */
#include "arm_neon.h"
diff --git a/gcc/testsuite/gcc.target/aarch64/sha256_1.c b/gcc/testsuite/gcc.target/aarch64/sha256_1.c
index 2102daf20a3..c3860c6b537 100644
--- a/gcc/testsuite/gcc.target/aarch64/sha256_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/sha256_1.c
@@ -1,6 +1,6 @@
/* { dg-do compile } */
-/* { dg-options "-march=armv8-a+crypto" } */
+/* { dg-options "-march=armv8-a+sha2" } */
#include "arm_neon.h"
diff --git a/gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_1.c b/gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_1.c
index c74cc900f98..3b354c06110 100644
--- a/gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_1.c
+++ b/gcc/testsuite/gcc.target/aarch64/target_attr_crypto_ice_1.c
@@ -6,7 +6,7 @@
/* Unless we do something about re-laying out the SIMD builtin types
this testcase ICEs during expansion of the crypto builtin. */
-__attribute__ ((target ("cpu=cortex-a57+crypto")))
+__attribute__ ((target ("cpu=cortex-a57+sha2")))
uint32x4_t
test_vsha1cq_u32 (uint32x4_t hash_abcd, uint32_t hash_e, uint32x4_t wk)
{
--
2.17.1
next prev parent reply other threads:[~2023-02-16 6:14 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-16 6:13 [PATCH 1/2, GCC12] AArch64: Update transitive closures of aes, sha2 and sha3 extensions Tejas Belagod
2023-02-16 6:13 ` Tejas Belagod [this message]
2023-02-27 12:19 ` [PATCH 2/2, GCC12] AArch64: Gate various crypto intrinsics availability based on features Richard Sandiford
2023-02-27 12:16 ` [PATCH 1/2, GCC12] AArch64: Update transitive closures of aes, sha2 and sha3 extensions Richard Sandiford
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230216061351.25090-2-tejas.belagod@arm.com \
--to=tejas.belagod@arm.com \
--cc=Richard.Earnshaw@arm.com \
--cc=gcc-patches@gcc.gnu.org \
--cc=richard.sandiford@arm.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).