From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from t04.bc.larksuite.com (t04.bc.larksuite.com [209.127.231.40]) by sourceware.org (Postfix) with UTF8SMTPS id 254513858C78 for ; Fri, 17 Feb 2023 08:36:13 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 254513858C78 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=oss.cipunited.com Authentication-Results: sourceware.org; spf=none smtp.mailfrom=oss.cipunited.com DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=s1; d=oss-cipunited-com.20200927.dkim.feishu.cn; t=1676622967; h=from:subject:mime-version:from:date:message-id:subject:to:cc: reply-to:content-type:mime-version:in-reply-to:message-id; bh=OFeRUHFRB0L6XaHs+xC26OBf2k7D2fWWxYw5xoFbh9Y=; b=OfVOgp2Z68B2TcE90ObD+ebtqxtk2LOX2+ZP/pYxzsahLO4IpJt6EekycwYHtJhqOqI6bK 0LZL7cS1KdbOlNtOLbKAo7N6tjcS3HgDyN9M7ZyrPgJU6FNdjamDUhIglCqqn7Qott7KrX jZ1vm2OC0X9G6AZHhkZoekVuY4vSNCaLM5OvmXOOi2qZyg358Zx+BRrXSCvBxp9RczUrA0 yECTZbz/LRC0OCel+v5tw9igkFZtrYGYCdUsF8dLF1k3DsbWOssPsdlTRj05+GKS6D05e7 q+8Py65rtQHLyww9yN3v0lLrJCVGcJxivIKd2AoWryJUxRXxM+NSUb41Y7fECQ== Subject: [PATCH] Add pattern for clo Mime-Version: 1.0 X-Lms-Return-Path: To: X-Original-From: "Junxian Zhu" Message-Id: <20230217083531.3409405-1-zhujunxian@oss.cipunited.com> Content-Transfer-Encoding: 8bit Content-Type: multipart/alternative; boundary=b8a7ce38928f275bea56008670b097fc7992ea30365e0b4a72974c0177a8 Cc: , , "Junxian Zhu" Date: Fri, 17 Feb 2023 16:35:56 +0800 From: "Junxian Zhu" X-Mailer: git-send-email 2.39.1 X-Spam-Status: No, score=-13.7 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,HTML_MESSAGE,KAM_SHORT,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: --b8a7ce38928f275bea56008670b097fc7992ea30365e0b4a72974c0177a8 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 From: Junxian Zhu gcc/ChangeLog: * config/mips/mips.md (*clo2): New pattern. gcc/testsuite/ChangeLog: * gcc.target/mips/clz.c: New test. * gcc.target/mips/clz.c: New test. * gcc.target/mips/mips.exp: New option HAS_CLZ. Signed-off-by: Junxian Zhu --- gcc/config/mips/mips.md | 9 +++++++++ gcc/testsuite/gcc.target/mips/clo.c | 11 +++++++++++ gcc/testsuite/gcc.target/mips/clz.c | 10 ++++++++++ gcc/testsuite/gcc.target/mips/mips.exp | 3 +++ 4 files changed, 33 insertions(+) create mode 100644 gcc/testsuite/gcc.target/mips/clo.c create mode 100644 gcc/testsuite/gcc.target/mips/clz.c diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index e3bf32a3430..10607a57efc 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -3165,6 +3165,15 @@ [(set_attr "type" "clz") (set_attr "mode" "")]) =20 + +(define_insn "*clo2" + [(set (match_operand:GPR 0 "register_operand" "=3Dd") + (clz:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d"))))] + "ISA_HAS_CLZ_CLO" + "clo\t%0,%1" + [(set_attr "type" "clz") + (set_attr "mode" "")]) + ;; ;; ................... ;; diff --git a/gcc/testsuite/gcc.target/mips/clo.c b/gcc/testsuite/gcc.target= /mips/clo.c new file mode 100644 index 00000000000..91f29a1322a --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/clo.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "(HAS_CLZ)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +NOMIPS16 unsigned int foo(unsigned int x) +{ + return __builtin_clz (~x); +} + +/* { dg-final { scan-assembler-not "\tclz\t" } } */ +/* { dg-final { scan-assembler "\tclo\t" } } */ diff --git a/gcc/testsuite/gcc.target/mips/clz.c b/gcc/testsuite/gcc.target= /mips/clz.c new file mode 100644 index 00000000000..74e6edb90aa --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/clz.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "(HAS_CLZ)" } */ +/* { dg-skip-if "code quality test" { *-*-* } { "-O0" } { "" } } */ + +NOMIPS16 unsigned int foo(unsigned int x) +{ + return __builtin_clz (x); +} + +/* { dg-final { scan-assembler "\tclz\t" } } */ diff --git a/gcc/testsuite/gcc.target/mips/mips.exp b/gcc/testsuite/gcc.tar= get/mips/mips.exp index 025fbe78359..ac3ab129541 100644 --- a/gcc/testsuite/gcc.target/mips/mips.exp +++ b/gcc/testsuite/gcc.target/mips/mips.exp @@ -252,6 +252,7 @@ set mips_option_groups { warnings "-w" dump "-fdump-.*" ins "HAS_INS" + clz "HAS_CLZ" dmul "NOT_HAS_DMUL" ldc "HAS_LDC" movn "HAS_MOVN" @@ -1198,11 +1199,13 @@ proc mips-dg-options { args } { # # - paired-single instructions(*) # - odd numbered single precision registers + # - clz clo instructions # # (*) Note that we don't support MIPS V at the moment. } elseif { $isa_rev < 1 && ([mips_have_test_option_p options "-mpaired-single"] || ([mips_have_test_option_p options "-modd-spreg"] + || [mips_have_test_option_p options "HAS_CLZ"] && ![mips_have_test_option_p options "-mfp64"]))} { if { $gp_size =3D=3D 32 } { mips_make_test_option options "-mips32" --=20 2.39.1= --b8a7ce38928f275bea56008670b097fc7992ea30365e0b4a72974c0177a8--