From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pl1-x632.google.com (mail-pl1-x632.google.com [IPv6:2607:f8b0:4864:20::632]) by sourceware.org (Postfix) with ESMTPS id A286A3858D33 for ; Wed, 1 Mar 2023 19:53:20 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org A286A3858D33 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-pl1-x632.google.com with SMTP id z2so15168032plf.12 for ; Wed, 01 Mar 2023 11:53:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; t=1677700398; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=WoiwmQNwOkZcVBLxrgqtgsyVfbsp0nRQe+NXEbAWXOY=; b=AVhfticEVZ5BA1Np6olw9iAifOA+hk2bRWK1xXvjjdoXM94lqIf1FDDBhiCts75H4N OwlYfjppQN9z0sVdpRfjLVVxhn9GircZRaj2YXYq6IIe+sbdMFmguBe31yYX8J5C9Mo8 tNC+ArdoHwTd49s1yFM09nTt9MQhVP6y2ZNrfNRSzgvTOz9GwKmNmpz6bTOpFi9u9Q+r mWIbO38ORf3+E03f+852FiXaipumzwl/ZtJ1zhuBVlm1PyBaz8+7CV5iXSjbHimOrK/p /4zEFYLM99pW4k3LYVHIhj/T/jZcwLPfl+WKih5q8AI4zdPFAKU2Hvgj+bBIFHzh/lGg 3gzQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1677700398; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=WoiwmQNwOkZcVBLxrgqtgsyVfbsp0nRQe+NXEbAWXOY=; b=zdBcpidbGNjtAEPzWzbXjgMdNVxEf/XddF8DW3eGV5pbRAl7o1BtczR+d4+qaIpZ2s vw3v2GDt/SqpGQaNwRsukoAYcsrqm4JKmQRk4MjLydhBVZg1WaKeOQtQFpaz+uTpcMfx 2eZB+doSGsn5ACI+N+DRVEbHd5BFRVWY+rizfxDSkzK1r/TXIqs8Cm3Shw/c6x3w5dp+ n1xNHf2XxNQW4L+ndHeOnoPXfCqpjg4Fp2Ak//h3dL6yYgrt+A8NNTGVwl4A7mQOx+wT AUSJaqM4pGfIqYqyFrilC6Ln9M/L++DZTATvLTg2FHdHo5tAOft0NbHJ4DZs73eFN4+M olkA== X-Gm-Message-State: AO0yUKXOKkf3PPUF1WB+tOZHaXu/BTviS6XNF7BOBoXBJM2PK8Y3fDyx YshaL+ULTk6Jk1rbp1+3jQmPoWaopspN6ANyN38= X-Google-Smtp-Source: AK7set+eaZuEjOEuoFlT/kgBh6P2sgGPPq6gzrsl6KVHXRD9qdVYc7Y9oy0f5yDQEGDmGCRBSwnD8w== X-Received: by 2002:a17:90b:1bcc:b0:237:b5d4:c0e5 with SMTP id oa12-20020a17090b1bcc00b00237b5d4c0e5mr8217814pjb.27.1677700398599; Wed, 01 Mar 2023 11:53:18 -0800 (PST) Received: from vineet-framework.ba.rivosinc.com ([71.202.114.183]) by smtp.gmail.com with ESMTPSA id y6-20020a17090a154600b002372107fc3dsm142741pja.49.2023.03.01.11.53.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Mar 2023 11:53:18 -0800 (PST) From: Vineet Gupta To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, Palmer Dabbelt , Philipp Tomsich , Christoph Mullner , Jeff Law , gnu-toolchain@rivosinc.com, Vineet Gupta Subject: [PATCH] RISC-V: costs: miscomputed shiftadd_cost triggering synth_mult [PR/108987] Date: Wed, 1 Mar 2023 11:53:15 -0800 Message-Id: <20230301195315.1793087-1-vineetg@rivosinc.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-10.7 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: This showed up as dynamic icount regression in SPEC 531.deepsjeng with upstream gcc (vs. gcc 12.2). gcc was resorting to synthetic multiply using shift+add(s) even when multiply had clear cost benefit. |00000000000133b8 : | 133b8: srl a3,a1,s6 | 133bc: and a3,a3,s5 | 133c0: slli a4,a3,0x9 | 133c4: add a4,a4,a3 | 133c6: slli a4,a4,0x9 | 133c8: add a4,a4,a3 | 133ca: slli a3,a4,0x1b | 133ce: add a4,a4,a3 vs. gcc 12 doing something lke below. |00000000000131c4 : | 131c4: ld s1,8(sp) | 131c6: srl a3,a1,s4 | 131ca: and a3,a3,s11 | 131ce: mul a3,a3,s1 Bisected this to f90cb39235c4 ("RISC-V: costs: support shift-and-add in strength-reduction"). The intent was to optimize cost for shift-add-pow2-{1,2,3} corresponding to bitmanip insns SH*ADD, but ended up doing that for all shift values which seems to favor synthezing multiply among others. The bug itself is trivial, IN_RANGE() calling pow2p_hwi() which returns bool vs. exact_log2() returning power of 2. This fix also requires update to the test introduced by the same commit which now generates MUL vs. synthesizing it. gcc/Changelog: * config/riscv/riscv.cc (riscv_rtx_costs): Fixed IN_RANGE() to use exact_log2(). gcc/testsuite/ChangeLog: * gcc.target/riscv/zba-shNadd-07.c: f2(i*783) now generates MUL vs. 5 insn sh1add+slli+add+slli+sub. * gcc.target/riscv/pr108987.c: New test. Signed-off-by: Vineet Gupta --- gcc/config/riscv/riscv.cc | 3 ++- gcc/testsuite/gcc.target/riscv/pr108987.c | 9 +++++++++ gcc/testsuite/gcc.target/riscv/zba-shNadd-07.c | 6 +++--- 3 files changed, 14 insertions(+), 4 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/pr108987.c diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index e36ff05695a6..2cf172f59c28 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -2496,7 +2496,8 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN && GET_CODE (XEXP (x, 0)) == MULT && REG_P (XEXP (XEXP (x, 0), 0)) && CONST_INT_P (XEXP (XEXP (x, 0), 1)) - && IN_RANGE (pow2p_hwi (INTVAL (XEXP (XEXP (x, 0), 1))), 1, 3)) + && pow2p_hwi (INTVAL (XEXP (XEXP (x, 0), 1))) + && IN_RANGE (exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1))), 1, 3)) { *total = COSTS_N_INSNS (1); return true; diff --git a/gcc/testsuite/gcc.target/riscv/pr108987.c b/gcc/testsuite/gcc.target/riscv/pr108987.c new file mode 100644 index 000000000000..6179c7e13a45 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr108987.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zba -mabi=lp64 -O2" } */ + +unsigned long long f5(unsigned long long i) +{ + return i * 0x0202020202020202ULL; +} + +/* { dg-final { scan-assembler-times "mul" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/zba-shNadd-07.c b/gcc/testsuite/gcc.target/riscv/zba-shNadd-07.c index 98d35e1da9b4..93da241c9b60 100644 --- a/gcc/testsuite/gcc.target/riscv/zba-shNadd-07.c +++ b/gcc/testsuite/gcc.target/riscv/zba-shNadd-07.c @@ -26,6 +26,6 @@ f4 (unsigned long i) } /* { dg-final { scan-assembler-times "sh2add" 2 } } */ -/* { dg-final { scan-assembler-times "sh1add" 2 } } */ -/* { dg-final { scan-assembler-times "slli" 5 } } */ -/* { dg-final { scan-assembler-times "mul" 1 } } */ +/* { dg-final { scan-assembler-times "sh1add" 1 } } */ +/* { dg-final { scan-assembler-times "slli" 3 } } */ +/* { dg-final { scan-assembler-times "mul" 2 } } */ -- 2.34.1