From: Christoph Muellner <christoph.muellner@vrull.eu>
To: gcc-patches@gcc.gnu.org, Kito Cheng <kito.cheng@sifive.com>,
Jim Wilson <jim.wilson.gcc@gmail.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Andrew Waterman <andrew@sifive.com>,
Philipp Tomsich <philipp.tomsich@vrull.eu>,
Cooper Qu <cooper.qu@linux.alibaba.com>,
Lifang Xia <lifang_xia@linux.alibaba.com>,
Yunhai Shang <yunhai@linux.alibaba.com>,
Zhiwei Liu <zhiwei_liu@linux.alibaba.com>,
Andrew Pinski <pinskia@gmail.com>,
Hans-Peter Nilsson <hp@bitrange.com>
Cc: "Christoph Müllner" <christoph.muellner@vrull.eu>
Subject: [PATCH v4 4/9] riscv: thead: Add support for the XTheadBs ISA extension
Date: Thu, 2 Mar 2023 09:35:29 +0100 [thread overview]
Message-ID: <20230302083534.4076244-5-christoph.muellner@vrull.eu> (raw)
In-Reply-To: <20230302083534.4076244-1-christoph.muellner@vrull.eu>
From: Christoph Müllner <christoph.muellner@vrull.eu>
This patch adds support for the XTheadBs ISA extension.
The new INSN pattern is defined in a new file to separate
this vendor extension from the standard extensions.
The cost model adjustment reuses the xbs:bext cost.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_rtx_costs): Add xthead:tst cost.
* config/riscv/thead.md (*th_tst<mode>3): New INSN.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/xtheadbs-tst.c: New test.
Changes in v4:
- Replace 'immediate_operand' by 'const_int_operand'
- Add number of arguments to pattern name
- Add range check
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
gcc/config/riscv/riscv.cc | 4 ++--
gcc/config/riscv/thead.md | 11 +++++++++++
gcc/testsuite/gcc.target/riscv/xtheadbs-tst.c | 13 +++++++++++++
3 files changed, 26 insertions(+), 2 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadbs-tst.c
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index f11b7949a49..e35bc0a745b 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -2400,8 +2400,8 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN
*total = COSTS_N_INSNS (SINGLE_SHIFT_COST);
return true;
}
- /* bext pattern for zbs. */
- if (TARGET_ZBS && outer_code == SET
+ /* bit extraction pattern (zbs:bext, xtheadbs:tst). */
+ if ((TARGET_ZBS || TARGET_XTHEADBS) && outer_code == SET
&& GET_CODE (XEXP (x, 1)) == CONST_INT
&& INTVAL (XEXP (x, 1)) == 1)
{
diff --git a/gcc/config/riscv/thead.md b/gcc/config/riscv/thead.md
index 2da5aaee94f..3842a194d16 100644
--- a/gcc/config/riscv/thead.md
+++ b/gcc/config/riscv/thead.md
@@ -29,3 +29,14 @@ (define_insn "*th_addsl<mode>4"
"th.addsl\t%0,%3,%1,%2"
[(set_attr "type" "bitmanip")
(set_attr "mode" "<X:MODE>")])
+
+;; XTheadBs
+
+(define_insn "*th_tst<mode>3"
+ [(set (match_operand:X 0 "register_operand" "=r")
+ (zero_extract:X (match_operand:X 1 "register_operand" "r")
+ (const_int 1)
+ (match_operand 2 "const_int_operand" "n")))]
+ "TARGET_XTHEADBS && UINTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode)"
+ "th.tst\t%0,%1,%2"
+ [(set_attr "type" "bitmanip")])
diff --git a/gcc/testsuite/gcc.target/riscv/xtheadbs-tst.c b/gcc/testsuite/gcc.target/riscv/xtheadbs-tst.c
new file mode 100644
index 00000000000..674cec09128
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xtheadbs-tst.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gc_xtheadbs" { target { rv32 } } } */
+/* { dg-options "-march=rv64gc_xtheadbs" { target { rv64 } } } */
+/* { dg-skip-if "" { *-*-* } { "-O0" } } */
+
+long
+foo1 (long i)
+{
+ return 1L & (i >> 20);
+}
+
+/* { dg-final { scan-assembler-times "th.tst\t" 1 } } */
+/* { dg-final { scan-assembler-not "andi" } } */
--
2.39.2
next prev parent reply other threads:[~2023-03-02 8:35 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-02 8:35 [PATCH v4 0/9] RISC-V: Add XThead* extension support Christoph Muellner
2023-03-02 8:35 ` [PATCH v4 1/9] riscv: Add basic XThead* vendor " Christoph Muellner
2023-03-02 8:35 ` [PATCH v4 2/9] riscv: riscv-cores.def: Add T-Head XuanTie C906 Christoph Muellner
2023-03-02 8:35 ` [PATCH v4 3/9] riscv: thead: Add support for the XTheadBa ISA extension Christoph Muellner
2023-03-02 8:35 ` Christoph Muellner [this message]
2023-03-02 8:35 ` [PATCH v4 5/9] riscv: thead: Add support for the XTheadBb " Christoph Muellner
2023-03-05 17:41 ` Jeff Law
2023-03-02 8:35 ` [PATCH v4 6/9] riscv: thead: Add support for the XTheadCondMov ISA extensions Christoph Muellner
2023-03-02 8:35 ` [PATCH v4 7/9] riscv: thead: Add support for the XTheadMac ISA extension Christoph Muellner
2023-03-02 8:35 ` [PATCH v4 8/9] riscv: thead: Add support for the XTheadFmv " Christoph Muellner
2023-03-02 8:35 ` [PATCH v4 9/9] riscv: thead: Add support for the XTheadMemPair " Christoph Muellner
2023-03-05 10:18 ` [PATCH v4 0/9] RISC-V: Add XThead* extension support Kito Cheng
2023-03-15 9:02 ` Philipp Tomsich
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