From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-qt1-x830.google.com (mail-qt1-x830.google.com [IPv6:2607:f8b0:4864:20::830]) by sourceware.org (Postfix) with ESMTPS id D4A1338582A3 for ; Wed, 8 Mar 2023 03:27:42 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org D4A1338582A3 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-qt1-x830.google.com with SMTP id h19so16900200qtk.7 for ; Tue, 07 Mar 2023 19:27:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; t=1678246062; h=content-transfer-encoding:mime-version:message-id:date:subject:to :from:from:to:cc:subject:date:message-id:reply-to; bh=swS/HhcrUrxR/FpqogHpVRSjOkhFuN9MX8oFcQ9lXMM=; b=i1T/psETiYzhvkaw4lsu7su6Saj8Vl4R3w+pdJR3hbLTrwEs2dpAJCeFPcfEKpsnnx RrDp1ChZCIY0YC7ONcHqC+ew2XTuu9uI9+wx/FzBn0+6n8UgKbJkO8vWcRIgbt70MuN7 FKe161BFsEdB9DuE3Mjp7RxqEiCaTcwPxt7Im/cuf678rKVPL68/PcH9z6d9+J5bVURz tfBxmEWOqtZHlCTqFkVvErPfuN9qvxvjAQ0bEd7tC2/Ss3H0o6Sr/sKtW4ysDTccvXpU Hu5KrVYVV1I0cfAw6g9zG6hucyAoBS79xkiknYUtvd0GAe2CnsTCsaqIpNUZTlrVoRcp iYew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678246062; h=content-transfer-encoding:mime-version:message-id:date:subject:to :from:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=swS/HhcrUrxR/FpqogHpVRSjOkhFuN9MX8oFcQ9lXMM=; b=PdFiA5Jqd0Yti5jcag+qdaysLCV6Z5xkDw0epyvcnY7/YEgI7dTarIlDQxy0Mj0pEk eLM2jXbdHS41VW+ACIQF9QSowvNCtwiVQP1ALI2mzsDvdYzpBL++gxQenNaiKb4MdXGO fBgz3CyywxiNiPehMeaRkSUjCPeEpdI/7qUqkofyFNDTW8lrTY9O1oRBCfnUa6QPt8X8 UzeVNeRak2I4LTEXim62qWomdWWvvHlClZIlGnVuI4DI1BYgZmDaq1S76msnLkf8Gcle scm3DR07frKCu7rFdLO4pZzVStl0ZBlOIy0/e+NJQGemy/aL4B4sY8eArRpDa2cwf4QW vQ7g== X-Gm-Message-State: AO0yUKWZPcgTwfP2L6rdrspx/g17M9E188qPw68/WnqULyrO7HeruFLL nfGJZgVHZJHWinfoh8U+IT4RKxJJO/SVZb8wIjY= X-Google-Smtp-Source: AK7set/ik59jiR9kUkxn2W35hx25bWxaGCR25luIfZsecJ+2pHbCpUbvsI3DdGzJ6Y5zi7DyB5j6Jw== X-Received: by 2002:a05:622a:148c:b0:3bf:b829:1939 with SMTP id t12-20020a05622a148c00b003bfb8291939mr26337803qtx.3.1678246062040; Tue, 07 Mar 2023 19:27:42 -0800 (PST) Received: from system76-pc.ba.rivosinc.com ([136.57.172.92]) by smtp.gmail.com with ESMTPSA id v21-20020ac87295000000b003b6382f66b1sm10759696qto.29.2023.03.07.19.27.41 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Mar 2023 19:27:41 -0800 (PST) From: Michael Collison To: gcc-patches@gcc.gnu.org Subject: [PATCH v3 0/6] RISC-V: autovec: Add auto-vectorization support Date: Tue, 7 Mar 2023 22:27:34 -0500 Message-Id: <20230308032740.989275-1-collison@rivosinc.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-6.2 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: This series of patches adds foundational support for RISC-V auto-vectorization support. These patches are based on the current upstream rvv vector intrinsic support and is not a new implementation. Most of the implementation consists of adding the new vector cost model, the autovectorization patterns themselves and target hooks. This implementation only provides support for integer addition and subtraction as a proof of concept. This patch set should not be construed to be feature complete. Based on conversations with the community these patches are intended to lay the groundwork for feature completion and collaboration within the RISC-V community. These patches are largely based off the work of Juzhe Zhong (juzhe.zhong@rivai.ai) of RiVAI. More specifically the rvv-next branch at: https://github.com/riscv-collab/riscv-gcc.git is the foundation of this patch set. As discussed on this list, if these patches are approved they will be merged into a "auto-vectorization" branch once gcc-13 branches for release. There are two known issues related to crashes (assert failures) associated with tree vectorization; one of which I have sent a patch for and have received feedback. Changes in v3: - Removed the cost model and cost hooks based on feedback from Richard Biener - Used RVV_VUNDEF macro to fix failing patterns Changes in v2 - Updated ChangeLog entry to include RiVAI contributions - Fixed ChangeLog email formatting - Fixed gnu formatting issues in the code Michael Collison (6): RISC-V: Add new predicates and function prototypes RISC-V: autovec: Export policy functions to global scope RISC-V:autovec: Add auto-vectorization support functions RISC-V:autovec: Add target vectorization hooks RISC-V:autovec: Add autovectorization patterns for add & sub RISC-V:autovec: Add autovectorization tests for add & sub gcc/config/riscv/predicates.md | 13 ++ gcc/config/riscv/riscv-opts.h | 40 ++++ gcc/config/riscv/riscv-protos.h | 15 ++ gcc/config/riscv/riscv-v.cc | 178 +++++++++++++++++- gcc/config/riscv/riscv-vector-builtins.cc | 4 +- gcc/config/riscv/riscv-vector-builtins.h | 2 + gcc/config/riscv/riscv.cc | 156 +++++++++++++++ gcc/config/riscv/riscv.md | 1 + gcc/config/riscv/riscv.opt | 20 ++ gcc/config/riscv/vector-auto.md | 172 +++++++++++++++++ gcc/config/riscv/vector-iterators.md | 2 + gcc/config/riscv/vector.md | 4 +- .../riscv/rvv/autovec/loop-add-rv32.c | 24 +++ .../gcc.target/riscv/rvv/autovec/loop-add.c | 24 +++ .../riscv/rvv/autovec/loop-sub-rv32.c | 24 +++ .../gcc.target/riscv/rvv/autovec/loop-sub.c | 24 +++ 16 files changed, 698 insertions(+), 5 deletions(-) create mode 100644 gcc/config/riscv/vector-auto.md create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c -- 2.34.1