From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-qt1-x836.google.com (mail-qt1-x836.google.com [IPv6:2607:f8b0:4864:20::836]) by sourceware.org (Postfix) with ESMTPS id ABF403858422 for ; Wed, 8 Mar 2023 03:27:43 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org ABF403858422 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivosinc.com Received: by mail-qt1-x836.google.com with SMTP id l18so16956892qtp.1 for ; Tue, 07 Mar 2023 19:27:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; t=1678246063; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=5LMCw3PjEnPTSnKCJqcsP4avCMYuQ1QiRzrBpsOwOw0=; b=mYML3stm4pnHGEraNs3GrLf3KyNo3IaJ2z4wWDNWIpsf8op7QXROw1Fzf4HMOQ/DSv KF9PkUlmJP+vnRB2xUigZ7ciGKIc9SQgL+YsMsTILZqIq3Rb9ryxgidHnopnabeAF4+U zIuWfoNj1PBfC8nWnq9Nncla6T8tU8cm2gXfa98fg7Ypnpz/izpFOeuqq6r2TANgn3gw Y4fzbm/6hq0jqlsBXqegbYU07v0HM/IjFa5qdfb730GC4ecRROB5zM1UEZv0H0xbyNQ3 2tgSGnxUSHXuAExy4yichslKb3i90NskPBzNsVQILTx3km4GjL4K2S2Hhc3/4AENwm/o FCXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678246063; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5LMCw3PjEnPTSnKCJqcsP4avCMYuQ1QiRzrBpsOwOw0=; b=KFig/6nETM9goul/EPICIDsQLVwR62OIKoqmDfK2rCUS8rXNsVF8crNfppcu5QmC7i JVMC2vV06wJtw18qXH6+iw2J1ySjJINlpyFZEVZ+ZW486FrGDWwcQY7fR77ZPVWUFPPH hPOMk+x3G+ZHxurAjP1cy+ovxVi7L1kHkB8SUHAhpvvzZlLGcgKMkcq8ASJIU5PA5viv O27Y5DwntUlJaSBqn4yAmO3VssQehcE64WyD1NhhQEPDW88dS43c3OSaI7Gcp0AMLyYh Adni7IBiBIffj+BTjT871HFFsJegI31XybwjcZg/dhBSm5cJz6xylr8AoK1RLVly1ELw rnPw== X-Gm-Message-State: AO0yUKX59Kia7UgwNd+dOAk7G4/TAkWfmZMJmJxV9g0MLJayV+2frY4E 61QDq+ZxguNS5n8Vj61SOonkW8YU3l/5CgNajo0= X-Google-Smtp-Source: AK7set8jWlc9rI2MicGalw+hcVZ8kxNwS3mDG6uZdDftMstvNgM+ogL1dGfhPHX4C/oY/OcE/i15XQ== X-Received: by 2002:ac8:5952:0:b0:3ac:1bd5:b7ad with SMTP id 18-20020ac85952000000b003ac1bd5b7admr27238849qtz.33.1678246062742; Tue, 07 Mar 2023 19:27:42 -0800 (PST) Received: from system76-pc.ba.rivosinc.com ([136.57.172.92]) by smtp.gmail.com with ESMTPSA id v21-20020ac87295000000b003b6382f66b1sm10759696qto.29.2023.03.07.19.27.42 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Mar 2023 19:27:42 -0800 (PST) From: Michael Collison To: gcc-patches@gcc.gnu.org Subject: [PATCH v3 1/6] RISC-V: autovec: Add new predicates and function prototypes Date: Tue, 7 Mar 2023 22:27:35 -0500 Message-Id: <20230308032740.989275-2-collison@rivosinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230308032740.989275-1-collison@rivosinc.com> References: <20230308032740.989275-1-collison@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-12.3 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,GIT_PATCH_0,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: 2023-03-02 Michael Collison Juzhe Zhong * config/riscv/riscv-protos.h (riscv_classify_vlmul_field): New external declaration. (riscv_vector_preferred_simd_mode): Ditto. (riscv_tuple_mode_p): Ditto. (riscv_vector_mask_mode_p): Ditto. (riscv_classify_nf): Ditto. (riscv_vlmul_regsize): Ditto. (riscv_vector_preferred_simd_mode): Ditto. (riscv_vector_get_mask_mode): Ditto. (emit_vlmax_vsetvl): Ditto. (get_mask_policy_no_pred): Ditto. (get_tail_policy_no_pred): Ditto. * config/riscv/riscv-opts.h (riscv_vector_bits_enum): New enum. (riscv_vector_lmul_enum): Ditto. (vlmul_field_enum): Ditto. * config/riscv/riscv-v.cc (emit_vlmax_vsetvl): Remove static scope. * config/riscv/riscv.opt (riscv_vector_lmul): New option -mriscv_vector_lmul. * config/riscv/predicates.md (p_reg_or_const_csr_operand): New predicate. (vector_reg_or_const_dup_operand): Ditto. --- gcc/config/riscv/predicates.md | 13 +++++++++++ gcc/config/riscv/riscv-opts.h | 40 +++++++++++++++++++++++++++++++++ gcc/config/riscv/riscv-protos.h | 15 +++++++++++++ gcc/config/riscv/riscv-v.cc | 2 +- gcc/config/riscv/riscv.opt | 20 +++++++++++++++++ 5 files changed, 89 insertions(+), 1 deletion(-) diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md index 0d9d7701c7e..19aa5e12920 100644 --- a/gcc/config/riscv/predicates.md +++ b/gcc/config/riscv/predicates.md @@ -264,6 +264,14 @@ }) ;; Predicates for the V extension. +(define_special_predicate "p_reg_or_const_csr_operand" + (match_code "reg, subreg, const_int") +{ + if (CONST_INT_P (op)) + return satisfies_constraint_K (op); + return GET_MODE (op) == Pmode; +}) + (define_special_predicate "vector_length_operand" (ior (match_operand 0 "pmode_register_operand") (match_operand 0 "const_csr_operand"))) @@ -291,6 +299,11 @@ (and (match_code "const_vector") (match_test "rtx_equal_p (op, riscv_vector::gen_scalar_move_mask (GET_MODE (op)))"))) +(define_predicate "vector_reg_or_const_dup_operand" + (ior (match_operand 0 "register_operand") + (match_test "const_vec_duplicate_p (op) + && !CONST_POLY_INT_P (CONST_VECTOR_ELT (op, 0))"))) + (define_predicate "vector_mask_operand" (ior (match_operand 0 "register_operand") (match_operand 0 "vector_all_trues_mask_operand"))) diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index ff398c0a2ae..c6b6d84fce4 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -67,6 +67,46 @@ enum stack_protector_guard { SSP_GLOBAL /* global canary */ }; +/* RVV vector register sizes. */ +enum riscv_vector_bits_enum +{ + RVV_SCALABLE, + RVV_NOT_IMPLEMENTED = RVV_SCALABLE, + RVV_64 = 64, + RVV_128 = 128, + RVV_256 = 256, + RVV_512 = 512, + RVV_1024 = 1024, + RVV_2048 = 2048, + RVV_4096 = 4096, + RVV_8192 = 8192, + RVV_16384 = 16384, + RVV_32768 = 32768, + RVV_65536 = 65536 +}; + +/* vectorization factor. */ +enum riscv_vector_lmul_enum +{ + RVV_LMUL1 = 1, + RVV_LMUL2 = 2, + RVV_LMUL4 = 4, + RVV_LMUL8 = 8 +}; + +enum vlmul_field_enum +{ + VLMUL_FIELD_000, /* LMUL = 1. */ + VLMUL_FIELD_001, /* LMUL = 2. */ + VLMUL_FIELD_010, /* LMUL = 4. */ + VLMUL_FIELD_011, /* LMUL = 8. */ + VLMUL_FIELD_100, /* RESERVED. */ + VLMUL_FIELD_101, /* LMUL = 1/8. */ + VLMUL_FIELD_110, /* LMUL = 1/4. */ + VLMUL_FIELD_111, /* LMUL = 1/2. */ + MAX_VLMUL_FIELD +}; + #define MASK_ZICSR (1 << 0) #define MASK_ZIFENCEI (1 << 1) diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 88a6bf5442f..6a486a1cd61 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -217,4 +217,19 @@ const unsigned int RISCV_BUILTIN_SHIFT = 1; /* Mask that selects the riscv_builtin_class part of a function code. */ const unsigned int RISCV_BUILTIN_CLASS = (1 << RISCV_BUILTIN_SHIFT) - 1; +/* Routines implemented in riscv-v.cc. */ + +namespace riscv_vector { +extern unsigned int riscv_classify_vlmul_field (enum machine_mode m); +extern machine_mode riscv_vector_preferred_simd_mode (scalar_mode mode, + unsigned vf); +extern bool riscv_tuple_mode_p (machine_mode); +extern bool riscv_vector_mask_mode_p (machine_mode); +extern int riscv_classify_nf (machine_mode); +extern int riscv_vlmul_regsize (machine_mode); +extern opt_machine_mode riscv_vector_get_mask_mode (machine_mode mode); +extern rtx emit_vlmax_vsetvl (machine_mode vmode); +extern rtx get_mask_policy_no_pred (); +extern rtx get_tail_policy_no_pred (); +} #endif /* ! GCC_RISCV_PROTOS_H */ diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index d65c65b26cd..2d2de6e4a6c 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -109,7 +109,7 @@ const_vec_all_same_in_range_p (rtx x, HOST_WIDE_INT minval, && IN_RANGE (INTVAL (elt), minval, maxval)); } -static rtx +rtx emit_vlmax_vsetvl (machine_mode vmode) { rtx vl = gen_reg_rtx (Pmode); diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index 95535235354..27005fb0f4a 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -70,6 +70,26 @@ Enum(abi_type) String(lp64f) Value(ABI_LP64F) EnumValue Enum(abi_type) String(lp64d) Value(ABI_LP64D) +Enum +Name(riscv_vector_lmul) Type(enum riscv_vector_lmul_enum) +The possible vectorization factor: + +EnumValue +Enum(riscv_vector_lmul) String(1) Value(RVV_LMUL1) + +EnumValue +Enum(riscv_vector_lmul) String(2) Value(RVV_LMUL2) + +EnumValue +Enum(riscv_vector_lmul) String(4) Value(RVV_LMUL4) + +EnumValue +Enum(riscv_vector_lmul) String(8) Value(RVV_LMUL8) + +mriscv-vector-lmul= +Target RejectNegative Joined Enum(riscv_vector_lmul) Var(riscv_vector_lmul) Init(RVV_LMUL1) +-mriscv-vector-lmul= Set the vf using lmul in auto-vectorization. + mfdiv Target Mask(FDIV) Use hardware floating-point divide and square root instructions. -- 2.34.1