From: juzhe.zhong@rivai.ai
To: gcc-patches@gcc.gnu.org
Cc: kito.cheng@gmail.com, rguenther@suse.de, jeffreyalaw@gmail.com,
richard.sandiford@arm.com, Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
Subject: [PATCH] Extend nops num in "maybe_gen_insn" for RISC-V Vector intrinsics
Date: Wed, 8 Mar 2023 15:42:13 +0800 [thread overview]
Message-ID: <20230308074213.97404-1-juzhe.zhong@rivai.ai> (raw)
From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
Hi, current maybe_gen_insn can only expand 9 nops.
For RVV intrinsics, I need to extend it as 10, otherwise I should use GEN_FCN.
This patch is quite obvious change, Ok for trunk ?
Thanks.
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins.cc (function_expander::use_ternop_insn): Use maybe_gen_insn instead.
(function_expander::use_widen_ternop_insn): Ditto.
* optabs.cc (maybe_gen_insn): Extend nops handling.
---
gcc/config/riscv/riscv-vector-builtins.cc | 24 ++---------------------
gcc/optabs.cc | 5 +++++
2 files changed, 7 insertions(+), 22 deletions(-)
diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc
index 60381cfe98f..fcda3863576 100644
--- a/gcc/config/riscv/riscv-vector-builtins.cc
+++ b/gcc/config/riscv/riscv-vector-builtins.cc
@@ -3154,17 +3154,7 @@ function_expander::use_ternop_insn (bool vd_accum_p, insn_code icode)
add_input_operand (Pmode, get_tail_policy_for_pred (pred));
add_input_operand (Pmode, get_mask_policy_for_pred (pred));
add_input_operand (Pmode, get_avl_type_rtx (avl_type::NONVLMAX));
-
- /* See optabs.cc, the maximum nops is 9 for using 'maybe_gen_insn'.
- We temporarily use GCN directly. We will change it back it we
- can support nops >= 10. */
- gcc_assert (maybe_legitimize_operands (icode, 0, opno, m_ops));
- rtx_insn *pat = GEN_FCN (
- icode) (m_ops[0].value, m_ops[1].value, m_ops[2].value, m_ops[3].value,
- m_ops[4].value, m_ops[5].value, m_ops[6].value, m_ops[7].value,
- m_ops[8].value, m_ops[9].value);
- emit_insn (pat);
- return m_ops[0].value;
+ return generate_insn (icode);
}
/* Implement the call using instruction ICODE, with a 1:1 mapping between
@@ -3196,17 +3186,7 @@ function_expander::use_widen_ternop_insn (insn_code icode)
add_input_operand (Pmode, get_tail_policy_for_pred (pred));
add_input_operand (Pmode, get_mask_policy_for_pred (pred));
add_input_operand (Pmode, get_avl_type_rtx (avl_type::NONVLMAX));
-
- /* See optabs.cc, the maximum nops is 9 for using 'maybe_gen_insn'.
- We temporarily use GCN directly. We will change it back it we
- can support nops >= 10. */
- gcc_assert (maybe_legitimize_operands (icode, 0, opno, m_ops));
- rtx_insn *pat = GEN_FCN (
- icode) (m_ops[0].value, m_ops[1].value, m_ops[2].value, m_ops[3].value,
- m_ops[4].value, m_ops[5].value, m_ops[6].value, m_ops[7].value,
- m_ops[8].value, m_ops[9].value);
- emit_insn (pat);
- return m_ops[0].value;
+ return generate_insn (icode);
}
/* Implement the call using instruction ICODE, with a 1:1 mapping between
diff --git a/gcc/optabs.cc b/gcc/optabs.cc
index cf22bfec3f5..4c641cab192 100644
--- a/gcc/optabs.cc
+++ b/gcc/optabs.cc
@@ -8091,6 +8091,11 @@ maybe_gen_insn (enum insn_code icode, unsigned int nops,
return GEN_FCN (icode) (ops[0].value, ops[1].value, ops[2].value,
ops[3].value, ops[4].value, ops[5].value,
ops[6].value, ops[7].value, ops[8].value);
+ case 10:
+ return GEN_FCN (icode) (ops[0].value, ops[1].value, ops[2].value,
+ ops[3].value, ops[4].value, ops[5].value,
+ ops[6].value, ops[7].value, ops[8].value,
+ ops[9].value);
}
gcc_unreachable ();
}
--
2.36.1
next reply other threads:[~2023-03-08 7:42 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-08 7:42 juzhe.zhong [this message]
2023-03-08 7:49 ` Richard Biener
2023-03-10 8:26 ` Kito Cheng
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