From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from smtpbgbr1.qq.com (smtpbgbr1.qq.com [54.207.19.206]) by sourceware.org (Postfix) with ESMTPS id D2A4F3858C30 for ; Wed, 8 Mar 2023 07:42:24 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org D2A4F3858C30 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp65t1678261336tfqdoaji Received: from server1.localdomain ( [58.60.1.22]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 08 Mar 2023 15:42:15 +0800 (CST) X-QQ-SSF: 01400000000000E0N000000A0000000 X-QQ-FEAT: CR3LFp2JE4nlqqxxJGlnDq82riclwGVqvaN0ZcPTS7e9A38+42vTXVuQNVeZK ebslANUfrg2IzsD6mnVWq1tExqQVYd783sycXuvqbhLqqsuyE5yh0A9DHfqprnwXJf1bqN8 1xLnhY9R+Xwye2JV0bfX3NaBootxH/usCHRDIcnhCzJLl0SV/s39oRkKexB6RyuX4YLvEeN CswEeKEGOVwJDcJWMGhBcqMRhwrePLD0lxRJEJMI0LFOucqaPh59JqlGtLru3dSk2REoCos PfItdU+Ix6cLpc6n+kMWdbpyIloP15+Ow5hvTQCOptpttBtyVc1VbwAamrSzkYl3Y5JUajG lNykGv9Aolx5UB5Ze1E3sKZ/DAHVb0S4/AEHTGXJkicF1DWxVZMa7NBAioUmvpRAHYzB3DQ X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, rguenther@suse.de, jeffreyalaw@gmail.com, richard.sandiford@arm.com, Ju-Zhe Zhong Subject: [PATCH] Extend nops num in "maybe_gen_insn" for RISC-V Vector intrinsics Date: Wed, 8 Mar 2023 15:42:13 +0800 Message-Id: <20230308074213.97404-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-11.0 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,RCVD_IN_BARRACUDACENTRAL,RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Ju-Zhe Zhong Hi, current maybe_gen_insn can only expand 9 nops. For RVV intrinsics, I need to extend it as 10, otherwise I should use GEN_FCN. This patch is quite obvious change, Ok for trunk ? Thanks. gcc/ChangeLog: * config/riscv/riscv-vector-builtins.cc (function_expander::use_ternop_insn): Use maybe_gen_insn instead. (function_expander::use_widen_ternop_insn): Ditto. * optabs.cc (maybe_gen_insn): Extend nops handling. --- gcc/config/riscv/riscv-vector-builtins.cc | 24 ++--------------------- gcc/optabs.cc | 5 +++++ 2 files changed, 7 insertions(+), 22 deletions(-) diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc index 60381cfe98f..fcda3863576 100644 --- a/gcc/config/riscv/riscv-vector-builtins.cc +++ b/gcc/config/riscv/riscv-vector-builtins.cc @@ -3154,17 +3154,7 @@ function_expander::use_ternop_insn (bool vd_accum_p, insn_code icode) add_input_operand (Pmode, get_tail_policy_for_pred (pred)); add_input_operand (Pmode, get_mask_policy_for_pred (pred)); add_input_operand (Pmode, get_avl_type_rtx (avl_type::NONVLMAX)); - - /* See optabs.cc, the maximum nops is 9 for using 'maybe_gen_insn'. - We temporarily use GCN directly. We will change it back it we - can support nops >= 10. */ - gcc_assert (maybe_legitimize_operands (icode, 0, opno, m_ops)); - rtx_insn *pat = GEN_FCN ( - icode) (m_ops[0].value, m_ops[1].value, m_ops[2].value, m_ops[3].value, - m_ops[4].value, m_ops[5].value, m_ops[6].value, m_ops[7].value, - m_ops[8].value, m_ops[9].value); - emit_insn (pat); - return m_ops[0].value; + return generate_insn (icode); } /* Implement the call using instruction ICODE, with a 1:1 mapping between @@ -3196,17 +3186,7 @@ function_expander::use_widen_ternop_insn (insn_code icode) add_input_operand (Pmode, get_tail_policy_for_pred (pred)); add_input_operand (Pmode, get_mask_policy_for_pred (pred)); add_input_operand (Pmode, get_avl_type_rtx (avl_type::NONVLMAX)); - - /* See optabs.cc, the maximum nops is 9 for using 'maybe_gen_insn'. - We temporarily use GCN directly. We will change it back it we - can support nops >= 10. */ - gcc_assert (maybe_legitimize_operands (icode, 0, opno, m_ops)); - rtx_insn *pat = GEN_FCN ( - icode) (m_ops[0].value, m_ops[1].value, m_ops[2].value, m_ops[3].value, - m_ops[4].value, m_ops[5].value, m_ops[6].value, m_ops[7].value, - m_ops[8].value, m_ops[9].value); - emit_insn (pat); - return m_ops[0].value; + return generate_insn (icode); } /* Implement the call using instruction ICODE, with a 1:1 mapping between diff --git a/gcc/optabs.cc b/gcc/optabs.cc index cf22bfec3f5..4c641cab192 100644 --- a/gcc/optabs.cc +++ b/gcc/optabs.cc @@ -8091,6 +8091,11 @@ maybe_gen_insn (enum insn_code icode, unsigned int nops, return GEN_FCN (icode) (ops[0].value, ops[1].value, ops[2].value, ops[3].value, ops[4].value, ops[5].value, ops[6].value, ops[7].value, ops[8].value); + case 10: + return GEN_FCN (icode) (ops[0].value, ops[1].value, ops[2].value, + ops[3].value, ops[4].value, ops[5].value, + ops[6].value, ops[7].value, ops[8].value, + ops[9].value); } gcc_unreachable (); } -- 2.36.1