From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by sourceware.org (Postfix) with ESMTPS id 9958F3858C5E for ; Fri, 10 Mar 2023 06:00:25 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 9958F3858C5E Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=marvell.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=marvell.com Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 32A5bsok025800 for ; Thu, 9 Mar 2023 22:00:24 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=vmLzYvgPQPUqKizoAXJ2H+BHlEg/7y1egimYidmx0zg=; b=LHWhMWSZ29Z+VYggVRpWV390qVf5B1SlHMrt7O9Gcuu2FRsga5pHIz6Ah2SPMdVcVD15 Jmd/8QAoqkSo9EBgfaNisnGsfGPIcKeVRqULE4PDy2PBxW4Rn1ayjANzmiuHb/xt3X8C fxenI+H6QAaxiSkduVOxHolmLfiO4qgCWjrfwtwovDEfswlnPLlCzUPxKEeHajUtYj7J HBuNRP1CLvYuPExoDE+3rT1FSzOxXr6ss3C1JiAzeshVXrxaLJQmov838UtQAOuuWLwG 8fXYWg15d5PHY7GsZzgwH9uLXkbl92YDAXgTycKopwFPHPU4UYXxRZasxvMbIELFQWYu rw== Received: from dc5-exch01.marvell.com ([199.233.59.181]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3p7n7dhnes-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 09 Mar 2023 22:00:24 -0800 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 9 Mar 2023 22:00:22 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.42 via Frontend Transport; Thu, 9 Mar 2023 22:00:22 -0800 Received: from vpnclient.wrightpinski.org.com (unknown [10.69.242.67]) by maili.marvell.com (Postfix) with ESMTP id C7BAD5C68E6; Thu, 9 Mar 2023 22:00:16 -0800 (PST) From: Andrew Pinski To: CC: Andrew Pinski Subject: [PATCH] Fix PR 108874: aarch64 code regression with shift and ands Date: Thu, 9 Mar 2023 21:59:47 -0800 Message-ID: <20230310055947.2918320-1-apinski@marvell.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: f36KTyZEyuHXPDf1ER_VSuIU63iNeUYv X-Proofpoint-ORIG-GUID: f36KTyZEyuHXPDf1ER_VSuIU63iNeUYv X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-10_02,2023-03-09_01,2023-02-09_01 X-Spam-Status: No, score=-14.6 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: After r6-2044-g98e30e515f184b, code like "((x & 0xff00ff00U) >> 8)" would be optimized like (x >> 8) & 0xff00ffU which is normally better except on aarch64, the shift right could be combined with another operation in some cases. So we need to add a few define_splits to the aarch64 backends that match "((x >> shift) & CST0) OP Y" and splits it to: TMP = X & CST1 (TMP >> shift) OP Y Note this also gets us to matching rev16 back too so I added a testcase to make sure we don't lose that matching any more. Note when the generic patch to recognize those as bswap ROT 16, we might regress again and need to add a few more patterns to the aarch64 backend but will deal with that once that happens. OK? Bootstrapped and tested on aarch64 with no regressions. gcc/ChangeLog: * config/aarch64/aarch64.md: Add a new define_split to help combine. gcc/testsuite/ChangeLog: * gcc.target/aarch64/rev16_2.c: New test. * gcc.target/aarch64/shift_and_operator-1.c: New test. --- gcc/config/aarch64/aarch64.md | 21 ++++++++++ gcc/testsuite/gcc.target/aarch64/rev16_2.c | 39 +++++++++++++++++++ .../gcc.target/aarch64/shift_and_operator-1.c | 22 +++++++++++ 3 files changed, 82 insertions(+) create mode 100644 gcc/testsuite/gcc.target/aarch64/rev16_2.c create mode 100644 gcc/testsuite/gcc.target/aarch64/shift_and_operator-1.c diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index af9087508ac..41cc563f10c 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -4656,6 +4656,27 @@ (define_insn "*_3" [(set_attr "type" "logic_shift_imm")] ) +(define_split + [(set (match_operand:GPI 0 "register_operand") + (LOGICAL_OR_PLUS:GPI + (and:GPI + (lshiftrt:GPI (match_operand:GPI 1 "register_operand") + (match_operand:QI 2 "aarch64_shift_imm_")) + (match_operand:GPI 3 "aarch64_logical_immediate")) + (match_operand:GPI 4 "register_operand")))] + "can_create_pseudo_p () + && aarch64_bitmask_imm (UINTVAL (operands[3]) << UINTVAL (operands[2]), mode)" + [(set (match_dup 5) (and:GPI (match_dup 1) (match_dup 6))) + (set (match_dup 0) (match_dup 7))] + { + operands[5] = gen_reg_rtx (mode); + operands[6] = gen_int_mode (UINTVAL (operands[3]) << UINTVAL (operands[2]), mode); + rtx shift = gen_rtx_LSHIFTRT (mode, operands[5], operands[2]); + rtx_code new_code = ; + operands[7] = gen_rtx_fmt_ee (new_code, mode, shift, operands[4]); + } +) + (define_split [(set (match_operand:GPI 0 "register_operand") (LOGICAL_OR_PLUS:GPI diff --git a/gcc/testsuite/gcc.target/aarch64/rev16_2.c b/gcc/testsuite/gcc.target/aarch64/rev16_2.c new file mode 100644 index 00000000000..621eb5dfbf0 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/rev16_2.c @@ -0,0 +1,39 @@ +/* { dg-options "-O2" } */ +/* { dg-do compile } */ + +extern void abort (void); + +typedef unsigned int __u32; + +__u32 +__rev16_32_alt (__u32 x) +{ + return (((__u32)(x) & (__u32)0xff00ff00UL) >> 8) + | (((__u32)(x) & (__u32)0x00ff00ffUL) << 8); +} + +__u32 +__rev16_32 (__u32 x) +{ + return (((__u32)(x) & (__u32)0x00ff00ffUL) << 8) + | (((__u32)(x) & (__u32)0xff00ff00UL) >> 8); +} + +typedef unsigned long long __u64; + +__u64 +__rev16_64_alt (__u64 x) +{ + return (((__u64)(x) & (__u64)0xff00ff00ff00ff00UL) >> 8) + | (((__u64)(x) & (__u64)0x00ff00ff00ff00ffUL) << 8); +} + +__u64 +__rev16_64 (__u64 x) +{ + return (((__u64)(x) & (__u64)0x00ff00ff00ff00ffUL) << 8) + | (((__u64)(x) & (__u64)0xff00ff00ff00ff00UL) >> 8); +} + +/* { dg-final { scan-assembler-times "rev16\\tx\[0-9\]+" 2 } } */ +/* { dg-final { scan-assembler-times "rev16\\tw\[0-9\]+" 2 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/shift_and_operator-1.c b/gcc/testsuite/gcc.target/aarch64/shift_and_operator-1.c new file mode 100644 index 00000000000..49152c5495a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/shift_and_operator-1.c @@ -0,0 +1,22 @@ +/* { dg-options "-O2" } */ +/* { dg-do compile } */ + +unsigned f(unsigned x, unsigned b) +{ + return ((x & 0xff00ff00U) >> 8) | b; +} + +unsigned f0(unsigned x, unsigned b) +{ + return ((x & 0xff00ff00U) >> 8) ^ b; +} +unsigned f1(unsigned x, unsigned b) +{ + return ((x & 0xff00ff00U) >> 8) + b; +} + +/* { dg-final { scan-assembler-times "lsr\\tw\[0-9\]+" 0 } } */ +/* { dg-final { scan-assembler-times "lsr 8" 3 } } */ +/* { dg-final { scan-assembler-times "eor\\tw\[0-9\]+" 1 } } */ +/* { dg-final { scan-assembler-times "add\\tw\[0-9\]+" 1 } } */ +/* { dg-final { scan-assembler-times "orr\\tw\[0-9\]+" 1 } } */ -- 2.31.1