From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by sourceware.org (Postfix) with ESMTPS id B2DD03858D1E for ; Sat, 11 Mar 2023 01:28:02 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org B2DD03858D1E Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=marvell.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=marvell.com Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 32ANgJFu007315 for ; Fri, 10 Mar 2023 17:28:01 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=7gRLQMDtPYcgW5Xe+SQsy0I9ROuSOBqBeNoOcYSyJDg=; b=kvSf6TcE2CjUZrd5MSpvPlBj4xovYDKrskJUBdAOuLhKd2BZQryM+ruDMO0wJp6yo0K1 NaqPJlSpqN8T+qu9faKekP61FJpP4pSN6Vqjg1DAQtCIHKdQ5rF25EkzmyKwLURyhxBO b7eStUaRKNctJm4GvRtC3W434UtNBNrK4paqWQT6njWmO1KAh5aSfH6wznhCvPm/PriC 7h1CXw5ekO8sGnDusXFq2S2rBrIuVZMGLDILEUlSyF5TJTnFQGHsRDHwPc9U4zcU26u2 L9upa+8X+CqdxytuUmmNc/dJviMa08I1xFGlnzuS+ECphf7kesBmXoUBX4QV8DE79hov WQ== Received: from dc5-exch02.marvell.com ([199.233.59.182]) by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3p80k7cqf8-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Fri, 10 Mar 2023 17:28:01 -0800 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 10 Mar 2023 17:27:59 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.42 via Frontend Transport; Fri, 10 Mar 2023 17:27:58 -0800 Received: from vpnclient.wrightpinski.org.com (unknown [10.76.242.80]) by maili.marvell.com (Postfix) with ESMTP id 708953F704D; Fri, 10 Mar 2023 17:27:58 -0800 (PST) From: Andrew Pinski To: CC: Andrew Pinski Subject: [COMMITTED/12] Fix PR 105532: match.pd patterns calling tree_nonzero_bits with vector types Date: Fri, 10 Mar 2023 17:27:49 -0800 Message-ID: <20230311012749.2949900-1-apinski@marvell.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-GUID: 8CPhev1JKZxfyJGgndj1NgHKkqsg8Wzq X-Proofpoint-ORIG-GUID: 8CPhev1JKZxfyJGgndj1NgHKkqsg8Wzq X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-10_10,2023-03-10_01,2023-02-09_01 X-Spam-Status: No, score=-14.5 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE,SPF_NONE,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Even though this PR was reported with an ubsan issue, the problem is tree_nonzero_bits is being called with an expression which is a vector type. This fixes three patterns I noticed which does that. And adds a testcase for one of the patterns. Committed after a bootstrapped and tested on x86_64-linux-gnu with no regressions gcc/ChangeLog: PR tree-optimization/105532 * match.pd (~(X >> Y) -> ~X >> Y): Check if it is an integral type before calling tree_nonzero_bits. (popcount(X) + popcount(Y)): Likewise. (popcount(X&C1)): Likewise. gcc/testsuite/ChangeLog: * gcc.c-torture/compile/vector-shift-1.c: New test. (cherry picked from commit 193fccaa5c3525e979a989835c47c76d2c49d10c) --- gcc/match.pd | 25 +++++++++++-------- .../gcc.c-torture/compile/vector-shift-1.c | 8 ++++++ 2 files changed, 22 insertions(+), 11 deletions(-) create mode 100644 gcc/testsuite/gcc.c-torture/compile/vector-shift-1.c diff --git a/gcc/match.pd b/gcc/match.pd index ef352af1572..fc2833bbdca 100644 --- a/gcc/match.pd +++ b/gcc/match.pd @@ -1268,7 +1268,8 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT) /* For logical right shifts, this is possible only if @0 doesn't have MSB set and the logical right shift is changed into arithmetic shift. */ - (if (!wi::neg_p (tree_nonzero_bits (@0))) + (if (INTEGRAL_TYPE_P (type) + && !wi::neg_p (tree_nonzero_bits (@0))) (with { tree stype = signed_type_for (TREE_TYPE (@0)); } (convert (rshift (bit_not! (convert:stype @0)) @1)))))) #endif @@ -7169,7 +7170,8 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT) /* popcount(X) + popcount(Y) is popcount(X|Y) when X&Y must be zero. */ (simplify (plus (POPCOUNT:s @0) (POPCOUNT:s @1)) - (if (wi::bit_and (tree_nonzero_bits (@0), tree_nonzero_bits (@1)) == 0) + (if (INTEGRAL_TYPE_P (type) + && wi::bit_and (tree_nonzero_bits (@0), tree_nonzero_bits (@1)) == 0) (POPCOUNT (bit_ior @0 @1)))) /* popcount(X) == 0 is X == 0, and related (in)equalities. */ @@ -7201,15 +7203,16 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT) (for pfun (POPCOUNT PARITY) (simplify (pfun @0) - (with { wide_int nz = tree_nonzero_bits (@0); } - (switch - (if (nz == 1) - (convert @0)) - (if (wi::popcount (nz) == 1) - (with { tree utype = unsigned_type_for (TREE_TYPE (@0)); } - (convert (rshift:utype (convert:utype @0) - { build_int_cst (integer_type_node, - wi::ctz (nz)); })))))))) + (if (INTEGRAL_TYPE_P (type)) + (with { wide_int nz = tree_nonzero_bits (@0); } + (switch + (if (nz == 1) + (convert @0)) + (if (wi::popcount (nz) == 1) + (with { tree utype = unsigned_type_for (TREE_TYPE (@0)); } + (convert (rshift:utype (convert:utype @0) + { build_int_cst (integer_type_node, + wi::ctz (nz)); }))))))))) #if GIMPLE /* 64- and 32-bits branchless implementations of popcount are detected: diff --git a/gcc/testsuite/gcc.c-torture/compile/vector-shift-1.c b/gcc/testsuite/gcc.c-torture/compile/vector-shift-1.c new file mode 100644 index 00000000000..142ea56d5bb --- /dev/null +++ b/gcc/testsuite/gcc.c-torture/compile/vector-shift-1.c @@ -0,0 +1,8 @@ +typedef unsigned char __attribute__((__vector_size__ (1))) U; + +U +foo (U u) +{ + u = u == u; + return (~(u >> 255)); +} -- 2.17.1