[PATCH] RISC-V: Optimize zbb ins sext.b and sext.h in rv64

[Feng Wang <wangfeng@eswincomputing.com>]

This patch optimize the combine processing for sext.b/h in rv64.
Please refer to the following test case,
int sextb32(int x)
{ return (x << 24) >> 24; }

The rtl expression is as follows,
(insn 6 3 7 2 (set (reg:SI 138)
        (ashift:SI (subreg/s/u:SI (reg/v:DI 136 [ xD.2271 ]) 0)
            (const_int 24 [0x18]))) "sextb.c":2:13 195 {ashlsi3}
     (expr_list:REG_DEAD (reg/v:DI 136 [ xD.2271 ])
        (nil)))
(insn 7 6 8 2 (set (reg:SI 137)
        (ashiftrt:SI (reg:SI 138)
            (const_int 24 [0x18]))) "sextb.c":2:20 196 {ashrsi3}
     (expr_list:REG_DEAD (reg:SI 138)
        (nil)))

During the combine phase, they will combine into
(set (reg:SI 137)
    (ashiftrt:SI (subreg:SI (ashift:DI (reg:DI 140)
                (const_int 24 [0x18])) 0)
        (const_int 24 [0x18])))

The optimal combine result is
(set (reg:SI 137)
    (sign_extend:SI (subreg:QI (reg:DI 140) 0)))
This can be converted to the sext ins.

Due to the influence of subreg,the current processing
can't obtain the imm of left shifts. Need to peel off
another layer of rtl to obtain it.

gcc/ChangeLog:

        * combine.cc (extract_left_shift): Add SUBREG case.

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/zbb-sext-rv64.c: New test.
---
 gcc/combine.cc                                 |  5 +++++
 gcc/testsuite/gcc.target/riscv/zbb-sext-rv64.c | 12 ++++++++++++
 2 files changed, 17 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-sext-rv64.c

diff --git a/gcc/combine.cc b/gcc/combine.cc
index 053879500b7..fb396a3d974 100644
--- a/gcc/combine.cc
+++ b/gcc/combine.cc
@@ -7915,6 +7915,11 @@ extract_left_shift (scalar_int_mode mode, rtx x, int count)
 
   switch (code)
     {
+    case SUBREG:
+      x = XEXP (x, 0);
+      if (GET_CODE(x) != ASHIFT)
+        break;
+
     case ASHIFT:
       /* This is the shift itself.  If it is wide enough, we will return
 	 either the value being shifted if the shift count is equal to
diff --git a/gcc/testsuite/gcc.target/riscv/zbb-sext-rv64.c b/gcc/testsuite/gcc.target/riscv/zbb-sext-rv64.c
new file mode 100644
index 00000000000..4086ee56f57
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zbb-sext-rv64.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64g_zbb -mabi=lp64d -O2" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
+
+int sextb32(int x)
+{ return (x << 24) >> 24; }
+
+int sexth32(int x)
+{ return (x << 16) >> 16; }
+
+/* { dg-final { scan-assembler "sext.b" } } */
+/* { dg-final { scan-assembler "sext.h" } } */
\ No newline at end of file
-- 
2.17.1